1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Linux Kernel Additions:
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
93 - Added 802.3x MAC-layer flow control support
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
198 #define DRV_NAME "3c59x"
199 #define DRV_VERSION "LK1.1.19"
200 #define DRV_RELDATE "10 Nov 2002"
204 /* A few values that may be tweaked. */
205 /* Keep the ring sizes a power of two for efficiency. */
206 #define TX_RING_SIZE 16
207 #define RX_RING_SIZE 32
208 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
210 /* "Knobs" that adjust features and parameters. */
211 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
212 Setting to > 1512 effectively disables this feature. */
214 static int rx_copybreak = 200;
216 /* ARM systems perform better by disregarding the bus-master
217 transfer capability of these cards. -- rmk */
218 static int rx_copybreak = 1513;
220 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
221 static const int mtu = 1500;
222 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
223 static int max_interrupt_work = 32;
224 /* Tx timeout interval (millisecs) */
225 static int watchdog = 5000;
227 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
228 * of possible Tx stalls if the system is blocking interrupts
229 * somewhere else. Undefine this to disable.
231 #define tx_interrupt_mitigation 1
233 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
234 #define vortex_debug debug
236 static int vortex_debug = VORTEX_DEBUG;
238 static int vortex_debug = 1;
242 #error You must compile this file with the correct options!
243 #error See the last lines of the source file.
244 #error You must compile this driver with "-O".
247 #include <linux/config.h>
248 #include <linux/module.h>
249 #include <linux/kernel.h>
250 #include <linux/string.h>
251 #include <linux/timer.h>
252 #include <linux/errno.h>
253 #include <linux/in.h>
254 #include <linux/ioport.h>
255 #include <linux/slab.h>
256 #include <linux/interrupt.h>
257 #include <linux/pci.h>
258 #include <linux/mii.h>
259 #include <linux/init.h>
260 #include <linux/netdevice.h>
261 #include <linux/etherdevice.h>
262 #include <linux/skbuff.h>
263 #include <linux/ethtool.h>
264 #include <linux/highmem.h>
265 #include <linux/eisa.h>
266 #include <asm/irq.h> /* For NR_IRQS only. */
267 #include <asm/bitops.h>
269 #include <asm/uaccess.h>
271 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
272 This is only in the support-all-kernels source code. */
274 #define RUN_AT(x) (jiffies + (x))
276 #include <linux/delay.h>
279 static char version[] __devinitdata =
280 DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
282 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
283 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "
284 DRV_VERSION " " DRV_RELDATE);
285 MODULE_LICENSE("GPL");
287 MODULE_PARM(debug, "i");
288 MODULE_PARM(global_options, "i");
289 MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
290 MODULE_PARM(global_full_duplex, "i");
291 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
292 MODULE_PARM(hw_checksums, "1-" __MODULE_STRING(8) "i");
293 MODULE_PARM(flow_ctrl, "1-" __MODULE_STRING(8) "i");
294 MODULE_PARM(global_enable_wol, "i");
295 MODULE_PARM(enable_wol, "1-" __MODULE_STRING(8) "i");
296 MODULE_PARM(rx_copybreak, "i");
297 MODULE_PARM(max_interrupt_work, "i");
298 MODULE_PARM(compaq_ioaddr, "i");
299 MODULE_PARM(compaq_irq, "i");
300 MODULE_PARM(compaq_device_id, "i");
301 MODULE_PARM(watchdog, "i");
302 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
303 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
304 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
305 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
306 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if options is unset");
307 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
308 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
309 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
310 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if options is unset");
311 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
312 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
313 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
314 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
315 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
316 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
318 /* Operational parameter that usually are not changed. */
320 /* The Vortex size is twice that of the original EtherLinkIII series: the
321 runtime register window, window 1, is now always mapped in.
322 The Boomerang size is twice as large as the Vortex -- it has additional
323 bus master control registers. */
324 #define VORTEX_TOTAL_SIZE 0x20
325 #define BOOMERANG_TOTAL_SIZE 0x40
327 /* Set iff a MII transceiver on any interface requires mdio preamble.
328 This only set with the original DP83840 on older 3c905 boards, so the extra
329 code size of a per-interface flag is not worthwhile. */
330 static char mii_preamble_required;
332 #define PFX DRV_NAME ": "
339 I. Board Compatibility
341 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
342 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
343 versions of the FastEtherLink cards. The supported product IDs are
344 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
346 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
347 with the kernel source or available from
348 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
350 II. Board-specific settings
352 PCI bus devices are configured by the system at boot time, so no jumpers
353 need to be set on the board. The system BIOS should be set to assign the
354 PCI INTA signal to an otherwise unused system IRQ line.
356 The EEPROM settings for media type and forced-full-duplex are observed.
357 The EEPROM media type should be left at the default "autoselect" unless using
358 10base2 or AUI connections which cannot be reliably detected.
360 III. Driver operation
362 The 3c59x series use an interface that's very similar to the previous 3c5x9
363 series. The primary interface is two programmed-I/O FIFOs, with an
364 alternate single-contiguous-region bus-master transfer (see next).
366 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
367 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
368 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
369 programmed-I/O interface that has been removed in 'B' and subsequent board
372 One extension that is advertised in a very large font is that the adapters
373 are capable of being bus masters. On the Vortex chip this capability was
374 only for a single contiguous region making it far less useful than the full
375 bus master capability. There is a significant performance impact of taking
376 an extra interrupt or polling for the completion of each transfer, as well
377 as difficulty sharing the single transfer engine between the transmit and
378 receive threads. Using DMA transfers is a win only with large blocks or
379 with the flawed versions of the Intel Orion motherboard PCI controller.
381 The Boomerang chip's full-bus-master interface is useful, and has the
382 currently-unused advantages over other similar chips that queued transmit
383 packets may be reordered and receive buffer groups are associated with a
386 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
387 Rather than a fixed intermediate receive buffer, this scheme allocates
388 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
389 the copying breakpoint: it is chosen to trade-off the memory wasted by
390 passing the full-sized skbuff to the queue layer for all frames vs. the
391 copying cost of copying a frame to a correctly-sized skbuff.
393 IIIC. Synchronization
394 The driver runs as two independent, single-threaded flows of control. One
395 is the send-packet routine, which enforces single-threaded use by the
396 dev->tbusy flag. The other thread is the interrupt handler, which is single
397 threaded by the hardware and other software.
401 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
402 3c590, 3c595, and 3c900 boards.
403 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
404 the EISA version is called "Demon". According to Terry these names come
405 from rides at the local amusement park.
407 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
408 This driver only supports ethernet packets because of the skbuff allocation
412 /* This table drives the PCI probe routines. It's mostly boilerplate in all
413 of the drivers, and will likely be provided by some future kernel.
416 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
417 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
420 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
421 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
422 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
423 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
424 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
425 EXTRA_PREAMBLE=0x8000, };
476 /* note: this array directly indexed by above enums, and MUST
477 * be kept in sync with both the enums above, and the PCI device
480 static struct vortex_chip_info {
485 } vortex_info_tbl[] __devinitdata = {
486 {"3c590 Vortex 10Mbps",
487 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
488 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
489 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
490 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
491 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
492 {"3c595 Vortex 100baseTx",
493 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
494 {"3c595 Vortex 100baseT4",
495 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
497 {"3c595 Vortex 100base-MII",
498 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
499 {"3c900 Boomerang 10baseT",
500 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, },
501 {"3c900 Boomerang 10Mbps Combo",
502 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, },
503 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
504 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
505 {"3c900 Cyclone 10Mbps Combo",
506 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
508 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
509 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
510 {"3c900B-FL Cyclone 10base-FL",
511 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
512 {"3c905 Boomerang 100baseTx",
513 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, },
514 {"3c905 Boomerang 100baseT4",
515 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, },
516 {"3c905B Cyclone 100baseTx",
517 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
519 {"3c905B Cyclone 10/100/BNC",
520 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
521 {"3c905B-FX Cyclone 100baseFx",
522 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
524 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
525 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
526 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
528 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
531 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
532 {"3cSOHO100-TX Hurricane",
533 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
534 {"3c555 Laptop Hurricane",
535 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
536 {"3c556 Laptop Tornado",
537 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
539 {"3c556B Laptop Hurricane",
540 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
541 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
543 {"3c575 [Megahertz] 10/100 LAN CardBus",
544 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
545 {"3c575 Boomerang CardBus",
546 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
547 {"3CCFE575BT Cyclone CardBus",
548 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
549 INVERT_LED_PWR|HAS_HWCKSM, 128, },
550 {"3CCFE575CT Tornado CardBus",
551 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
552 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
553 {"3CCFE656 Cyclone CardBus",
554 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
555 INVERT_LED_PWR|HAS_HWCKSM, 128, },
557 {"3CCFEM656B Cyclone+Winmodem CardBus",
558 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
559 INVERT_LED_PWR|HAS_HWCKSM, 128, },
560 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
561 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
562 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
563 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
564 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
566 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
567 {"3c982 Hydra Dual Port A",
568 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
570 {"3c982 Hydra Dual Port B",
571 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
573 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
574 {"3c920B-EMB-WNM Tornado",
575 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
577 {0,}, /* 0 terminated list. */
581 static struct pci_device_id vortex_pci_tbl[] = {
582 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
583 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
584 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
585 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
586 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
588 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
589 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
590 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
591 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
592 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
594 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
595 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
596 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
597 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
598 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
600 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
601 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
602 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
603 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
604 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
605 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
607 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
608 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
609 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
610 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
611 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
613 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
614 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
615 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
616 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
617 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
619 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
620 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
621 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
622 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
623 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
625 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
626 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
628 {0,} /* 0 terminated list. */
630 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
633 /* Operational definitions.
634 These are not used by other compilation units and thus are not
635 exported in a ".h" file.
637 First the windows. There are eight register windows, with the command
638 and status registers available in each.
640 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
642 #define EL3_STATUS 0x0e
644 /* The top five bits written to EL3_CMD are a command, the lower
645 11 bits are the parameter, if applicable.
646 Note that 11 parameters bits was fine for ethernet, but the new chip
647 can handle FDDI length frames (~4500 octets) and now parameters count
648 32-bit 'Dwords' rather than octets. */
651 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
652 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
653 UpStall = 6<<11, UpUnstall = (6<<11)+1,
654 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
655 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
656 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
657 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
658 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
659 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
660 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
662 /* The SetRxFilter command accepts the following classes: */
664 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
666 /* Bits in the general status register. */
668 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
669 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
670 IntReq = 0x0040, StatsFull = 0x0080,
671 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
672 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
673 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
676 /* Register window 1 offsets, the window used in normal operation.
677 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
679 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
680 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
681 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
684 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
685 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
686 IntrStatus=0x0E, /* Valid in all windows. */
688 enum Win0_EEPROM_bits {
689 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
690 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
691 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
693 /* EEPROM locations. */
695 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
696 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
697 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
698 DriverTune=13, Checksum=15};
700 enum Window2 { /* Window 2. */
703 enum Window3 { /* Window 3: MAC/config bits. */
704 Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8,
707 #define BFEXT(value, offset, bitcount) \
708 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
710 #define BFINS(lhs, rhs, offset, bitcount) \
711 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
712 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
714 #define RAM_SIZE(v) BFEXT(v, 0, 3)
715 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
716 #define RAM_SPEED(v) BFEXT(v, 4, 2)
717 #define ROM_SIZE(v) BFEXT(v, 6, 2)
718 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
719 #define XCVR(v) BFEXT(v, 20, 4)
720 #define AUTOSELECT(v) BFEXT(v, 24, 1)
722 enum Window4 { /* Window 4: Xcvr/media bits. */
723 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
725 enum Win4_Media_bits {
726 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
727 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
728 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
729 Media_LnkBeat = 0x0800,
731 enum Window7 { /* Window 7: Bus Master control. */
732 Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
734 /* Boomerang bus master control registers. */
736 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
737 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
740 /* The Rx and Tx descriptor lists.
741 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
742 alignment contraint on tx_ring[] and rx_ring[]. */
743 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
744 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
745 struct boom_rx_desc {
746 u32 next; /* Last entry points to 0. */
748 u32 addr; /* Up to 63 addr/len pairs possible. */
749 s32 length; /* Set LAST_FRAG to indicate last pair. */
751 /* Values for the Rx status entry. */
752 enum rx_desc_status {
753 RxDComplete=0x00008000, RxDError=0x4000,
754 /* See boomerang_rx() for actual error bits */
755 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
756 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
760 #define DO_ZEROCOPY 1
762 #define DO_ZEROCOPY 0
765 struct boom_tx_desc {
766 u32 next; /* Last entry points to 0. */
767 s32 status; /* bits 0:12 length, others see below. */
772 } frag[1+MAX_SKB_FRAGS];
779 /* Values for the Tx status entry. */
780 enum tx_desc_status {
781 CRCDisable=0x2000, TxDComplete=0x8000,
782 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
783 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
786 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
787 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
789 struct vortex_private {
790 /* The Rx and Tx rings should be quad-word-aligned. */
791 struct boom_rx_desc* rx_ring;
792 struct boom_tx_desc* tx_ring;
793 dma_addr_t rx_ring_dma;
794 dma_addr_t tx_ring_dma;
795 /* The addresses of transmit- and receive-in-place skbuffs. */
796 struct sk_buff* rx_skbuff[RX_RING_SIZE];
797 struct sk_buff* tx_skbuff[TX_RING_SIZE];
798 unsigned int cur_rx, cur_tx; /* The next free ring entry */
799 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
800 struct net_device_stats stats;
801 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
802 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
804 /* PCI configuration space information. */
805 struct device *gendev;
806 char *cb_fn_base; /* CardBus function status addr space. */
808 /* Some values here only for performance evaluation and path-coverage */
809 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
812 /* The remainder are related to chip state, mostly media selection. */
813 struct timer_list timer; /* Media selection timer. */
814 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
815 int options; /* User-settable misc. driver options. */
816 unsigned int media_override:4, /* Passed-in media type. */
817 default_media:4, /* Read from the EEPROM/Wn3_Config. */
818 full_duplex:1, force_fd:1, autoselect:1,
819 bus_master:1, /* Vortex can only do a fragment bus-m. */
820 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
821 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
822 partner_flow_ctrl:1, /* Partner supports flow control */
824 enable_wol:1, /* Wake-on-LAN is enabled */
825 pm_state_valid:1, /* power_state[] has sane contents */
828 must_free_region:1; /* Flag: if zero, Cardbus owns the I/O region */
832 u16 available_media; /* From Wn3_Options. */
833 u16 capabilities, info1, info2; /* Various, from EEPROM. */
834 u16 advertising; /* NWay media advertisement */
835 unsigned char phys[2]; /* MII device addresses. */
836 u16 deferred; /* Resend these interrupts when we
837 * bale from the ISR */
838 u16 io_size; /* Size of PCI region (for release_region) */
839 spinlock_t lock; /* Serialise access to device & its vortex_private */
840 spinlock_t mdio_lock; /* Serialise access to mdio hardware */
845 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
847 #define DEVICE_PCI(dev) NULL
850 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
853 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
855 #define DEVICE_EISA(dev) NULL
858 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
860 /* The action to take with a media selection timer tick.
861 Note that we deviate from the 3Com order by checking 10base2 before AUI.
864 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
865 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
868 static struct media_table {
870 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
871 mask:8, /* The transceiver-present bit in Wn3_Config.*/
872 next:8; /* The media type to try next. */
873 int wait; /* Time before we check media status. */
875 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
876 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
877 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
878 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
879 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
880 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
881 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
882 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
883 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
884 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
885 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
888 static int vortex_probe1(struct device *gendev, long ioaddr, int irq,
889 int chip_idx, int card_idx);
890 static void vortex_up(struct net_device *dev);
891 static void vortex_down(struct net_device *dev, int final);
892 static int vortex_open(struct net_device *dev);
893 static void mdio_sync(long ioaddr, int bits);
894 static int mdio_read(struct net_device *dev, int phy_id, int location);
895 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
896 static void vortex_timer(unsigned long arg);
897 static void rx_oom_timer(unsigned long arg);
898 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
899 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
900 static int vortex_rx(struct net_device *dev);
901 static int boomerang_rx(struct net_device *dev);
902 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
903 static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
904 static int vortex_close(struct net_device *dev);
905 static void dump_tx_ring(struct net_device *dev);
906 static void update_stats(long ioaddr, struct net_device *dev);
907 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
908 static void set_rx_mode(struct net_device *dev);
909 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
910 static void vortex_tx_timeout(struct net_device *dev);
911 static void acpi_set_WOL(struct net_device *dev);
912 static struct ethtool_ops vortex_ethtool_ops;
914 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
915 /* Option count limit only -- unlimited interfaces are supported. */
917 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,};
918 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
919 static int hw_checksums[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
920 static int flow_ctrl[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
921 static int enable_wol[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
922 static int global_options = -1;
923 static int global_full_duplex = -1;
924 static int global_enable_wol = -1;
926 /* #define dev_alloc_skb dev_alloc_skb_debug */
928 /* Variables to work-around the Compaq PCI BIOS32 problem. */
929 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
930 static struct net_device *compaq_net_device;
932 static int vortex_cards_found;
934 #ifdef CONFIG_NET_POLL_CONTROLLER
935 static void poll_vortex(struct net_device *dev)
937 struct vortex_private *vp = (struct vortex_private *)dev->priv;
939 local_save_flags(flags);
941 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
942 local_irq_restore(flags);
948 static int vortex_suspend (struct pci_dev *pdev, u32 state)
950 struct net_device *dev = pci_get_drvdata(pdev);
952 if (dev && dev->priv) {
953 if (netif_running(dev)) {
954 netif_device_detach(dev);
961 static int vortex_resume (struct pci_dev *pdev)
963 struct net_device *dev = pci_get_drvdata(pdev);
965 if (dev && dev->priv) {
966 if (netif_running(dev)) {
968 netif_device_attach(dev);
974 #endif /* CONFIG_PM */
977 static struct eisa_device_id vortex_eisa_ids[] = {
978 { "TCM5920", CH_3C592 },
979 { "TCM5970", CH_3C597 },
983 static int vortex_eisa_probe (struct device *device);
984 static int vortex_eisa_remove (struct device *device);
986 static struct eisa_driver vortex_eisa_driver = {
987 .id_table = vortex_eisa_ids,
990 .probe = vortex_eisa_probe,
991 .remove = vortex_eisa_remove
995 static int vortex_eisa_probe (struct device *device)
998 struct eisa_device *edev;
1000 edev = to_eisa_device (device);
1001 ioaddr = edev->base_addr;
1003 if (!request_region(ioaddr, VORTEX_TOTAL_SIZE, DRV_NAME))
1006 if (vortex_probe1(device, ioaddr, inw(ioaddr + 0xC88) >> 12,
1007 edev->id.driver_data, vortex_cards_found)) {
1008 release_region (ioaddr, VORTEX_TOTAL_SIZE);
1012 vortex_cards_found++;
1017 static int vortex_eisa_remove (struct device *device)
1019 struct eisa_device *edev;
1020 struct net_device *dev;
1021 struct vortex_private *vp;
1024 edev = to_eisa_device (device);
1025 dev = eisa_get_drvdata (edev);
1028 printk("vortex_eisa_remove called for Compaq device!\n");
1032 vp = netdev_priv(dev);
1033 ioaddr = dev->base_addr;
1035 unregister_netdev (dev);
1036 outw (TotalReset|0x14, ioaddr + EL3_CMD);
1037 release_region (ioaddr, VORTEX_TOTAL_SIZE);
1044 /* returns count found (>= 0), or negative on error */
1045 static int __init vortex_eisa_init (void)
1048 int orig_cards_found = vortex_cards_found;
1051 if (eisa_driver_register (&vortex_eisa_driver) >= 0) {
1052 /* Because of the way EISA bus is probed, we cannot assume
1053 * any device have been found when we exit from
1054 * eisa_driver_register (the bus root driver may not be
1055 * initialized yet). So we blindly assume something was
1056 * found, and let the sysfs magic happend... */
1062 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1063 if (compaq_ioaddr) {
1064 vortex_probe1(NULL, compaq_ioaddr, compaq_irq,
1065 compaq_device_id, vortex_cards_found++);
1068 return vortex_cards_found - orig_cards_found + eisa_found;
1071 /* returns count (>= 0), or negative on error */
1072 static int __devinit vortex_init_one (struct pci_dev *pdev,
1073 const struct pci_device_id *ent)
1077 /* wake up and enable device */
1078 if (pci_enable_device (pdev)) {
1081 rc = vortex_probe1 (&pdev->dev, pci_resource_start (pdev, 0),
1082 pdev->irq, ent->driver_data, vortex_cards_found);
1084 vortex_cards_found++;
1090 * Start up the PCI/EISA device which is described by *gendev.
1091 * Return 0 on success.
1093 * NOTE: pdev can be NULL, for the case of a Compaq device
1095 static int __devinit vortex_probe1(struct device *gendev,
1096 long ioaddr, int irq,
1097 int chip_idx, int card_idx)
1099 struct vortex_private *vp;
1101 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1103 struct net_device *dev;
1104 static int printed_version;
1105 int retval, print_info;
1106 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1107 char *print_name = "3c59x";
1108 struct pci_dev *pdev = NULL;
1109 struct eisa_device *edev = NULL;
1111 if (!printed_version) {
1113 printed_version = 1;
1117 if ((pdev = DEVICE_PCI(gendev))) {
1118 print_name = pci_name(pdev);
1121 if ((edev = DEVICE_EISA(gendev))) {
1122 print_name = edev->dev.bus_id;
1126 dev = alloc_etherdev(sizeof(*vp));
1129 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1132 SET_MODULE_OWNER(dev);
1133 SET_NETDEV_DEV(dev, gendev);
1134 vp = netdev_priv(dev);
1136 option = global_options;
1138 /* The lower four bits are the media type. */
1139 if (dev->mem_start) {
1141 * The 'options' param is passed in as the third arg to the
1142 * LILO 'ether=' argument for non-modular use
1144 option = dev->mem_start;
1146 else if (card_idx < MAX_UNITS) {
1147 if (options[card_idx] >= 0)
1148 option = options[card_idx];
1152 if (option & 0x8000)
1154 if (option & 0x4000)
1156 if (option & 0x0400)
1160 print_info = (vortex_debug > 1);
1162 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1164 printk(KERN_INFO "%s: 3Com %s %s at 0x%lx. Vers " DRV_VERSION "\n",
1166 pdev ? "PCI" : "EISA",
1170 dev->base_addr = ioaddr;
1173 vp->drv_flags = vci->drv_flags;
1174 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1175 vp->io_size = vci->io_size;
1176 vp->card_idx = card_idx;
1178 /* module list only for Compaq device */
1179 if (gendev == NULL) {
1180 compaq_net_device = dev;
1183 /* PCI-only startup logic */
1185 /* EISA resources already marked, so only PCI needs to do this here */
1186 /* Ignore return value, because Cardbus drivers already allocate for us */
1187 if (request_region(ioaddr, vci->io_size, print_name) != NULL)
1188 vp->must_free_region = 1;
1190 /* enable bus-mastering if necessary */
1191 if (vci->flags & PCI_USES_MASTER)
1192 pci_set_master (pdev);
1194 if (vci->drv_flags & IS_VORTEX) {
1196 u8 new_latency = 248;
1198 /* Check the PCI latency value. On the 3c590 series the latency timer
1199 must be set to the maximum value to avoid data corruption that occurs
1200 when the timer expires during a transfer. This bug exists the Vortex
1202 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1203 if (pci_latency < new_latency) {
1204 printk(KERN_INFO "%s: Overriding PCI latency"
1205 " timer (CFLT) setting of %d, new value is %d.\n",
1206 print_name, pci_latency, new_latency);
1207 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1212 spin_lock_init(&vp->lock);
1213 spin_lock_init(&vp->mdio_lock);
1214 vp->gendev = gendev;
1216 /* Makes sure rings are at least 16 byte aligned. */
1217 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1218 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1221 if (vp->rx_ring == 0)
1224 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1225 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1227 /* if we are a PCI driver, we store info in pdev->driver_data
1228 * instead of a module list */
1230 pci_set_drvdata(pdev, dev);
1232 eisa_set_drvdata (edev, dev);
1234 vp->media_override = 7;
1236 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1237 if (vp->media_override != 7)
1239 vp->full_duplex = (option & 0x200) ? 1 : 0;
1240 vp->bus_master = (option & 16) ? 1 : 0;
1243 if (global_full_duplex > 0)
1244 vp->full_duplex = 1;
1245 if (global_enable_wol > 0)
1248 if (card_idx < MAX_UNITS) {
1249 if (full_duplex[card_idx] > 0)
1250 vp->full_duplex = 1;
1251 if (flow_ctrl[card_idx] > 0)
1253 if (enable_wol[card_idx] > 0)
1257 vp->force_fd = vp->full_duplex;
1258 vp->options = option;
1259 /* Read the station address from the EEPROM. */
1264 if (vci->drv_flags & EEPROM_8BIT)
1266 else if (vci->drv_flags & EEPROM_OFFSET)
1267 base = EEPROM_Read + 0x30;
1271 for (i = 0; i < 0x40; i++) {
1273 outw(base + i, ioaddr + Wn0EepromCmd);
1274 /* Pause for at least 162 us. for the read to take place. */
1275 for (timer = 10; timer >= 0; timer--) {
1277 if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1280 eeprom[i] = inw(ioaddr + Wn0EepromData);
1283 for (i = 0; i < 0x18; i++)
1284 checksum ^= eeprom[i];
1285 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1286 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1288 checksum ^= eeprom[i++];
1289 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1291 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1292 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1293 for (i = 0; i < 3; i++)
1294 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1296 for (i = 0; i < 6; i++)
1297 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1300 for (i = 0; i < 6; i++)
1301 outb(dev->dev_addr[i], ioaddr + i);
1305 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1308 printk(", IRQ %d\n", dev->irq);
1309 /* Tell them about an invalid IRQ. */
1310 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1311 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1316 step = (inb(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1318 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1319 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1325 unsigned long fn_st_addr; /* Cardbus function status space */
1328 fn_st_addr = pci_resource_start (pdev, 2);
1330 vp->cb_fn_base = ioremap(fn_st_addr, 128);
1332 if (!vp->cb_fn_base)
1336 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
1337 print_name, fn_st_addr, vp->cb_fn_base);
1341 n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1342 if (vp->drv_flags & INVERT_LED_PWR)
1344 if (vp->drv_flags & INVERT_MII_PWR)
1346 outw(n, ioaddr + Wn2_ResetOptions);
1347 if (vp->drv_flags & WNO_XCVR_PWR) {
1349 outw(0x0800, ioaddr);
1353 /* Extract our information from the EEPROM data. */
1354 vp->info1 = eeprom[13];
1355 vp->info2 = eeprom[15];
1356 vp->capabilities = eeprom[16];
1358 if (vp->info1 & 0x8000) {
1359 vp->full_duplex = 1;
1361 printk(KERN_INFO "Full duplex capable\n");
1365 static const char * ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1366 unsigned int config;
1368 vp->available_media = inw(ioaddr + Wn3_Options);
1369 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1370 vp->available_media = 0x40;
1371 config = inl(ioaddr + Wn3_Config);
1373 printk(KERN_DEBUG " Internal config register is %4.4x, "
1374 "transceivers %#x.\n", config, inw(ioaddr + Wn3_Options));
1375 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1376 8 << RAM_SIZE(config),
1377 RAM_WIDTH(config) ? "word" : "byte",
1378 ram_split[RAM_SPLIT(config)],
1379 AUTOSELECT(config) ? "autoselect/" : "",
1380 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1381 media_tbl[XCVR(config)].name);
1383 vp->default_media = XCVR(config);
1384 if (vp->default_media == XCVR_NWAY)
1386 vp->autoselect = AUTOSELECT(config);
1389 if (vp->media_override != 7) {
1390 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1391 print_name, vp->media_override,
1392 media_tbl[vp->media_override].name);
1393 dev->if_port = vp->media_override;
1395 dev->if_port = vp->default_media;
1397 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1398 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1399 int phy, phy_idx = 0;
1401 mii_preamble_required++;
1402 if (vp->drv_flags & EXTRA_PREAMBLE)
1403 mii_preamble_required++;
1404 mdio_sync(ioaddr, 32);
1405 mdio_read(dev, 24, 1);
1406 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1407 int mii_status, phyx;
1410 * For the 3c905CX we look at index 24 first, because it bogusly
1411 * reports an external PHY at all indices
1419 mii_status = mdio_read(dev, phyx, 1);
1420 if (mii_status && mii_status != 0xffff) {
1421 vp->phys[phy_idx++] = phyx;
1423 printk(KERN_INFO " MII transceiver found at address %d,"
1424 " status %4x.\n", phyx, mii_status);
1426 if ((mii_status & 0x0040) == 0)
1427 mii_preamble_required++;
1430 mii_preamble_required--;
1432 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1435 vp->advertising = mdio_read(dev, vp->phys[0], 4);
1436 if (vp->full_duplex) {
1437 /* Only advertise the FD media types. */
1438 vp->advertising &= ~0x02A0;
1439 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1444 if (vp->capabilities & CapBusMaster) {
1445 vp->full_bus_master_tx = 1;
1447 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1448 (vp->info2 & 1) ? "early" : "whole-frame" );
1450 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1451 vp->bus_master = 0; /* AKPM: vortex only */
1454 /* The 3c59x-specific entries in the device structure. */
1455 dev->open = vortex_open;
1456 if (vp->full_bus_master_tx) {
1457 dev->hard_start_xmit = boomerang_start_xmit;
1458 /* Actually, it still should work with iommu. */
1459 dev->features |= NETIF_F_SG;
1460 if (((hw_checksums[card_idx] == -1) && (vp->drv_flags & HAS_HWCKSM)) ||
1461 (hw_checksums[card_idx] == 1)) {
1462 dev->features |= NETIF_F_IP_CSUM;
1465 dev->hard_start_xmit = vortex_start_xmit;
1469 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1471 (dev->features & NETIF_F_SG) ? "en":"dis",
1472 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1475 dev->stop = vortex_close;
1476 dev->get_stats = vortex_get_stats;
1477 dev->do_ioctl = vortex_ioctl;
1478 dev->ethtool_ops = &vortex_ethtool_ops;
1479 dev->set_multicast_list = set_rx_mode;
1480 dev->tx_timeout = vortex_tx_timeout;
1481 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1482 #ifdef CONFIG_NET_POLL_CONTROLLER
1483 dev->poll_controller = poll_vortex;
1485 if (pdev && vp->enable_wol) {
1486 vp->pm_state_valid = 1;
1487 pci_save_state(VORTEX_PCI(vp), vp->power_state);
1490 retval = register_netdev(dev);
1495 pci_free_consistent(pdev,
1496 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1497 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1501 if (vp->must_free_region)
1502 release_region(ioaddr, vci->io_size);
1504 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1510 issue_and_wait(struct net_device *dev, int cmd)
1514 outw(cmd, dev->base_addr + EL3_CMD);
1515 for (i = 0; i < 2000; i++) {
1516 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress))
1520 /* OK, that didn't work. Do it the slow way. One second */
1521 for (i = 0; i < 100000; i++) {
1522 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress)) {
1523 if (vortex_debug > 1)
1524 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1525 dev->name, cmd, i * 10);
1530 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1531 dev->name, cmd, inw(dev->base_addr + EL3_STATUS));
1535 vortex_up(struct net_device *dev)
1537 long ioaddr = dev->base_addr;
1538 struct vortex_private *vp = netdev_priv(dev);
1539 unsigned int config;
1542 if (VORTEX_PCI(vp) && vp->enable_wol) {
1543 pci_set_power_state(VORTEX_PCI(vp), 0); /* Go active */
1544 pci_restore_state(VORTEX_PCI(vp), vp->power_state);
1547 /* Before initializing select the active media port. */
1549 config = inl(ioaddr + Wn3_Config);
1551 if (vp->media_override != 7) {
1552 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1553 dev->name, vp->media_override,
1554 media_tbl[vp->media_override].name);
1555 dev->if_port = vp->media_override;
1556 } else if (vp->autoselect) {
1558 if (vortex_debug > 1)
1559 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1560 dev->name, dev->if_port);
1561 dev->if_port = XCVR_NWAY;
1563 /* Find first available media type, starting with 100baseTx. */
1564 dev->if_port = XCVR_100baseTx;
1565 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1566 dev->if_port = media_tbl[dev->if_port].next;
1567 if (vortex_debug > 1)
1568 printk(KERN_INFO "%s: first available media type: %s\n",
1569 dev->name, media_tbl[dev->if_port].name);
1572 dev->if_port = vp->default_media;
1573 if (vortex_debug > 1)
1574 printk(KERN_INFO "%s: using default media %s\n",
1575 dev->name, media_tbl[dev->if_port].name);
1578 init_timer(&vp->timer);
1579 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1580 vp->timer.data = (unsigned long)dev;
1581 vp->timer.function = vortex_timer; /* timer handler */
1582 add_timer(&vp->timer);
1584 init_timer(&vp->rx_oom_timer);
1585 vp->rx_oom_timer.data = (unsigned long)dev;
1586 vp->rx_oom_timer.function = rx_oom_timer;
1588 if (vortex_debug > 1)
1589 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1590 dev->name, media_tbl[dev->if_port].name);
1592 vp->full_duplex = vp->force_fd;
1593 config = BFINS(config, dev->if_port, 20, 4);
1594 if (vortex_debug > 6)
1595 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1596 outl(config, ioaddr + Wn3_Config);
1598 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1599 int mii_reg1, mii_reg5;
1601 /* Read BMSR (reg1) only to clear old status. */
1602 mii_reg1 = mdio_read(dev, vp->phys[0], 1);
1603 mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1604 if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) {
1605 netif_carrier_off(dev); /* No MII device or no link partner report */
1607 mii_reg5 &= vp->advertising;
1608 if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1609 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1610 vp->full_duplex = 1;
1611 netif_carrier_on(dev);
1613 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1614 if (vortex_debug > 1)
1615 printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1616 " info1 %04x, setting %s-duplex.\n",
1617 dev->name, vp->phys[0],
1619 vp->info1, ((vp->info1 & 0x8000) || vp->full_duplex) ? "full" : "half");
1623 /* Set the full-duplex bit. */
1624 outw( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1625 (dev->mtu > 1500 ? 0x40 : 0) |
1626 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1627 ioaddr + Wn3_MAC_Ctrl);
1629 if (vortex_debug > 1) {
1630 printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",
1634 issue_and_wait(dev, TxReset);
1636 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1638 issue_and_wait(dev, RxReset|0x04);
1640 outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1642 if (vortex_debug > 1) {
1644 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1645 dev->name, dev->irq, inw(ioaddr + Wn4_Media));
1648 /* Set the station address and mask in window 2 each time opened. */
1650 for (i = 0; i < 6; i++)
1651 outb(dev->dev_addr[i], ioaddr + i);
1652 for (; i < 12; i+=2)
1653 outw(0, ioaddr + i);
1655 if (vp->cb_fn_base) {
1656 unsigned short n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1657 if (vp->drv_flags & INVERT_LED_PWR)
1659 if (vp->drv_flags & INVERT_MII_PWR)
1661 outw(n, ioaddr + Wn2_ResetOptions);
1664 if (dev->if_port == XCVR_10base2)
1665 /* Start the thinnet transceiver. We should really wait 50ms...*/
1666 outw(StartCoax, ioaddr + EL3_CMD);
1667 if (dev->if_port != XCVR_NWAY) {
1669 outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1670 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1673 /* Switch to the stats window, and clear all stats by reading. */
1674 outw(StatsDisable, ioaddr + EL3_CMD);
1676 for (i = 0; i < 10; i++)
1680 /* New: On the Vortex we must also clear the BadSSD counter. */
1683 /* ..and on the Boomerang we enable the extra statistics bits. */
1684 outw(0x0040, ioaddr + Wn4_NetDiag);
1686 /* Switch to register set 7 for normal use. */
1689 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1690 vp->cur_rx = vp->dirty_rx = 0;
1691 /* Initialize the RxEarly register as recommended. */
1692 outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1693 outl(0x0020, ioaddr + PktStatus);
1694 outl(vp->rx_ring_dma, ioaddr + UpListPtr);
1696 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1697 vp->cur_tx = vp->dirty_tx = 0;
1698 if (vp->drv_flags & IS_BOOMERANG)
1699 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1700 /* Clear the Rx, Tx rings. */
1701 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1702 vp->rx_ring[i].status = 0;
1703 for (i = 0; i < TX_RING_SIZE; i++)
1704 vp->tx_skbuff[i] = 0;
1705 outl(0, ioaddr + DownListPtr);
1707 /* Set receiver mode: presumably accept b-case and phys addr only. */
1709 outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1711 // issue_and_wait(dev, SetTxStart|0x07ff);
1712 outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1713 outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1714 /* Allow status bits to be seen. */
1715 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1716 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1717 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1718 (vp->bus_master ? DMADone : 0);
1719 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1720 (vp->full_bus_master_rx ? 0 : RxComplete) |
1721 StatsFull | HostError | TxComplete | IntReq
1722 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1723 outw(vp->status_enable, ioaddr + EL3_CMD);
1724 /* Ack all pending events, and set active indicator mask. */
1725 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1727 outw(vp->intr_enable, ioaddr + EL3_CMD);
1728 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1729 writel(0x8000, vp->cb_fn_base + 4);
1730 netif_start_queue (dev);
1734 vortex_open(struct net_device *dev)
1736 struct vortex_private *vp = netdev_priv(dev);
1740 /* Use the now-standard shared IRQ implementation. */
1741 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1742 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1743 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1747 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1748 if (vortex_debug > 2)
1749 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1750 for (i = 0; i < RX_RING_SIZE; i++) {
1751 struct sk_buff *skb;
1752 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1753 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1754 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1755 skb = dev_alloc_skb(PKT_BUF_SZ);
1756 vp->rx_skbuff[i] = skb;
1758 break; /* Bad news! */
1759 skb->dev = dev; /* Mark as being used by this device. */
1760 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1761 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->tail, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1763 if (i != RX_RING_SIZE) {
1765 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1766 for (j = 0; j < i; j++) {
1767 if (vp->rx_skbuff[j]) {
1768 dev_kfree_skb(vp->rx_skbuff[j]);
1769 vp->rx_skbuff[j] = 0;
1775 /* Wrap the ring. */
1776 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1783 free_irq(dev->irq, dev);
1785 if (vortex_debug > 1)
1786 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1791 vortex_timer(unsigned long data)
1793 struct net_device *dev = (struct net_device *)data;
1794 struct vortex_private *vp = netdev_priv(dev);
1795 long ioaddr = dev->base_addr;
1796 int next_tick = 10*HZ;
1798 int media_status, mii_status, old_window;
1800 if (vortex_debug > 2) {
1801 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1802 dev->name, media_tbl[dev->if_port].name);
1803 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1807 goto leave_media_alone;
1808 disable_irq(dev->irq);
1809 old_window = inw(ioaddr + EL3_CMD) >> 13;
1811 media_status = inw(ioaddr + Wn4_Media);
1812 switch (dev->if_port) {
1813 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1814 if (media_status & Media_LnkBeat) {
1815 netif_carrier_on(dev);
1817 if (vortex_debug > 1)
1818 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1819 dev->name, media_tbl[dev->if_port].name, media_status);
1821 netif_carrier_off(dev);
1822 if (vortex_debug > 1) {
1823 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1824 dev->name, media_tbl[dev->if_port].name, media_status);
1828 case XCVR_MII: case XCVR_NWAY:
1830 mii_status = mdio_read(dev, vp->phys[0], 1);
1832 if (vortex_debug > 2)
1833 printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1834 dev->name, mii_status);
1835 if (mii_status & BMSR_LSTATUS) {
1836 int mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1837 if (! vp->force_fd && mii_reg5 != 0xffff) {
1840 mii_reg5 &= vp->advertising;
1841 duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
1842 if (vp->full_duplex != duplex) {
1843 vp->full_duplex = duplex;
1844 printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1845 "#%d link partner capability of %4.4x.\n",
1846 dev->name, vp->full_duplex ? "full" : "half",
1847 vp->phys[0], mii_reg5);
1848 /* Set the full-duplex bit. */
1850 outw( (vp->full_duplex ? 0x20 : 0) |
1851 (dev->mtu > 1500 ? 0x40 : 0) |
1852 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1853 ioaddr + Wn3_MAC_Ctrl);
1854 if (vortex_debug > 1)
1855 printk(KERN_DEBUG "Setting duplex in Wn3_MAC_Ctrl\n");
1856 /* AKPM: bug: should reset Tx and Rx after setting Duplex. Page 180 */
1859 netif_carrier_on(dev);
1861 netif_carrier_off(dev);
1865 default: /* Other media types handled by Tx timeouts. */
1866 if (vortex_debug > 1)
1867 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1868 dev->name, media_tbl[dev->if_port].name, media_status);
1872 unsigned int config;
1875 dev->if_port = media_tbl[dev->if_port].next;
1876 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1877 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1878 dev->if_port = vp->default_media;
1879 if (vortex_debug > 1)
1880 printk(KERN_DEBUG "%s: Media selection failing, using default "
1882 dev->name, media_tbl[dev->if_port].name);
1884 if (vortex_debug > 1)
1885 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1887 dev->name, media_tbl[dev->if_port].name);
1888 next_tick = media_tbl[dev->if_port].wait;
1890 outw((media_status & ~(Media_10TP|Media_SQE)) |
1891 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1894 config = inl(ioaddr + Wn3_Config);
1895 config = BFINS(config, dev->if_port, 20, 4);
1896 outl(config, ioaddr + Wn3_Config);
1898 outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1900 if (vortex_debug > 1)
1901 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1902 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1904 EL3WINDOW(old_window);
1905 enable_irq(dev->irq);
1908 if (vortex_debug > 2)
1909 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1910 dev->name, media_tbl[dev->if_port].name);
1912 mod_timer(&vp->timer, RUN_AT(next_tick));
1914 outw(FakeIntr, ioaddr + EL3_CMD);
1918 static void vortex_tx_timeout(struct net_device *dev)
1920 struct vortex_private *vp = netdev_priv(dev);
1921 long ioaddr = dev->base_addr;
1923 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1924 dev->name, inb(ioaddr + TxStatus),
1925 inw(ioaddr + EL3_STATUS));
1927 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1928 inw(ioaddr + Wn4_NetDiag),
1929 inw(ioaddr + Wn4_Media),
1930 inl(ioaddr + PktStatus),
1931 inw(ioaddr + Wn4_FIFODiag));
1932 /* Slight code bloat to be user friendly. */
1933 if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
1934 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1935 " network cable problem?\n", dev->name);
1936 if (inw(ioaddr + EL3_STATUS) & IntLatch) {
1937 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1938 " IRQ blocked by another device?\n", dev->name);
1939 /* Bad idea here.. but we might as well handle a few events. */
1942 * Block interrupts because vortex_interrupt does a bare spin_lock()
1944 unsigned long flags;
1945 local_irq_save(flags);
1946 if (vp->full_bus_master_tx)
1947 boomerang_interrupt(dev->irq, dev, 0);
1949 vortex_interrupt(dev->irq, dev, 0);
1950 local_irq_restore(flags);
1954 if (vortex_debug > 0)
1957 issue_and_wait(dev, TxReset);
1959 vp->stats.tx_errors++;
1960 if (vp->full_bus_master_tx) {
1961 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
1962 if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0)
1963 outl(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1964 ioaddr + DownListPtr);
1965 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1966 netif_wake_queue (dev);
1967 if (vp->drv_flags & IS_BOOMERANG)
1968 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1969 outw(DownUnstall, ioaddr + EL3_CMD);
1971 vp->stats.tx_dropped++;
1972 netif_wake_queue(dev);
1975 /* Issue Tx Enable */
1976 outw(TxEnable, ioaddr + EL3_CMD);
1977 dev->trans_start = jiffies;
1979 /* Switch to register set 7 for normal use. */
1984 * Handle uncommon interrupt sources. This is a separate routine to minimize
1988 vortex_error(struct net_device *dev, int status)
1990 struct vortex_private *vp = netdev_priv(dev);
1991 long ioaddr = dev->base_addr;
1992 int do_tx_reset = 0, reset_mask = 0;
1993 unsigned char tx_status = 0;
1995 if (vortex_debug > 2) {
1996 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1999 if (status & TxComplete) { /* Really "TxError" for us. */
2000 tx_status = inb(ioaddr + TxStatus);
2001 /* Presumably a tx-timeout. We must merely re-enable. */
2002 if (vortex_debug > 2
2003 || (tx_status != 0x88 && vortex_debug > 0)) {
2004 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2005 dev->name, tx_status);
2006 if (tx_status == 0x82) {
2007 printk(KERN_ERR "Probably a duplex mismatch. See "
2008 "Documentation/networking/vortex.txt\n");
2012 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2013 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2014 outb(0, ioaddr + TxStatus);
2015 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2017 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
2019 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2020 } else { /* Merely re-enable the transmitter. */
2021 outw(TxEnable, ioaddr + EL3_CMD);
2025 if (status & RxEarly) { /* Rx early is unused. */
2027 outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
2029 if (status & StatsFull) { /* Empty statistics. */
2030 static int DoneDidThat;
2031 if (vortex_debug > 4)
2032 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2033 update_stats(ioaddr, dev);
2034 /* HACK: Disable statistics as an interrupt source. */
2035 /* This occurs when we have the wrong media type! */
2036 if (DoneDidThat == 0 &&
2037 inw(ioaddr + EL3_STATUS) & StatsFull) {
2038 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2039 "stats as an interrupt source.\n", dev->name);
2041 outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
2042 vp->intr_enable &= ~StatsFull;
2047 if (status & IntReq) { /* Restore all interrupt sources. */
2048 outw(vp->status_enable, ioaddr + EL3_CMD);
2049 outw(vp->intr_enable, ioaddr + EL3_CMD);
2051 if (status & HostError) {
2054 fifo_diag = inw(ioaddr + Wn4_FIFODiag);
2055 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2056 dev->name, fifo_diag);
2057 /* Adapter failure requires Tx/Rx reset and reinit. */
2058 if (vp->full_bus_master_tx) {
2059 int bus_status = inl(ioaddr + PktStatus);
2060 /* 0x80000000 PCI master abort. */
2061 /* 0x40000000 PCI target abort. */
2063 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2065 /* In this case, blow the card away */
2066 /* Must not enter D3 or we can't legally issue the reset! */
2067 vortex_down(dev, 0);
2068 issue_and_wait(dev, TotalReset | 0xff);
2069 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2070 } else if (fifo_diag & 0x0400)
2072 if (fifo_diag & 0x3000) {
2073 /* Reset Rx fifo and upload logic */
2074 issue_and_wait(dev, RxReset|0x07);
2075 /* Set the Rx filter to the current state. */
2077 outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2078 outw(AckIntr | HostError, ioaddr + EL3_CMD);
2083 issue_and_wait(dev, TxReset|reset_mask);
2084 outw(TxEnable, ioaddr + EL3_CMD);
2085 if (!vp->full_bus_master_tx)
2086 netif_wake_queue(dev);
2091 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2093 struct vortex_private *vp = netdev_priv(dev);
2094 long ioaddr = dev->base_addr;
2096 /* Put out the doubleword header... */
2097 outl(skb->len, ioaddr + TX_FIFO);
2098 if (vp->bus_master) {
2099 /* Set the bus-master controller to transfer the packet. */
2100 int len = (skb->len + 3) & ~3;
2101 outl( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2102 ioaddr + Wn7_MasterAddr);
2103 outw(len, ioaddr + Wn7_MasterLen);
2105 outw(StartDMADown, ioaddr + EL3_CMD);
2106 /* netif_wake_queue() will be called at the DMADone interrupt. */
2108 /* ... and the packet rounded to a doubleword. */
2109 outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2110 dev_kfree_skb (skb);
2111 if (inw(ioaddr + TxFree) > 1536) {
2112 netif_start_queue (dev); /* AKPM: redundant? */
2114 /* Interrupt us when the FIFO has room for max-sized packet. */
2115 netif_stop_queue(dev);
2116 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2120 dev->trans_start = jiffies;
2122 /* Clear the Tx status stack. */
2127 while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
2128 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2129 if (vortex_debug > 2)
2130 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2131 dev->name, tx_status);
2132 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2133 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2134 if (tx_status & 0x30) {
2135 issue_and_wait(dev, TxReset);
2137 outw(TxEnable, ioaddr + EL3_CMD);
2139 outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2146 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2148 struct vortex_private *vp = netdev_priv(dev);
2149 long ioaddr = dev->base_addr;
2150 /* Calculate the next Tx descriptor entry. */
2151 int entry = vp->cur_tx % TX_RING_SIZE;
2152 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2153 unsigned long flags;
2155 if (vortex_debug > 6) {
2156 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2157 if (vortex_debug > 3)
2158 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2159 dev->name, vp->cur_tx);
2162 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2163 if (vortex_debug > 0)
2164 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2166 netif_stop_queue(dev);
2170 vp->tx_skbuff[entry] = skb;
2172 vp->tx_ring[entry].next = 0;
2174 if (skb->ip_summed != CHECKSUM_HW)
2175 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2177 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2179 if (!skb_shinfo(skb)->nr_frags) {
2180 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2181 skb->len, PCI_DMA_TODEVICE));
2182 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2186 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2187 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2188 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2190 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2191 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2193 vp->tx_ring[entry].frag[i+1].addr =
2194 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2195 (void*)page_address(frag->page) + frag->page_offset,
2196 frag->size, PCI_DMA_TODEVICE));
2198 if (i == skb_shinfo(skb)->nr_frags-1)
2199 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2201 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2205 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2206 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2207 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2210 spin_lock_irqsave(&vp->lock, flags);
2211 /* Wait for the stall to complete. */
2212 issue_and_wait(dev, DownStall);
2213 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2214 if (inl(ioaddr + DownListPtr) == 0) {
2215 outl(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2216 vp->queued_packet++;
2220 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2221 netif_stop_queue (dev);
2222 } else { /* Clear previous interrupt enable. */
2223 #if defined(tx_interrupt_mitigation)
2224 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2225 * were selected, this would corrupt DN_COMPLETE. No?
2227 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2230 outw(DownUnstall, ioaddr + EL3_CMD);
2231 spin_unlock_irqrestore(&vp->lock, flags);
2232 dev->trans_start = jiffies;
2236 /* The interrupt handler does all of the Rx thread work and cleans up
2237 after the Tx thread. */
2240 * This is the ISR for the vortex series chips.
2241 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2245 vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2247 struct net_device *dev = dev_id;
2248 struct vortex_private *vp = netdev_priv(dev);
2251 int work_done = max_interrupt_work;
2254 ioaddr = dev->base_addr;
2255 spin_lock(&vp->lock);
2257 status = inw(ioaddr + EL3_STATUS);
2259 if (vortex_debug > 6)
2260 printk("vortex_interrupt(). status=0x%4x\n", status);
2262 if ((status & IntLatch) == 0)
2263 goto handler_exit; /* No interrupt: shared IRQs cause this */
2266 if (status & IntReq) {
2267 status |= vp->deferred;
2271 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2274 if (vortex_debug > 4)
2275 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2276 dev->name, status, inb(ioaddr + Timer));
2279 if (vortex_debug > 5)
2280 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2282 if (status & RxComplete)
2285 if (status & TxAvailable) {
2286 if (vortex_debug > 5)
2287 printk(KERN_DEBUG " TX room bit was handled.\n");
2288 /* There's room in the FIFO for a full-sized packet. */
2289 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2290 netif_wake_queue (dev);
2293 if (status & DMADone) {
2294 if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) {
2295 outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2296 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2297 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2298 if (inw(ioaddr + TxFree) > 1536) {
2300 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2301 * insufficient FIFO room, the TxAvailable test will succeed and call
2302 * netif_wake_queue()
2304 netif_wake_queue(dev);
2305 } else { /* Interrupt when FIFO has room for max-sized packet. */
2306 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2307 netif_stop_queue(dev);
2311 /* Check for all uncommon interrupts at once. */
2312 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2313 if (status == 0xffff)
2315 vortex_error(dev, status);
2318 if (--work_done < 0) {
2319 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2320 "%4.4x.\n", dev->name, status);
2321 /* Disable all pending interrupts. */
2323 vp->deferred |= status;
2324 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2326 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2327 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2328 /* The timer will reenable interrupts. */
2329 mod_timer(&vp->timer, jiffies + 1*HZ);
2332 /* Acknowledge the IRQ. */
2333 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2334 } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2336 if (vortex_debug > 4)
2337 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2340 spin_unlock(&vp->lock);
2341 return IRQ_RETVAL(handled);
2345 * This is the ISR for the boomerang series chips.
2346 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2350 boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2352 struct net_device *dev = dev_id;
2353 struct vortex_private *vp = netdev_priv(dev);
2356 int work_done = max_interrupt_work;
2358 ioaddr = dev->base_addr;
2361 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2362 * and boomerang_start_xmit
2364 spin_lock(&vp->lock);
2366 status = inw(ioaddr + EL3_STATUS);
2368 if (vortex_debug > 6)
2369 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2371 if ((status & IntLatch) == 0)
2372 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2374 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2375 if (vortex_debug > 1)
2376 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2380 if (status & IntReq) {
2381 status |= vp->deferred;
2385 if (vortex_debug > 4)
2386 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2387 dev->name, status, inb(ioaddr + Timer));
2389 if (vortex_debug > 5)
2390 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2392 if (status & UpComplete) {
2393 outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
2394 if (vortex_debug > 5)
2395 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2399 if (status & DownComplete) {
2400 unsigned int dirty_tx = vp->dirty_tx;
2402 outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
2403 while (vp->cur_tx - dirty_tx > 0) {
2404 int entry = dirty_tx % TX_RING_SIZE;
2405 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2406 if (inl(ioaddr + DownListPtr) ==
2407 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2408 break; /* It still hasn't been processed. */
2410 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2411 break; /* It still hasn't been processed. */
2414 if (vp->tx_skbuff[entry]) {
2415 struct sk_buff *skb = vp->tx_skbuff[entry];
2418 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2419 pci_unmap_single(VORTEX_PCI(vp),
2420 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2421 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2424 pci_unmap_single(VORTEX_PCI(vp),
2425 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2427 dev_kfree_skb_irq(skb);
2428 vp->tx_skbuff[entry] = 0;
2430 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2432 /* vp->stats.tx_packets++; Counted below. */
2435 vp->dirty_tx = dirty_tx;
2436 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2437 if (vortex_debug > 6)
2438 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2439 netif_wake_queue (dev);
2443 /* Check for all uncommon interrupts at once. */
2444 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2445 vortex_error(dev, status);
2447 if (--work_done < 0) {
2448 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2449 "%4.4x.\n", dev->name, status);
2450 /* Disable all pending interrupts. */
2452 vp->deferred |= status;
2453 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2455 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2456 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2457 /* The timer will reenable interrupts. */
2458 mod_timer(&vp->timer, jiffies + 1*HZ);
2461 /* Acknowledge the IRQ. */
2462 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2463 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2464 writel(0x8000, vp->cb_fn_base + 4);
2466 } while ((status = inw(ioaddr + EL3_STATUS)) & IntLatch);
2468 if (vortex_debug > 4)
2469 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2472 spin_unlock(&vp->lock);
2476 static int vortex_rx(struct net_device *dev)
2478 struct vortex_private *vp = netdev_priv(dev);
2479 long ioaddr = dev->base_addr;
2483 if (vortex_debug > 5)
2484 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2485 inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
2486 while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
2487 if (rx_status & 0x4000) { /* Error, update stats. */
2488 unsigned char rx_error = inb(ioaddr + RxErrors);
2489 if (vortex_debug > 2)
2490 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2491 vp->stats.rx_errors++;
2492 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2493 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2494 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2495 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2496 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2498 /* The packet length: up to 4.5K!. */
2499 int pkt_len = rx_status & 0x1fff;
2500 struct sk_buff *skb;
2502 skb = dev_alloc_skb(pkt_len + 5);
2503 if (vortex_debug > 4)
2504 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2505 pkt_len, rx_status);
2508 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2509 /* 'skb_put()' points to the start of sk_buff data area. */
2510 if (vp->bus_master &&
2511 ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2512 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2513 pkt_len, PCI_DMA_FROMDEVICE);
2514 outl(dma, ioaddr + Wn7_MasterAddr);
2515 outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2516 outw(StartDMAUp, ioaddr + EL3_CMD);
2517 while (inw(ioaddr + Wn7_MasterStatus) & 0x8000)
2519 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2521 insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
2522 (pkt_len + 3) >> 2);
2524 outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2525 skb->protocol = eth_type_trans(skb, dev);
2527 dev->last_rx = jiffies;
2528 vp->stats.rx_packets++;
2529 /* Wait a limited time to go to next packet. */
2530 for (i = 200; i >= 0; i--)
2531 if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
2534 } else if (vortex_debug > 0)
2535 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2536 "size %d.\n", dev->name, pkt_len);
2538 vp->stats.rx_dropped++;
2539 issue_and_wait(dev, RxDiscard);
2546 boomerang_rx(struct net_device *dev)
2548 struct vortex_private *vp = netdev_priv(dev);
2549 int entry = vp->cur_rx % RX_RING_SIZE;
2550 long ioaddr = dev->base_addr;
2552 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2554 if (vortex_debug > 5)
2555 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", inw(ioaddr+EL3_STATUS));
2557 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2558 if (--rx_work_limit < 0)
2560 if (rx_status & RxDError) { /* Error, update stats. */
2561 unsigned char rx_error = rx_status >> 16;
2562 if (vortex_debug > 2)
2563 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2564 vp->stats.rx_errors++;
2565 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2566 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2567 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2568 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2569 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2571 /* The packet length: up to 4.5K!. */
2572 int pkt_len = rx_status & 0x1fff;
2573 struct sk_buff *skb;
2574 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2576 if (vortex_debug > 4)
2577 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2578 pkt_len, rx_status);
2580 /* Check if the packet is long enough to just accept without
2581 copying to a properly sized skbuff. */
2582 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2584 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2585 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2586 /* 'skb_put()' points to the start of sk_buff data area. */
2587 memcpy(skb_put(skb, pkt_len),
2588 vp->rx_skbuff[entry]->tail,
2590 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2593 /* Pass up the skbuff already on the Rx ring. */
2594 skb = vp->rx_skbuff[entry];
2595 vp->rx_skbuff[entry] = NULL;
2596 skb_put(skb, pkt_len);
2597 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2600 skb->protocol = eth_type_trans(skb, dev);
2601 { /* Use hardware checksum info. */
2602 int csum_bits = rx_status & 0xee000000;
2604 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2605 csum_bits == (IPChksumValid | UDPChksumValid))) {
2606 skb->ip_summed = CHECKSUM_UNNECESSARY;
2611 dev->last_rx = jiffies;
2612 vp->stats.rx_packets++;
2614 entry = (++vp->cur_rx) % RX_RING_SIZE;
2616 /* Refill the Rx ring buffers. */
2617 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2618 struct sk_buff *skb;
2619 entry = vp->dirty_rx % RX_RING_SIZE;
2620 if (vp->rx_skbuff[entry] == NULL) {
2621 skb = dev_alloc_skb(PKT_BUF_SZ);
2623 static unsigned long last_jif;
2624 if ((jiffies - last_jif) > 10 * HZ) {
2625 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2628 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2629 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2630 break; /* Bad news! */
2632 skb->dev = dev; /* Mark as being used by this device. */
2633 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2634 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->tail, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2635 vp->rx_skbuff[entry] = skb;
2637 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2638 outw(UpUnstall, ioaddr + EL3_CMD);
2644 * If we've hit a total OOM refilling the Rx ring we poll once a second
2645 * for some memory. Otherwise there is no way to restart the rx process.
2648 rx_oom_timer(unsigned long arg)
2650 struct net_device *dev = (struct net_device *)arg;
2651 struct vortex_private *vp = netdev_priv(dev);
2653 spin_lock_irq(&vp->lock);
2654 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2656 if (vortex_debug > 1) {
2657 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2658 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2660 spin_unlock_irq(&vp->lock);
2664 vortex_down(struct net_device *dev, int final_down)
2666 struct vortex_private *vp = netdev_priv(dev);
2667 long ioaddr = dev->base_addr;
2669 netif_stop_queue (dev);
2671 del_timer_sync(&vp->rx_oom_timer);
2672 del_timer_sync(&vp->timer);
2674 /* Turn off statistics ASAP. We update vp->stats below. */
2675 outw(StatsDisable, ioaddr + EL3_CMD);
2677 /* Disable the receiver and transmitter. */
2678 outw(RxDisable, ioaddr + EL3_CMD);
2679 outw(TxDisable, ioaddr + EL3_CMD);
2681 if (dev->if_port == XCVR_10base2)
2682 /* Turn off thinnet power. Green! */
2683 outw(StopCoax, ioaddr + EL3_CMD);
2685 outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2687 update_stats(ioaddr, dev);
2688 if (vp->full_bus_master_rx)
2689 outl(0, ioaddr + UpListPtr);
2690 if (vp->full_bus_master_tx)
2691 outl(0, ioaddr + DownListPtr);
2693 if (final_down && VORTEX_PCI(vp) && vp->enable_wol) {
2694 pci_save_state(VORTEX_PCI(vp), vp->power_state);
2700 vortex_close(struct net_device *dev)
2702 struct vortex_private *vp = netdev_priv(dev);
2703 long ioaddr = dev->base_addr;
2706 if (netif_device_present(dev))
2707 vortex_down(dev, 1);
2709 if (vortex_debug > 1) {
2710 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2711 dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus));
2712 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2713 " tx_queued %d Rx pre-checksummed %d.\n",
2714 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2718 if ( vp->rx_csumhits &&
2719 ((vp->drv_flags & HAS_HWCKSM) == 0) &&
2720 (hw_checksums[vp->card_idx] == -1)) {
2721 printk(KERN_WARNING "%s supports hardware checksums, and we're not using them!\n", dev->name);
2725 free_irq(dev->irq, dev);
2727 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2728 for (i = 0; i < RX_RING_SIZE; i++)
2729 if (vp->rx_skbuff[i]) {
2730 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2731 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2732 dev_kfree_skb(vp->rx_skbuff[i]);
2733 vp->rx_skbuff[i] = 0;
2736 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2737 for (i = 0; i < TX_RING_SIZE; i++) {
2738 if (vp->tx_skbuff[i]) {
2739 struct sk_buff *skb = vp->tx_skbuff[i];
2743 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2744 pci_unmap_single(VORTEX_PCI(vp),
2745 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2746 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2749 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2752 vp->tx_skbuff[i] = 0;
2761 dump_tx_ring(struct net_device *dev)
2763 if (vortex_debug > 0) {
2764 struct vortex_private *vp = netdev_priv(dev);
2765 long ioaddr = dev->base_addr;
2767 if (vp->full_bus_master_tx) {
2769 int stalled = inl(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2771 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2772 vp->full_bus_master_tx,
2773 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2774 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2775 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2776 inl(ioaddr + DownListPtr),
2777 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2778 issue_and_wait(dev, DownStall);
2779 for (i = 0; i < TX_RING_SIZE; i++) {
2780 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2783 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2785 le32_to_cpu(vp->tx_ring[i].length),
2787 le32_to_cpu(vp->tx_ring[i].status));
2790 outw(DownUnstall, ioaddr + EL3_CMD);
2795 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2797 struct vortex_private *vp = netdev_priv(dev);
2798 unsigned long flags;
2800 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2801 spin_lock_irqsave (&vp->lock, flags);
2802 update_stats(dev->base_addr, dev);
2803 spin_unlock_irqrestore (&vp->lock, flags);
2808 /* Update statistics.
2809 Unlike with the EL3 we need not worry about interrupts changing
2810 the window setting from underneath us, but we must still guard
2811 against a race condition with a StatsUpdate interrupt updating the
2812 table. This is done by checking that the ASM (!) code generated uses
2813 atomic updates with '+='.
2815 static void update_stats(long ioaddr, struct net_device *dev)
2817 struct vortex_private *vp = netdev_priv(dev);
2818 int old_window = inw(ioaddr + EL3_CMD);
2820 if (old_window == 0xffff) /* Chip suspended or ejected. */
2822 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2823 /* Switch to the stats window, and read everything. */
2825 vp->stats.tx_carrier_errors += inb(ioaddr + 0);
2826 vp->stats.tx_heartbeat_errors += inb(ioaddr + 1);
2827 /* Multiple collisions. */ inb(ioaddr + 2);
2828 vp->stats.collisions += inb(ioaddr + 3);
2829 vp->stats.tx_window_errors += inb(ioaddr + 4);
2830 vp->stats.rx_fifo_errors += inb(ioaddr + 5);
2831 vp->stats.tx_packets += inb(ioaddr + 6);
2832 vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4;
2833 /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */
2834 /* Tx deferrals */ inb(ioaddr + 8);
2835 /* Don't bother with register 9, an extension of registers 6&7.
2836 If we do use the 6&7 values the atomic update assumption above
2838 vp->stats.rx_bytes += inw(ioaddr + 10);
2839 vp->stats.tx_bytes += inw(ioaddr + 12);
2840 /* New: On the Vortex we must also clear the BadSSD counter. */
2845 u8 up = inb(ioaddr + 13);
2846 vp->stats.rx_bytes += (up & 0x0f) << 16;
2847 vp->stats.tx_bytes += (up & 0xf0) << 12;
2850 EL3WINDOW(old_window >> 13);
2855 static void vortex_get_drvinfo(struct net_device *dev,
2856 struct ethtool_drvinfo *info)
2858 struct vortex_private *vp = netdev_priv(dev);
2860 strcpy(info->driver, DRV_NAME);
2861 strcpy(info->version, DRV_VERSION);
2862 if (VORTEX_PCI(vp)) {
2863 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2865 if (VORTEX_EISA(vp))
2866 sprintf(info->bus_info, vp->gendev->bus_id);
2868 sprintf(info->bus_info, "EISA 0x%lx %d",
2869 dev->base_addr, dev->irq);
2873 static struct ethtool_ops vortex_ethtool_ops = {
2874 .get_drvinfo = vortex_get_drvinfo,
2877 static int vortex_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2879 struct vortex_private *vp = netdev_priv(dev);
2880 long ioaddr = dev->base_addr;
2881 struct mii_ioctl_data *data = if_mii(rq);
2882 int phy = vp->phys[0] & 0x1f;
2886 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2889 case SIOCGMIIREG: /* Read MII PHY register. */
2891 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2895 case SIOCSMIIREG: /* Write MII PHY register. */
2896 if (!capable(CAP_NET_ADMIN)) {
2900 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2905 retval = -EOPNOTSUPP;
2913 * Must power the device up to do MDIO operations
2915 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2918 struct vortex_private *vp = netdev_priv(dev);
2922 state = VORTEX_PCI(vp)->current_state;
2924 /* The kernel core really should have pci_get_power_state() */
2927 pci_set_power_state(VORTEX_PCI(vp), 0);
2928 err = vortex_do_ioctl(dev, rq, cmd);
2930 pci_set_power_state(VORTEX_PCI(vp), state);
2936 /* Pre-Cyclone chips have no documented multicast filter, so the only
2937 multicast setting is to receive all multicast frames. At least
2938 the chip has a very clean way to set the mode, unlike many others. */
2939 static void set_rx_mode(struct net_device *dev)
2941 long ioaddr = dev->base_addr;
2944 if (dev->flags & IFF_PROMISC) {
2945 if (vortex_debug > 0)
2946 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2947 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2948 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2949 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2951 new_mode = SetRxFilter | RxStation | RxBroadcast;
2953 outw(new_mode, ioaddr + EL3_CMD);
2956 /* MII transceiver control section.
2957 Read and write the MII registers using software-generated serial
2958 MDIO protocol. See the MII specifications or DP83840A data sheet
2961 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
2962 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
2963 "overclocking" issues. */
2964 #define mdio_delay() inl(mdio_addr)
2966 #define MDIO_SHIFT_CLK 0x01
2967 #define MDIO_DIR_WRITE 0x04
2968 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
2969 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
2970 #define MDIO_DATA_READ 0x02
2971 #define MDIO_ENB_IN 0x00
2973 /* Generate the preamble required for initial synchronization and
2974 a few older transceivers. */
2975 static void mdio_sync(long ioaddr, int bits)
2977 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2979 /* Establish sync by sending at least 32 logic ones. */
2980 while (-- bits >= 0) {
2981 outw(MDIO_DATA_WRITE1, mdio_addr);
2983 outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
2988 static int mdio_read(struct net_device *dev, int phy_id, int location)
2990 struct vortex_private *vp = netdev_priv(dev);
2992 long ioaddr = dev->base_addr;
2993 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
2994 unsigned int retval = 0;
2995 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2997 spin_lock_bh(&vp->mdio_lock);
2999 if (mii_preamble_required)
3000 mdio_sync(ioaddr, 32);
3002 /* Shift the read command bits out. */
3003 for (i = 14; i >= 0; i--) {
3004 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3005 outw(dataval, mdio_addr);
3007 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
3010 /* Read the two transition, 16 data, and wire-idle bits. */
3011 for (i = 19; i > 0; i--) {
3012 outw(MDIO_ENB_IN, mdio_addr);
3014 retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3015 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3018 spin_unlock_bh(&vp->mdio_lock);
3019 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3022 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3024 struct vortex_private *vp = netdev_priv(dev);
3025 long ioaddr = dev->base_addr;
3026 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3027 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3030 spin_lock_bh(&vp->mdio_lock);
3032 if (mii_preamble_required)
3033 mdio_sync(ioaddr, 32);
3035 /* Shift the command bits out. */
3036 for (i = 31; i >= 0; i--) {
3037 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3038 outw(dataval, mdio_addr);
3040 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
3043 /* Leave the interface idle. */
3044 for (i = 1; i >= 0; i--) {
3045 outw(MDIO_ENB_IN, mdio_addr);
3047 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3050 spin_unlock_bh(&vp->mdio_lock);
3054 /* ACPI: Advanced Configuration and Power Interface. */
3055 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3056 static void acpi_set_WOL(struct net_device *dev)
3058 struct vortex_private *vp = netdev_priv(dev);
3059 long ioaddr = dev->base_addr;
3061 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3063 outw(2, ioaddr + 0x0c);
3064 /* The RxFilter must accept the WOL frames. */
3065 outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3066 outw(RxEnable, ioaddr + EL3_CMD);
3068 /* Change the power state to D3; RxEnable doesn't take effect. */
3069 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3070 pci_set_power_state(VORTEX_PCI(vp), 3);
3074 static void __devexit vortex_remove_one (struct pci_dev *pdev)
3076 struct net_device *dev = pci_get_drvdata(pdev);
3077 struct vortex_private *vp;
3080 printk("vortex_remove_one called for Compaq device!\n");
3084 vp = netdev_priv(dev);
3086 /* AKPM: FIXME: we should have
3087 * if (vp->cb_fn_base) iounmap(vp->cb_fn_base);
3090 unregister_netdev(dev);
3092 if (VORTEX_PCI(vp) && vp->enable_wol) {
3093 pci_set_power_state(VORTEX_PCI(vp), 0); /* Go active */
3094 if (vp->pm_state_valid)
3095 pci_restore_state(VORTEX_PCI(vp), vp->power_state);
3097 /* Should really use issue_and_wait() here */
3098 outw(TotalReset|0x14, dev->base_addr + EL3_CMD);
3100 pci_free_consistent(pdev,
3101 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3102 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3105 if (vp->must_free_region)
3106 release_region(dev->base_addr, vp->io_size);
3111 static struct pci_driver vortex_driver = {
3113 .probe = vortex_init_one,
3114 .remove = __devexit_p(vortex_remove_one),
3115 .id_table = vortex_pci_tbl,
3117 .suspend = vortex_suspend,
3118 .resume = vortex_resume,
3123 static int vortex_have_pci;
3124 static int vortex_have_eisa;
3127 static int __init vortex_init (void)
3129 int pci_rc, eisa_rc;
3131 pci_rc = pci_module_init(&vortex_driver);
3132 eisa_rc = vortex_eisa_init();
3135 vortex_have_pci = 1;
3137 vortex_have_eisa = 1;
3139 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3143 static void __exit vortex_eisa_cleanup (void)
3145 struct vortex_private *vp;
3149 /* Take care of the EISA devices */
3150 eisa_driver_unregister (&vortex_eisa_driver);
3153 if (compaq_net_device) {
3154 vp = compaq_net_device->priv;
3155 ioaddr = compaq_net_device->base_addr;
3157 unregister_netdev (compaq_net_device);
3158 outw (TotalReset, ioaddr + EL3_CMD);
3159 release_region (ioaddr, VORTEX_TOTAL_SIZE);
3161 free_netdev (compaq_net_device);
3166 static void __exit vortex_cleanup (void)
3168 if (vortex_have_pci)
3169 pci_unregister_driver (&vortex_driver);
3170 if (vortex_have_eisa)
3171 vortex_eisa_cleanup ();
3175 module_init(vortex_init);
3176 module_exit(vortex_cleanup);