1 /*******************************************************************************
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * e100.c: Intel(R) PRO/100 ethernet driver
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
55 * II. Driver Operation
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt, or
91 * in dev->poll in the case where NAPI is enabled. cbs_avail keeps
92 * track of number of free CB resources available.
94 * Hardware padding of short packets to minimum packet size is
95 * enabled. 82557 pads with 7Eh, while the later controllers pad
100 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
101 * Descriptors (RFD) + data buffer, thus forming the simplified mode
102 * memory structure. Rx skbs are allocated to contain both the RFD
103 * and the data buffer, but the RFD is pulled off before the skb is
104 * indicated. The data buffer is aligned such that encapsulated
105 * protocol headers are u32-aligned. Since the RFD is part of the
106 * mapped shared memory, and completion status is contained within
107 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
108 * view from software and hardware.
110 * Under typical operation, the receive unit (RU) is start once,
111 * and the controller happily fills RFDs as frames arrive. If
112 * replacement RFDs cannot be allocated, or the RU goes non-active,
113 * the RU must be restarted. Frame arrival generates an interrupt,
114 * and Rx indication and re-allocation happen in the same context,
115 * therefore no locking is required. If NAPI is enabled, this work
116 * happens in dev->poll. A software-generated interrupt is gen-
117 * erated from the watchdog to recover from a failed allocation
118 * senario where all Rx resources have been indicated and none re-
123 * VLAN offloading of tagging, stripping and filtering is not
124 * supported, but driver will accommodate the extra 4-byte VLAN tag
125 * for processing by upper layers. Tx/Rx Checksum offloading is not
126 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
127 * not supported (hardware limitation).
129 * NAPI support is enabled with CONFIG_E100_NAPI.
131 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
133 * Thanks to JC (jchapman@katalix.com) for helping with
134 * testing/troubleshooting the development driver.
137 * o several entry points race with dev->close
138 * o check for tx-no-resources/stop Q races with tx clean/wake Q
141 #include <linux/config.h>
142 #include <linux/module.h>
143 #include <linux/moduleparam.h>
144 #include <linux/kernel.h>
145 #include <linux/types.h>
146 #include <linux/slab.h>
147 #include <linux/delay.h>
148 #include <linux/init.h>
149 #include <linux/pci.h>
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/mii.h>
153 #include <linux/if_vlan.h>
154 #include <linux/skbuff.h>
155 #include <linux/ethtool.h>
156 #include <linux/string.h>
157 #include <asm/unaligned.h>
160 #define DRV_NAME "e100"
161 #define DRV_VERSION "3.0.17"
162 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
163 #define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation"
164 #define PFX DRV_NAME ": "
166 #define E100_WATCHDOG_PERIOD (2 * HZ)
167 #define E100_NAPI_WEIGHT 16
169 MODULE_DESCRIPTION(DRV_DESCRIPTION);
170 MODULE_AUTHOR(DRV_COPYRIGHT);
171 MODULE_LICENSE("GPL");
173 static int debug = 3;
174 module_param(debug, int, 0);
175 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
176 #define DPRINTK(nlevel, klevel, fmt, args...) \
177 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
178 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
179 __FUNCTION__ , ## args))
181 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
182 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
183 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
184 static struct pci_device_id e100_id_table[] = {
185 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
187 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
192 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
198 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
205 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
206 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
215 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
216 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
217 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
220 MODULE_DEVICE_TABLE(pci, e100_id_table);
223 mac_82557_D100_A = 0,
224 mac_82557_D100_B = 1,
225 mac_82557_D100_C = 2,
226 mac_82558_D101_A4 = 4,
227 mac_82558_D101_B0 = 5,
231 mac_82550_D102_C = 13,
239 phy_100a = 0x000003E0,
240 phy_100c = 0x035002A8,
241 phy_82555_tx = 0x015002A8,
242 phy_nsc_tx = 0x5C002000,
243 phy_82562_et = 0x033002A8,
244 phy_82562_em = 0x032002A8,
245 phy_82562_eh = 0x017002A8,
246 phy_unknown = 0xFFFFFFFF,
249 /* CSR (Control/Status Registers) */
272 stat_ack_not_ours = 0x00,
273 stat_ack_sw_gen = 0x04,
275 stat_ack_cu_idle = 0x20,
276 stat_ack_frame_rx = 0x40,
277 stat_ack_cu_cmd_done = 0x80,
278 stat_ack_not_present = 0xFF,
279 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
280 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
284 irq_mask_none = 0x00,
292 ruc_load_base = 0x06,
295 cuc_dump_addr = 0x40,
296 cuc_dump_stats = 0x50,
297 cuc_load_base = 0x60,
298 cuc_dump_reset = 0x70,
302 cuc_dump_complete = 0x0000A005,
303 cuc_dump_reset_complete = 0x0000A007,
307 software_reset = 0x0000,
309 selective_reset = 0x0002,
312 enum eeprom_ctrl_lo {
320 mdi_write = 0x04000000,
321 mdi_read = 0x08000000,
322 mdi_ready = 0x10000000,
332 enum eeprom_offsets {
334 eeprom_config_asf = 0x0D,
335 eeprom_smbus_addr = 0x90,
339 eeprom_id_wol = 0x0020,
342 enum eeprom_config_asf {
348 cb_complete = 0x8000,
375 struct rx *next, *prev;
380 #if defined(__BIG_ENDIAN_BITFIELD)
386 /*0*/ u8 X(byte_count:6, pad0:2);
387 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
388 /*2*/ u8 adaptive_ifs;
389 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
390 term_write_cache_line:1), pad3:4);
391 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
392 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
393 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
394 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
395 rx_discard_overruns:1), rx_save_bad_frames:1);
396 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
397 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
399 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
400 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
401 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
402 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
404 /*11*/ u8 X(linear_priority:3, pad11:5);
405 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
406 /*13*/ u8 ip_addr_lo;
407 /*14*/ u8 ip_addr_hi;
408 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
409 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
410 pad15_2:1), crs_or_cdt:1);
411 /*16*/ u8 fc_delay_lo;
412 /*17*/ u8 fc_delay_hi;
413 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
414 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
415 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
416 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
417 full_duplex_force:1), full_duplex_pin:1);
418 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
419 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
420 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
424 #define E100_MAX_MULTICAST_ADDRS 64
427 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
430 /* Important: keep total struct u32-aligned */
437 struct config config;
450 u32 dump_buffer_addr;
452 struct cb *next, *prev;
458 lb_none = 0, lb_mac = 1, lb_phy = 3,
462 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
463 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
464 tx_multiple_collisions, tx_total_collisions;
465 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
466 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
467 rx_short_frame_errors;
468 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
469 u16 xmt_tco_frames, rcv_tco_frames;
489 struct param_range rfds;
490 struct param_range cbs;
494 /* Begin: frequently used values: keep adjacent for cache effect */
495 u32 msg_enable ____cacheline_aligned;
496 struct net_device *netdev;
497 struct pci_dev *pdev;
499 struct rx *rxs ____cacheline_aligned;
500 struct rx *rx_to_use;
501 struct rx *rx_to_clean;
502 struct rfd blank_rfd;
505 spinlock_t cb_lock ____cacheline_aligned;
508 enum scb_cmd_lo cuc_cmd;
509 unsigned int cbs_avail;
511 struct cb *cb_to_use;
512 struct cb *cb_to_send;
513 struct cb *cb_to_clean;
515 /* End: frequently used values: keep adjacent for cache effect */
519 promiscuous = (1 << 1),
520 multicast_all = (1 << 2),
521 wol_magic = (1 << 3),
522 ich_10h_workaround = (1 << 4),
523 } flags ____cacheline_aligned;
527 struct params params;
528 struct net_device_stats net_stats;
529 struct timer_list watchdog;
530 struct timer_list blink_timer;
531 struct mii_if_info mii;
532 enum loopback loopback;
537 dma_addr_t cbs_dma_addr;
543 u32 tx_single_collisions;
544 u32 tx_multiple_collisions;
549 u32 rx_fc_unsupported;
559 static inline void e100_write_flush(struct nic *nic)
561 /* Flush previous PCI writes through intermediate bridges
562 * by doing a benign read */
563 (void)readb(&nic->csr->scb.status);
566 static inline void e100_enable_irq(struct nic *nic)
568 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
569 e100_write_flush(nic);
572 static inline void e100_disable_irq(struct nic *nic)
574 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
575 e100_write_flush(nic);
578 static void e100_hw_reset(struct nic *nic)
580 /* Put CU and RU into idle with a selective reset to get
581 * device off of PCI bus */
582 writel(selective_reset, &nic->csr->port);
583 e100_write_flush(nic); udelay(20);
585 /* Now fully reset device */
586 writel(software_reset, &nic->csr->port);
587 e100_write_flush(nic); udelay(20);
589 /* TCO workaround - 82559 and greater */
590 if(nic->mac >= mac_82559_D101M) {
591 /* Issue a redundant CU load base without setting
592 * general pointer, and without waiting for scb to
593 * clear. This gets us into post-driver. Finally,
594 * wait 20 msec for reset to take effect. */
595 writeb(cuc_load_base, &nic->csr->scb.cmd_lo);
599 /* Mask off our interrupt line - it's unmasked after reset */
600 e100_disable_irq(nic);
603 static int e100_self_test(struct nic *nic)
605 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
607 /* Passing the self-test is a pretty good indication
608 * that the device can DMA to/from host memory */
610 nic->mem->selftest.signature = 0;
611 nic->mem->selftest.result = 0xFFFFFFFF;
613 writel(selftest | dma_addr, &nic->csr->port);
614 e100_write_flush(nic);
615 /* Wait 10 msec for self-test to complete */
616 set_current_state(TASK_UNINTERRUPTIBLE);
617 schedule_timeout(HZ / 100 + 1);
619 /* Interrupts are enabled after self-test */
620 e100_disable_irq(nic);
622 /* Check results of self-test */
623 if(nic->mem->selftest.result != 0) {
624 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
625 nic->mem->selftest.result);
628 if(nic->mem->selftest.signature == 0) {
629 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
636 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
638 u32 cmd_addr_data[3];
642 /* Three cmds: write/erase enable, write data, write/erase disable */
643 cmd_addr_data[0] = op_ewen << (addr_len - 2);
644 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) | data;
645 cmd_addr_data[2] = op_ewds << (addr_len - 2);
647 /* Bit-bang cmds to write word to eeprom */
648 for(j = 0; j < 3; j++) {
651 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
652 e100_write_flush(nic); udelay(4);
654 for(i = 31; i >= 0; i--) {
655 ctrl = (cmd_addr_data[j] & (1 << i)) ?
657 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
658 e100_write_flush(nic); udelay(4);
660 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
661 e100_write_flush(nic); udelay(4);
663 /* Wait 10 msec for cmd to complete */
664 set_current_state(TASK_UNINTERRUPTIBLE);
665 schedule_timeout(HZ / 100 + 1);
668 writeb(0, &nic->csr->eeprom_ctrl_lo);
669 e100_write_flush(nic); udelay(4);
674 /* General technique stolen from the eepro100 driver - very clever */
675 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
682 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
685 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
686 e100_write_flush(nic); udelay(4);
688 /* Bit-bang to read word from eeprom */
689 for(i = 31; i >= 0; i--) {
690 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
691 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
692 e100_write_flush(nic); udelay(4);
694 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
695 e100_write_flush(nic); udelay(4);
697 /* Eeprom drives a dummy zero to EEDO after receiving
698 * complete address. Use this to adjust addr_len. */
699 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
700 if(!(ctrl & eedo) && i > 16) {
701 *addr_len -= (i - 16);
705 data = (data << 1) | (ctrl & eedo ? 1 : 0);
709 writeb(0, &nic->csr->eeprom_ctrl_lo);
710 e100_write_flush(nic); udelay(4);
715 /* Load entire EEPROM image into driver cache and validate checksum */
716 static int e100_eeprom_load(struct nic *nic)
718 u16 addr, addr_len = 8, checksum = 0;
720 /* Try reading with an 8-bit addr len to discover actual addr len */
721 e100_eeprom_read(nic, &addr_len, 0);
722 nic->eeprom_wc = 1 << addr_len;
724 for(addr = 0; addr < nic->eeprom_wc; addr++) {
725 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
726 if(addr < nic->eeprom_wc - 1)
727 checksum += nic->eeprom[addr];
730 /* The checksum, stored in the last word, is calculated such that
731 * the sum of words should be 0xBABA */
732 checksum = 0xBABA - checksum;
733 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
734 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
741 /* Save (portion of) driver EEPROM cache to device and update checksum */
742 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
744 u16 addr, addr_len = 8, checksum = 0;
746 /* Try reading with an 8-bit addr len to discover actual addr len */
747 e100_eeprom_read(nic, &addr_len, 0);
748 nic->eeprom_wc = 1 << addr_len;
750 if(start + count >= nic->eeprom_wc)
753 for(addr = start; addr < start + count; addr++)
754 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
756 /* The checksum, stored in the last word, is calculated such that
757 * the sum of words should be 0xBABA */
758 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
759 checksum += nic->eeprom[addr];
760 nic->eeprom[nic->eeprom_wc - 1] = 0xBABA - checksum;
761 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1, 0xBABA - checksum);
766 #define E100_WAIT_SCB_TIMEOUT 40
767 static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
773 spin_lock_irqsave(&nic->cmd_lock, flags);
775 /* Previous command is accepted when SCB clears */
776 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
777 if(likely(!readb(&nic->csr->scb.cmd_lo)))
780 if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
783 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
788 if(unlikely(cmd != cuc_resume))
789 writel(dma_addr, &nic->csr->scb.gen_ptr);
790 writeb(cmd, &nic->csr->scb.cmd_lo);
793 spin_unlock_irqrestore(&nic->cmd_lock, flags);
798 static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
799 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
805 spin_lock_irqsave(&nic->cb_lock, flags);
807 if(unlikely(!nic->cbs_avail)) {
813 nic->cb_to_use = cb->next;
817 if(unlikely(!nic->cbs_avail))
820 cb_prepare(nic, cb, skb);
822 /* Order is important otherwise we'll be in a race with h/w:
823 * set S-bit in current first, then clear S-bit in previous. */
824 cb->command |= cpu_to_le16(cb_s);
826 cb->prev->command &= cpu_to_le16(~cb_s);
828 while(nic->cb_to_send != nic->cb_to_use) {
829 if(unlikely((err = e100_exec_cmd(nic, nic->cuc_cmd,
830 nic->cb_to_send->dma_addr)))) {
831 /* Ok, here's where things get sticky. It's
832 * possible that we can't schedule the command
833 * because the controller is too busy, so
834 * let's just queue the command and try again
835 * when another command is scheduled. */
838 nic->cuc_cmd = cuc_resume;
839 nic->cb_to_send = nic->cb_to_send->next;
844 spin_unlock_irqrestore(&nic->cb_lock, flags);
849 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
854 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
856 for(i = 0; i < 100; i++) {
858 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
863 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
864 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
865 return (u16)data_out;
868 static int mdio_read(struct net_device *netdev, int addr, int reg)
870 return mdio_ctrl(netdev->priv, addr, mdi_read, reg, 0);
873 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
875 mdio_ctrl(netdev->priv, addr, mdi_write, reg, data);
878 static void e100_get_defaults(struct nic *nic)
880 struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
881 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
883 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
884 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
885 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
886 if(nic->mac == mac_unknown)
887 nic->mac = mac_82557_D100_A;
889 nic->params.rfds = rfds;
890 nic->params.cbs = cbs;
892 /* Quadwords to DMA into FIFO before starting frame transmit */
893 nic->tx_threshold = 0xE0;
895 nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
896 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));
898 /* Template for a freshly allocated RFD */
899 nic->blank_rfd.command = cpu_to_le16(cb_el);
900 nic->blank_rfd.rbd = 0xFFFFFFFF;
901 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
904 nic->mii.phy_id_mask = 0x1F;
905 nic->mii.reg_num_mask = 0x1F;
906 nic->mii.dev = nic->netdev;
907 nic->mii.mdio_read = mdio_read;
908 nic->mii.mdio_write = mdio_write;
911 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
913 struct config *config = &cb->u.config;
914 u8 *c = (u8 *)config;
916 cb->command = cpu_to_le16(cb_config);
918 memset(config, 0, sizeof(struct config));
920 config->byte_count = 0x16; /* bytes in this struct */
921 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
922 config->direct_rx_dma = 0x1; /* reserved */
923 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
924 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
925 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
926 config->tx_underrun_retry = 0x3; /* # of underrun retries */
927 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
929 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
930 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
931 config->ifs = 0x6; /* x16 = inter frame spacing */
932 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
933 config->pad15_1 = 0x1;
934 config->pad15_2 = 0x1;
935 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
936 config->fc_delay_hi = 0x40; /* time delay for fc frame */
937 config->tx_padding = 0x1; /* 1=pad short frames */
938 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
940 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
941 config->pad20_1 = 0x1F;
942 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
943 config->pad21_1 = 0x5;
945 config->adaptive_ifs = nic->adaptive_ifs;
946 config->loopback = nic->loopback;
948 if(nic->mii.force_media && nic->mii.full_duplex)
949 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
951 if(nic->flags & promiscuous || nic->loopback) {
952 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
953 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
954 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
957 if(nic->flags & multicast_all)
958 config->multicast_all = 0x1; /* 1=accept, 0=no */
960 if(!(nic->flags & wol_magic))
961 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
963 if(nic->mac >= mac_82558_D101_A4) {
964 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
965 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
966 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
967 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
968 if(nic->mac >= mac_82559_D101M)
969 config->tno_intr = 0x1; /* TCO stats enable */
971 config->standard_stat_counter = 0x0;
974 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
975 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
976 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
977 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
978 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
979 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
982 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
985 cb->command = cpu_to_le16(cb_iaaddr);
986 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
989 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
991 cb->command = cpu_to_le16(cb_dump);
992 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
993 offsetof(struct mem, dump_buf));
996 #define NCONFIG_AUTO_SWITCH 0x0080
997 #define MII_NSC_CONG MII_RESV1
998 #define NSC_CONG_ENABLE 0x0100
999 #define NSC_CONG_TXREADY 0x0400
1000 #define ADVERTISE_FC_SUPPORTED 0x0400
1001 static int e100_phy_init(struct nic *nic)
1003 struct net_device *netdev = nic->netdev;
1005 u16 bmcr, stat, id_lo, id_hi, cong;
1007 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1008 for(addr = 0; addr < 32; addr++) {
1009 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1010 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1011 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1012 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1013 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1016 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1020 /* Selected the phy and isolate the rest */
1021 for(addr = 0; addr < 32; addr++) {
1022 if(addr != nic->mii.phy_id) {
1023 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1025 bmcr = mdio_read(netdev, addr, MII_BMCR);
1026 mdio_write(netdev, addr, MII_BMCR,
1027 bmcr & ~BMCR_ISOLATE);
1032 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1033 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1034 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1035 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1037 /* Handle National tx phys */
1038 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1039 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1040 /* Disable congestion control */
1041 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1042 cong |= NSC_CONG_TXREADY;
1043 cong &= ~NSC_CONG_ENABLE;
1044 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1047 if(nic->mac >= mac_82550_D102)
1048 /* enable/disable MDI/MDI-X auto-switching */
1049 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1050 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1055 static int e100_hw_init(struct nic *nic)
1061 DPRINTK(HW, ERR, "e100_hw_init\n");
1062 if(!in_interrupt() && (err = e100_self_test(nic)))
1065 if((err = e100_phy_init(nic)))
1067 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1069 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1071 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1073 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1075 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1076 nic->dma_addr + offsetof(struct mem, stats))))
1078 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1081 e100_disable_irq(nic);
1086 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1088 struct net_device *netdev = nic->netdev;
1089 struct dev_mc_list *list = netdev->mc_list;
1090 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1092 cb->command = cpu_to_le16(cb_multi);
1093 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1094 for(i = 0; list && i < count; i++, list = list->next)
1095 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1099 static void e100_set_multicast_list(struct net_device *netdev)
1101 struct nic *nic = netdev->priv;
1103 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1104 netdev->mc_count, netdev->flags);
1106 if(netdev->flags & IFF_PROMISC)
1107 nic->flags |= promiscuous;
1109 nic->flags &= ~promiscuous;
1111 if(netdev->flags & IFF_ALLMULTI ||
1112 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1113 nic->flags |= multicast_all;
1115 nic->flags &= ~multicast_all;
1117 e100_exec_cb(nic, NULL, e100_configure);
1118 e100_exec_cb(nic, NULL, e100_multi);
1121 static void e100_update_stats(struct nic *nic)
1123 struct net_device_stats *ns = &nic->net_stats;
1124 struct stats *s = &nic->mem->stats;
1125 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1126 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1129 /* Device's stats reporting may take several microseconds to
1130 * complete, so where always waiting for results of the
1131 * previous command. */
1133 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1135 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1136 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1137 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1138 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1139 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1140 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1141 ns->collisions += nic->tx_collisions;
1142 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1143 le32_to_cpu(s->tx_lost_crs);
1144 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1145 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors);
1146 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1147 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1148 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1149 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1150 le32_to_cpu(s->rx_alignment_errors) +
1151 le32_to_cpu(s->rx_short_frame_errors) +
1152 le32_to_cpu(s->rx_cdt_errors);
1153 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1154 nic->tx_single_collisions +=
1155 le32_to_cpu(s->tx_single_collisions);
1156 nic->tx_multiple_collisions +=
1157 le32_to_cpu(s->tx_multiple_collisions);
1158 if(nic->mac >= mac_82558_D101_A4) {
1159 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1160 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1161 nic->rx_fc_unsupported +=
1162 le32_to_cpu(s->fc_rcv_unsupported);
1163 if(nic->mac >= mac_82559_D101M) {
1164 nic->tx_tco_frames +=
1165 le16_to_cpu(s->xmt_tco_frames);
1166 nic->rx_tco_frames +=
1167 le16_to_cpu(s->rcv_tco_frames);
1172 e100_exec_cmd(nic, cuc_dump_reset, 0);
1175 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1177 /* Adjust inter-frame-spacing (IFS) between two transmits if
1178 * we're getting collisions on a half-duplex connection. */
1180 if(duplex == DUPLEX_HALF) {
1181 u32 prev = nic->adaptive_ifs;
1182 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1184 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1185 (nic->tx_frames > min_frames)) {
1186 if(nic->adaptive_ifs < 60)
1187 nic->adaptive_ifs += 5;
1188 } else if (nic->tx_frames < min_frames) {
1189 if(nic->adaptive_ifs >= 5)
1190 nic->adaptive_ifs -= 5;
1192 if(nic->adaptive_ifs != prev)
1193 e100_exec_cb(nic, NULL, e100_configure);
1197 static void e100_watchdog(unsigned long data)
1199 struct nic *nic = (struct nic *)data;
1200 struct ethtool_cmd cmd;
1202 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1204 /* mii library handles link maintenance tasks */
1206 mii_ethtool_gset(&nic->mii, &cmd);
1208 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1209 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1210 cmd.speed == SPEED_100 ? "100" : "10",
1211 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1212 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1213 DPRINTK(LINK, INFO, "link down\n");
1216 mii_check_link(&nic->mii);
1218 /* Software generated interrupt to recover from (rare) Rx
1219 * allocation failure */
1220 writeb(irq_sw_gen, &nic->csr->scb.cmd_hi);
1221 e100_write_flush(nic);
1223 e100_update_stats(nic);
1224 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1226 if(nic->mac <= mac_82557_D100_C)
1227 /* Issue a multicast command to workaround a 557 lock up */
1228 e100_set_multicast_list(nic->netdev);
1230 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1231 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1232 nic->flags |= ich_10h_workaround;
1234 nic->flags &= ~ich_10h_workaround;
1236 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1239 static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1240 struct sk_buff *skb)
1242 cb->command = nic->tx_command;
1243 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1244 cb->u.tcb.tcb_byte_count = 0;
1245 cb->u.tcb.threshold = nic->tx_threshold;
1246 cb->u.tcb.tbd_count = 1;
1247 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1248 skb->data, skb->len, PCI_DMA_TODEVICE));
1249 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1252 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1254 struct nic *nic = netdev->priv;
1257 if(nic->flags & ich_10h_workaround) {
1258 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1259 Issue a NOP command followed by a 1us delay before
1260 issuing the Tx command. */
1261 e100_exec_cmd(nic, cuc_nop, 0);
1265 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1269 /* We queued the skb, but now we're out of space. */
1270 netif_stop_queue(netdev);
1273 /* This is a hard error - log it. */
1274 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1275 netif_stop_queue(netdev);
1279 netdev->trans_start = jiffies;
1283 static inline int e100_tx_clean(struct nic *nic)
1288 spin_lock(&nic->cb_lock);
1290 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1291 nic->cb_to_clean->status);
1293 /* Clean CBs marked complete */
1294 for(cb = nic->cb_to_clean;
1295 cb->status & cpu_to_le16(cb_complete);
1296 cb = nic->cb_to_clean = cb->next) {
1297 if(likely(cb->skb != NULL)) {
1298 nic->net_stats.tx_packets++;
1299 nic->net_stats.tx_bytes += cb->skb->len;
1301 pci_unmap_single(nic->pdev,
1302 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1303 le16_to_cpu(cb->u.tcb.tbd.size),
1305 dev_kfree_skb_any(cb->skb);
1313 spin_unlock(&nic->cb_lock);
1315 /* Recover from running out of Tx resources in xmit_frame */
1316 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1317 netif_wake_queue(nic->netdev);
1322 static void e100_clean_cbs(struct nic *nic)
1325 while(nic->cb_to_clean != nic->cb_to_use) {
1326 struct cb *cb = nic->cb_to_clean;
1328 pci_unmap_single(nic->pdev,
1329 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1330 le16_to_cpu(cb->u.tcb.tbd.size),
1332 dev_kfree_skb(cb->skb);
1334 nic->cb_to_clean = nic->cb_to_clean->next;
1336 nic->cbs_avail = nic->params.cbs.count;
1337 pci_free_consistent(nic->pdev,
1338 sizeof(struct cb) * nic->params.cbs.count,
1339 nic->cbs, nic->cbs_dma_addr);
1343 nic->cuc_cmd = cuc_start;
1344 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1348 static int e100_alloc_cbs(struct nic *nic)
1351 unsigned int i, count = nic->params.cbs.count;
1353 nic->cuc_cmd = cuc_start;
1354 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1357 nic->cbs = pci_alloc_consistent(nic->pdev,
1358 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1362 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1363 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1364 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1366 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1367 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1368 ((i+1) % count) * sizeof(struct cb));
1372 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1373 nic->cbs_avail = count;
1378 static inline void e100_start_receiver(struct nic *nic)
1380 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1381 if(!nic->ru_running && nic->rx_to_clean->skb) {
1382 e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr);
1383 nic->ru_running = 1;
1387 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1388 static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1390 unsigned int rx_offset = 2; /* u32 align protocol headers */
1392 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + rx_offset)))
1395 /* Align, init, and map the RFA. */
1396 rx->skb->dev = nic->netdev;
1397 skb_reserve(rx->skb, rx_offset);
1398 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1399 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1400 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1402 /* Link the RFD to end of RFA by linking previous RFD to
1403 * this one, and clearing EL bit of previous. */
1405 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1406 put_unaligned(cpu_to_le32(rx->dma_addr),
1407 (u32 *)&prev_rfd->link);
1409 prev_rfd->command &= ~cpu_to_le16(cb_el);
1410 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1411 sizeof(struct rfd), PCI_DMA_TODEVICE);
1417 static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1418 unsigned int *work_done, unsigned int work_to_do)
1420 struct sk_buff *skb = rx->skb;
1421 struct rfd *rfd = (struct rfd *)skb->data;
1422 u16 rfd_status, actual_size;
1424 if(unlikely(work_done && *work_done >= work_to_do))
1427 /* Need to sync before taking a peek at cb_complete bit */
1428 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1429 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1430 rfd_status = le16_to_cpu(rfd->status);
1432 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1434 /* If data isn't ready, nothing to indicate */
1435 if(unlikely(!(rfd_status & cb_complete)))
1438 /* Get actual data size */
1439 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1440 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1441 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1444 pci_unmap_single(nic->pdev, rx->dma_addr,
1445 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1447 /* Pull off the RFD and put the actual data (minus eth hdr) */
1448 skb_reserve(skb, sizeof(struct rfd));
1449 skb_put(skb, actual_size);
1450 skb->protocol = eth_type_trans(skb, nic->netdev);
1452 if(unlikely(!(rfd_status & cb_ok))) {
1453 /* Don't indicate if hardware indicates errors */
1454 nic->net_stats.rx_dropped++;
1455 dev_kfree_skb_any(skb);
1456 } else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
1457 /* Don't indicate oversized frames */
1458 nic->net_stats.rx_over_errors++;
1459 nic->net_stats.rx_dropped++;
1460 dev_kfree_skb_any(skb);
1462 nic->net_stats.rx_packets++;
1463 nic->net_stats.rx_bytes += actual_size;
1464 nic->netdev->last_rx = jiffies;
1465 #ifdef CONFIG_E100_NAPI
1466 netif_receive_skb(skb);
1479 static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1480 unsigned int work_to_do)
1484 /* Indicate newly arrived packets */
1485 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1486 if(e100_rx_indicate(nic, rx, work_done, work_to_do))
1487 break; /* No more to clean */
1490 /* Alloc new skbs to refill list */
1491 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1492 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1493 break; /* Better luck next time (see watchdog) */
1496 e100_start_receiver(nic);
1499 static void e100_rx_clean_list(struct nic *nic)
1502 unsigned int i, count = nic->params.rfds.count;
1505 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1507 pci_unmap_single(nic->pdev, rx->dma_addr,
1508 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1509 dev_kfree_skb(rx->skb);
1516 nic->rx_to_use = nic->rx_to_clean = NULL;
1517 nic->ru_running = 0;
1520 static int e100_rx_alloc_list(struct nic *nic)
1523 unsigned int i, count = nic->params.rfds.count;
1525 nic->rx_to_use = nic->rx_to_clean = NULL;
1527 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1529 memset(nic->rxs, 0, sizeof(struct rx) * count);
1531 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1532 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1533 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1534 if(e100_rx_alloc_skb(nic, rx)) {
1535 e100_rx_clean_list(nic);
1540 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1545 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1547 struct net_device *netdev = dev_id;
1548 struct nic *nic = netdev->priv;
1549 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1551 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1553 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1554 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1557 /* Ack interrupt(s) */
1558 writeb(stat_ack, &nic->csr->scb.stat_ack);
1560 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1561 if(stat_ack & stat_ack_rnr)
1562 nic->ru_running = 0;
1564 #ifdef CONFIG_E100_NAPI
1565 e100_disable_irq(nic);
1566 netif_rx_schedule(netdev);
1568 if(stat_ack & stat_ack_rx)
1569 e100_rx_clean(nic, NULL, 0);
1570 if(stat_ack & stat_ack_tx)
1577 #ifdef CONFIG_E100_NAPI
1578 static int e100_poll(struct net_device *netdev, int *budget)
1580 struct nic *nic = netdev->priv;
1581 unsigned int work_to_do = min(netdev->quota, *budget);
1582 unsigned int work_done = 0;
1585 e100_rx_clean(nic, &work_done, work_to_do);
1586 tx_cleaned = e100_tx_clean(nic);
1588 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1589 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1590 netif_rx_complete(netdev);
1591 e100_enable_irq(nic);
1595 *budget -= work_done;
1596 netdev->quota -= work_done;
1602 #ifdef CONFIG_NET_POLL_CONTROLLER
1603 static void e100_netpoll(struct net_device *netdev)
1605 struct nic *nic = netdev->priv;
1606 e100_disable_irq(nic);
1607 e100_intr(nic->pdev->irq, netdev, NULL);
1608 e100_enable_irq(nic);
1612 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1614 struct nic *nic = netdev->priv;
1615 return &nic->net_stats;
1618 static int e100_set_mac_address(struct net_device *netdev, void *p)
1620 struct nic *nic = netdev->priv;
1621 struct sockaddr *addr = p;
1623 if (!is_valid_ether_addr(addr->sa_data))
1624 return -EADDRNOTAVAIL;
1626 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1627 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1632 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1634 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1636 netdev->mtu = new_mtu;
1640 static int e100_asf(struct nic *nic)
1642 /* ASF can be enabled from eeprom */
1643 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1055) &&
1644 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1645 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1646 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1649 static int e100_up(struct nic *nic)
1653 if((err = e100_rx_alloc_list(nic)))
1655 if((err = e100_alloc_cbs(nic)))
1656 goto err_rx_clean_list;
1657 if((err = e100_hw_init(nic)))
1659 e100_set_multicast_list(nic->netdev);
1660 e100_start_receiver(nic);
1661 netif_start_queue(nic->netdev);
1662 mod_timer(&nic->watchdog, jiffies);
1663 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1664 nic->netdev->name, nic->netdev)))
1666 e100_enable_irq(nic);
1670 del_timer_sync(&nic->watchdog);
1671 netif_stop_queue(nic->netdev);
1673 e100_clean_cbs(nic);
1675 e100_rx_clean_list(nic);
1679 static void e100_down(struct nic *nic)
1682 free_irq(nic->pdev->irq, nic->netdev);
1683 del_timer_sync(&nic->watchdog);
1684 netif_carrier_off(nic->netdev);
1685 netif_stop_queue(nic->netdev);
1686 e100_clean_cbs(nic);
1687 e100_rx_clean_list(nic);
1690 static void e100_tx_timeout(struct net_device *netdev)
1692 struct nic *nic = netdev->priv;
1694 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1695 readb(&nic->csr->scb.status));
1696 e100_down(netdev->priv);
1697 e100_up(netdev->priv);
1700 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1703 struct sk_buff *skb;
1705 /* Use driver resources to perform internal MAC or PHY
1706 * loopback test. A single packet is prepared and transmitted
1707 * in loopback mode, and the test passes if the received
1708 * packet compares byte-for-byte to the transmitted packet. */
1710 if((err = e100_rx_alloc_list(nic)))
1712 if((err = e100_alloc_cbs(nic)))
1715 /* ICH PHY loopback is broken so do MAC loopback instead */
1716 if(nic->flags & ich && loopback_mode == lb_phy)
1717 loopback_mode = lb_mac;
1719 nic->loopback = loopback_mode;
1720 if((err = e100_hw_init(nic)))
1721 goto err_loopback_none;
1723 if(loopback_mode == lb_phy)
1724 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1727 e100_start_receiver(nic);
1729 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1731 goto err_loopback_none;
1733 skb_put(skb, ETH_DATA_LEN);
1734 memset(skb->data, 0xFF, ETH_DATA_LEN);
1735 e100_xmit_frame(skb, nic->netdev);
1737 set_current_state(TASK_UNINTERRUPTIBLE);
1738 schedule_timeout(HZ / 100 + 1);
1740 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1741 skb->data, ETH_DATA_LEN))
1745 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
1746 nic->loopback = lb_none;
1748 e100_clean_cbs(nic);
1750 e100_rx_clean_list(nic);
1754 #define MII_LED_CONTROL 0x1B
1755 static void e100_blink_led(unsigned long data)
1757 struct nic *nic = (struct nic *)data;
1765 nic->leds = (nic->leds & led_on) ? led_off :
1766 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
1767 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
1768 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
1771 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1773 struct nic *nic = netdev->priv;
1774 return mii_ethtool_gset(&nic->mii, cmd);
1777 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1779 struct nic *nic = netdev->priv;
1782 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
1783 err = mii_ethtool_sset(&nic->mii, cmd);
1784 e100_exec_cb(nic, NULL, e100_configure);
1789 static void e100_get_drvinfo(struct net_device *netdev,
1790 struct ethtool_drvinfo *info)
1792 struct nic *nic = netdev->priv;
1793 strcpy(info->driver, DRV_NAME);
1794 strcpy(info->version, DRV_VERSION);
1795 strcpy(info->fw_version, "N/A");
1796 strcpy(info->bus_info, pci_name(nic->pdev));
1799 static int e100_get_regs_len(struct net_device *netdev)
1801 struct nic *nic = netdev->priv;
1802 #define E100_PHY_REGS 0x1C
1803 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
1804 sizeof(nic->mem->dump_buf) / sizeof(u32)
1805 return E100_REGS_LEN * sizeof(u32);
1808 static void e100_get_regs(struct net_device *netdev,
1809 struct ethtool_regs *regs, void *p)
1811 struct nic *nic = netdev->priv;
1815 regs->version = (1 << 24) | nic->rev_id;
1816 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
1817 readb(&nic->csr->scb.cmd_lo) << 16 |
1818 readw(&nic->csr->scb.status);
1819 for(i = E100_PHY_REGS; i >= 0; i--)
1820 buff[1 + E100_PHY_REGS - i] =
1821 mdio_read(netdev, nic->mii.phy_id, i);
1822 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
1823 e100_exec_cb(nic, NULL, e100_dump);
1824 set_current_state(TASK_UNINTERRUPTIBLE);
1825 schedule_timeout(HZ / 100 + 1);
1826 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
1827 sizeof(nic->mem->dump_buf));
1830 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1832 struct nic *nic = netdev->priv;
1833 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
1834 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
1837 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1839 struct nic *nic = netdev->priv;
1841 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
1845 nic->flags |= wol_magic;
1847 nic->flags &= ~wol_magic;
1849 pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
1850 e100_exec_cb(nic, NULL, e100_configure);
1855 static u32 e100_get_msglevel(struct net_device *netdev)
1857 struct nic *nic = netdev->priv;
1858 return nic->msg_enable;
1861 static void e100_set_msglevel(struct net_device *netdev, u32 value)
1863 struct nic *nic = netdev->priv;
1864 nic->msg_enable = value;
1867 static int e100_nway_reset(struct net_device *netdev)
1869 struct nic *nic = netdev->priv;
1870 return mii_nway_restart(&nic->mii);
1873 static u32 e100_get_link(struct net_device *netdev)
1875 struct nic *nic = netdev->priv;
1876 return mii_link_ok(&nic->mii);
1879 static int e100_get_eeprom_len(struct net_device *netdev)
1881 struct nic *nic = netdev->priv;
1882 return nic->eeprom_wc << 1;
1885 #define E100_EEPROM_MAGIC 0x1234
1886 static int e100_get_eeprom(struct net_device *netdev,
1887 struct ethtool_eeprom *eeprom, u8 *bytes)
1889 struct nic *nic = netdev->priv;
1891 eeprom->magic = E100_EEPROM_MAGIC;
1892 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
1897 static int e100_set_eeprom(struct net_device *netdev,
1898 struct ethtool_eeprom *eeprom, u8 *bytes)
1900 struct nic *nic = netdev->priv;
1902 if(eeprom->magic != E100_EEPROM_MAGIC)
1904 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
1906 return e100_eeprom_save(nic, eeprom->offset >> 1,
1907 (eeprom->len >> 1) + 1);
1910 static void e100_get_ringparam(struct net_device *netdev,
1911 struct ethtool_ringparam *ring)
1913 struct nic *nic = netdev->priv;
1914 struct param_range *rfds = &nic->params.rfds;
1915 struct param_range *cbs = &nic->params.cbs;
1917 ring->rx_max_pending = rfds->max;
1918 ring->tx_max_pending = cbs->max;
1919 ring->rx_mini_max_pending = 0;
1920 ring->rx_jumbo_max_pending = 0;
1921 ring->rx_pending = rfds->count;
1922 ring->tx_pending = cbs->count;
1923 ring->rx_mini_pending = 0;
1924 ring->rx_jumbo_pending = 0;
1927 static int e100_set_ringparam(struct net_device *netdev,
1928 struct ethtool_ringparam *ring)
1930 struct nic *nic = netdev->priv;
1931 struct param_range *rfds = &nic->params.rfds;
1932 struct param_range *cbs = &nic->params.cbs;
1934 if(netif_running(netdev))
1936 rfds->count = max(ring->rx_pending, rfds->min);
1937 rfds->count = min(rfds->count, rfds->max);
1938 cbs->count = max(ring->tx_pending, cbs->min);
1939 cbs->count = min(cbs->count, cbs->max);
1940 if(netif_running(netdev))
1946 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
1947 "Link test (on/offline)",
1948 "Eeprom test (on/offline)",
1949 "Self test (offline)",
1950 "Mac loopback (offline)",
1951 "Phy loopback (offline)",
1953 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
1955 static int e100_diag_test_count(struct net_device *netdev)
1957 return E100_TEST_LEN;
1960 static void e100_diag_test(struct net_device *netdev,
1961 struct ethtool_test *test, u64 *data)
1963 struct nic *nic = netdev->priv;
1966 memset(data, 0, E100_TEST_LEN * sizeof(u64));
1967 data[0] = !mii_link_ok(&nic->mii);
1968 data[1] = e100_eeprom_load(nic);
1969 if(test->flags & ETH_TEST_FL_OFFLINE) {
1970 if(netif_running(netdev))
1972 data[2] = e100_self_test(nic);
1973 data[3] = e100_loopback_test(nic, lb_mac);
1974 data[4] = e100_loopback_test(nic, lb_phy);
1975 if(netif_running(netdev))
1978 for(i = 0; i < E100_TEST_LEN; i++)
1979 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
1982 static int e100_phys_id(struct net_device *netdev, u32 data)
1984 struct nic *nic = netdev->priv;
1986 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1987 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1988 mod_timer(&nic->blink_timer, jiffies);
1989 set_current_state(TASK_INTERRUPTIBLE);
1990 schedule_timeout(data * HZ);
1991 del_timer_sync(&nic->blink_timer);
1992 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
1997 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
1998 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1999 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2000 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2001 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2002 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2003 "tx_heartbeat_errors", "tx_window_errors",
2004 /* device-specific stats */
2005 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2006 "tx_flow_control_pause", "rx_flow_control_pause",
2007 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2009 #define E100_NET_STATS_LEN 21
2010 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2012 static int e100_get_stats_count(struct net_device *netdev)
2014 return E100_STATS_LEN;
2017 static void e100_get_ethtool_stats(struct net_device *netdev,
2018 struct ethtool_stats *stats, u64 *data)
2020 struct nic *nic = netdev->priv;
2023 for(i = 0; i < E100_NET_STATS_LEN; i++)
2024 data[i] = ((unsigned long *)&nic->net_stats)[i];
2026 data[i++] = nic->tx_deferred;
2027 data[i++] = nic->tx_single_collisions;
2028 data[i++] = nic->tx_multiple_collisions;
2029 data[i++] = nic->tx_fc_pause;
2030 data[i++] = nic->rx_fc_pause;
2031 data[i++] = nic->rx_fc_unsupported;
2032 data[i++] = nic->tx_tco_frames;
2033 data[i++] = nic->rx_tco_frames;
2036 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2040 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2043 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2048 static struct ethtool_ops e100_ethtool_ops = {
2049 .get_settings = e100_get_settings,
2050 .set_settings = e100_set_settings,
2051 .get_drvinfo = e100_get_drvinfo,
2052 .get_regs_len = e100_get_regs_len,
2053 .get_regs = e100_get_regs,
2054 .get_wol = e100_get_wol,
2055 .set_wol = e100_set_wol,
2056 .get_msglevel = e100_get_msglevel,
2057 .set_msglevel = e100_set_msglevel,
2058 .nway_reset = e100_nway_reset,
2059 .get_link = e100_get_link,
2060 .get_eeprom_len = e100_get_eeprom_len,
2061 .get_eeprom = e100_get_eeprom,
2062 .set_eeprom = e100_set_eeprom,
2063 .get_ringparam = e100_get_ringparam,
2064 .set_ringparam = e100_set_ringparam,
2065 .self_test_count = e100_diag_test_count,
2066 .self_test = e100_diag_test,
2067 .get_strings = e100_get_strings,
2068 .phys_id = e100_phys_id,
2069 .get_stats_count = e100_get_stats_count,
2070 .get_ethtool_stats = e100_get_ethtool_stats,
2073 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2075 struct nic *nic = netdev->priv;
2076 struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&ifr->ifr_data;
2078 return generic_mii_ioctl(&nic->mii, mii, cmd, NULL);
2081 static int e100_alloc(struct nic *nic)
2083 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2085 return nic->mem ? 0 : -ENOMEM;
2088 static void e100_free(struct nic *nic)
2091 pci_free_consistent(nic->pdev, sizeof(struct mem),
2092 nic->mem, nic->dma_addr);
2097 static int e100_open(struct net_device *netdev)
2099 struct nic *nic = netdev->priv;
2102 netif_carrier_off(netdev);
2103 if((err = e100_up(nic)))
2104 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2108 static int e100_close(struct net_device *netdev)
2110 e100_down(netdev->priv);
2114 static int __devinit e100_probe(struct pci_dev *pdev,
2115 const struct pci_device_id *ent)
2117 struct net_device *netdev;
2121 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2122 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2123 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2127 netdev->open = e100_open;
2128 netdev->stop = e100_close;
2129 netdev->hard_start_xmit = e100_xmit_frame;
2130 netdev->get_stats = e100_get_stats;
2131 netdev->set_multicast_list = e100_set_multicast_list;
2132 netdev->set_mac_address = e100_set_mac_address;
2133 netdev->change_mtu = e100_change_mtu;
2134 netdev->do_ioctl = e100_do_ioctl;
2135 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2136 netdev->tx_timeout = e100_tx_timeout;
2137 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2138 #ifdef CONFIG_E100_NAPI
2139 netdev->poll = e100_poll;
2140 netdev->weight = E100_NAPI_WEIGHT;
2142 #ifdef CONFIG_NET_POLL_CONTROLLER
2143 netdev->poll_controller = e100_netpoll;
2147 nic->netdev = netdev;
2149 nic->msg_enable = (1 << debug) - 1;
2150 pci_set_drvdata(pdev, netdev);
2152 if((err = pci_enable_device(pdev))) {
2153 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2154 goto err_out_free_dev;
2157 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2158 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2159 "base address, aborting.\n");
2161 goto err_out_disable_pdev;
2164 if((err = pci_request_regions(pdev, DRV_NAME))) {
2165 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2166 goto err_out_disable_pdev;
2169 pci_set_master(pdev);
2171 if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
2172 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2173 goto err_out_free_res;
2176 SET_MODULE_OWNER(netdev);
2177 SET_NETDEV_DEV(netdev, &pdev->dev);
2179 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2181 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2183 goto err_out_free_res;
2186 if(ent->driver_data)
2191 spin_lock_init(&nic->cb_lock);
2192 spin_lock_init(&nic->cmd_lock);
2194 init_timer(&nic->watchdog);
2195 nic->watchdog.function = e100_watchdog;
2196 nic->watchdog.data = (unsigned long)nic;
2197 init_timer(&nic->blink_timer);
2198 nic->blink_timer.function = e100_blink_led;
2199 nic->blink_timer.data = (unsigned long)nic;
2201 if((err = e100_alloc(nic))) {
2202 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2203 goto err_out_iounmap;
2206 e100_get_defaults(nic);
2210 if((err = e100_eeprom_load(nic)))
2212 ((u16 *)netdev->dev_addr)[0] = le16_to_cpu(nic->eeprom[0]);
2213 ((u16 *)netdev->dev_addr)[1] = le16_to_cpu(nic->eeprom[1]);
2214 ((u16 *)netdev->dev_addr)[2] = le16_to_cpu(nic->eeprom[2]);
2215 if(!is_valid_ether_addr(netdev->dev_addr)) {
2216 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2217 "EEPROM, aborting.\n");
2222 /* Wol magic packet can be enabled from eeprom */
2223 if((nic->mac >= mac_82558_D101_A4) &&
2224 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2225 nic->flags |= wol_magic;
2227 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2229 if((err = register_netdev(netdev))) {
2230 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2234 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2235 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2236 pci_resource_start(pdev, 0), pdev->irq,
2237 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2238 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2247 pci_release_regions(pdev);
2248 err_out_disable_pdev:
2249 pci_disable_device(pdev);
2251 pci_set_drvdata(pdev, NULL);
2252 free_netdev(netdev);
2256 static void __devexit e100_remove(struct pci_dev *pdev)
2258 struct net_device *netdev = pci_get_drvdata(pdev);
2261 struct nic *nic = netdev->priv;
2262 unregister_netdev(netdev);
2265 free_netdev(netdev);
2266 pci_release_regions(pdev);
2267 pci_disable_device(pdev);
2268 pci_set_drvdata(pdev, NULL);
2273 static int e100_suspend(struct pci_dev *pdev, u32 state)
2275 struct net_device *netdev = pci_get_drvdata(pdev);
2276 struct nic *nic = netdev->priv;
2278 if(netif_running(netdev))
2281 netif_device_detach(netdev);
2283 pci_save_state(pdev, nic->pm_state);
2284 pci_enable_wake(pdev, state, nic->flags & (wol_magic | e100_asf(nic)));
2285 pci_disable_device(pdev);
2286 pci_set_power_state(pdev, state);
2291 static int e100_resume(struct pci_dev *pdev)
2293 struct net_device *netdev = pci_get_drvdata(pdev);
2294 struct nic *nic = netdev->priv;
2296 pci_set_power_state(pdev, 0);
2297 pci_restore_state(pdev, nic->pm_state);
2300 netif_device_attach(netdev);
2301 if(netif_running(netdev))
2308 static struct pci_driver e100_driver = {
2310 .id_table = e100_id_table,
2311 .probe = e100_probe,
2312 .remove = __devexit_p(e100_remove),
2314 .suspend = e100_suspend,
2315 .resume = e100_resume,
2319 static int __init e100_init_module(void)
2321 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2322 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2323 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2325 return pci_module_init(&e100_driver);
2328 static void __exit e100_cleanup_module(void)
2330 pci_unregister_driver(&e100_driver);
2333 module_init(e100_init_module);
2334 module_exit(e100_cleanup_module);