drivers/net/sb1250-mac.c

   1 /*
   2  * Copyright (C) 2001,2002,2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  *
  19  * This driver is designed for the Broadcom SiByte SOC built-in
  20  * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/string.h>
  25 #include <linux/timer.h>
  26 #include <linux/errno.h>
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/init.h>
  34 #include <linux/config.h>
  35 #include <linux/bitops.h>
  36 #include <asm/processor.h>              /* Processor type for cache alignment. */
  37 #include <asm/io.h>
  38 #include <asm/cache.h>
  39
  40 /* This is only here until the firmware is ready.  In that case,
  41    the firmware leaves the ethernet address in the register for us. */
  42 #ifdef CONFIG_SIBYTE_STANDALONE
  43 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  44 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  45 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  46 #endif
  47
  48
  49 /* These identify the driver base version and may not be removed. */
  50 #if 0
  51 static char version1[] __devinitdata =
  52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
  53 #endif
  54
  55
  56 /* Operational parameters that usually are not changed. */
  57
  58 #define CONFIG_SBMAC_COALESCE
  59
  60 #define MAX_UNITS 3             /* More are supported, limit only on options */
  61
  62 /* Time in jiffies before concluding the transmitter is hung. */
  63 #define TX_TIMEOUT  (2*HZ)
  64
  65
  66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  68
  69 /* A few user-configurable values which may be modified when a driver
  70    module is loaded. */
  71
  72 /* 1 normal messages, 0 quiet .. 7 verbose. */
  73 static int debug = 1;
  74 module_param(debug, int, S_IRUGO);
  75 MODULE_PARM_DESC(debug, "Debug messages");
  76
  77 /* mii status msgs */
  78 static int noisy_mii = 1;
  79 module_param(noisy_mii, int, S_IRUGO);
  80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
  81
  82 /* Used to pass the media type, etc.
  83    Both 'options[]' and 'full_duplex[]' should exist for driver
  84    interoperability.
  85    The media type is usually passed in 'options[]'.
  86 */
  87 #ifdef MODULE
  88 static int options[MAX_UNITS] = {-1, -1, -1};
  89 module_param_array(options, int, NULL, S_IRUGO);
  90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
  91
  92 static int full_duplex[MAX_UNITS] = {-1, -1, -1};
  93 module_param_array(full_duplex, int, NULL, S_IRUGO);
  94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
  95 #endif
  96
  97 #ifdef CONFIG_SBMAC_COALESCE
  98 static int int_pktcnt = 0;
  99 module_param(int_pktcnt, int, S_IRUGO);
 100 MODULE_PARM_DESC(int_pktcnt, "Packet count");
 101
 102 static int int_timeout = 0;
 103 module_param(int_timeout, int, S_IRUGO);
 104 MODULE_PARM_DESC(int_timeout, "Timeout value");
 105 #endif
 106
 107 #include <asm/sibyte/sb1250.h>
 108 #include <asm/sibyte/sb1250_defs.h>
 109 #include <asm/sibyte/sb1250_regs.h>
 110 #include <asm/sibyte/sb1250_mac.h>
 111 #include <asm/sibyte/sb1250_dma.h>
 112 #include <asm/sibyte/sb1250_int.h>
 113 #include <asm/sibyte/sb1250_scd.h>
 114
 115
 116 /**********************************************************************
 117  *  Simple types
 118  ********************************************************************* */
 119
 120
 121 typedef enum { sbmac_speed_auto, sbmac_speed_10,
 122                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
 123
 124 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
 125                sbmac_duplex_full } sbmac_duplex_t;
 126
 127 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
 128                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
 129
 130 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
 131                sbmac_state_broken } sbmac_state_t;
 132
 133
 134 /**********************************************************************
 135  *  Macros
 136  ********************************************************************* */
 137
 138
 139 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 140                           (d)->sbdma_dscrtable : (d)->f+1)
 141
 142
 143 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
 144
 145 #define SBMAC_MAX_TXDESCR       32
 146 #define SBMAC_MAX_RXDESCR       32
 147
 148 #define ETHER_ALIGN     2
 149 #define ETHER_ADDR_LEN  6
 150 #define ENET_PACKET_SIZE        1518
 151 /*#define ENET_PACKET_SIZE      9216 */
 152
 153 /**********************************************************************
 154  *  DMA Descriptor structure
 155  ********************************************************************* */
 156
 157 typedef struct sbdmadscr_s {
 158         uint64_t  dscr_a;
 159         uint64_t  dscr_b;
 160 } sbdmadscr_t;
 161
 162 typedef unsigned long paddr_t;
 163
 164 /**********************************************************************
 165  *  DMA Controller structure
 166  ********************************************************************* */
 167
 168 typedef struct sbmacdma_s {
 169
 170         /*
 171          * This stuff is used to identify the channel and the registers
 172          * associated with it.
 173          */
 174
 175         struct sbmac_softc *sbdma_eth;          /* back pointer to associated MAC */
 176         int              sbdma_channel; /* channel number */
 177         int              sbdma_txdir;       /* direction (1=transmit) */
 178         int              sbdma_maxdescr;        /* total # of descriptors in ring */
 179 #ifdef CONFIG_SBMAC_COALESCE
 180         int              sbdma_int_pktcnt;  /* # descriptors rx/tx before interrupt*/
 181         int              sbdma_int_timeout; /* # usec rx/tx interrupt */
 182 #endif
 183
 184         volatile void __iomem *sbdma_config0;   /* DMA config register 0 */
 185         volatile void __iomem *sbdma_config1;   /* DMA config register 1 */
 186         volatile void __iomem *sbdma_dscrbase;  /* Descriptor base address */
 187         volatile void __iomem *sbdma_dscrcnt;     /* Descriptor count register */
 188         volatile void __iomem *sbdma_curdscr;   /* current descriptor address */
 189
 190         /*
 191          * This stuff is for maintenance of the ring
 192          */
 193
 194         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
 195         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
 196
 197         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
 198
 199         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
 200         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
 201         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
 202 } sbmacdma_t;
 203
 204
 205 /**********************************************************************
 206  *  Ethernet softc structure
 207  ********************************************************************* */
 208
 209 struct sbmac_softc {
 210
 211         /*
 212          * Linux-specific things
 213          */
 214
 215         struct net_device *sbm_dev;             /* pointer to linux device */
 216         spinlock_t sbm_lock;            /* spin lock */
 217         struct timer_list sbm_timer;            /* for monitoring MII */
 218         struct net_device_stats sbm_stats;
 219         int sbm_devflags;                       /* current device flags */
 220
 221         int          sbm_phy_oldbmsr;
 222         int          sbm_phy_oldanlpar;
 223         int          sbm_phy_oldk1stsr;
 224         int          sbm_phy_oldlinkstat;
 225         int sbm_buffersize;
 226
 227         unsigned char sbm_phys[2];
 228
 229         /*
 230          * Controller-specific things
 231          */
 232
 233         volatile void __iomem *sbm_base;          /* MAC's base address */
 234         sbmac_state_t    sbm_state;         /* current state */
 235
 236         volatile void __iomem   *sbm_macenable; /* MAC Enable Register */
 237         volatile void __iomem   *sbm_maccfg;    /* MAC Configuration Register */
 238         volatile void __iomem   *sbm_fifocfg;   /* FIFO configuration register */
 239         volatile void __iomem   *sbm_framecfg;  /* Frame configuration register */
 240         volatile void __iomem   *sbm_rxfilter;  /* receive filter register */
 241         volatile void __iomem   *sbm_isr;       /* Interrupt status register */
 242         volatile void __iomem   *sbm_imr;       /* Interrupt mask register */
 243         volatile void __iomem   *sbm_mdio;      /* MDIO register */
 244
 245         sbmac_speed_t    sbm_speed;             /* current speed */
 246         sbmac_duplex_t   sbm_duplex;    /* current duplex */
 247         sbmac_fc_t       sbm_fc;                /* current flow control setting */
 248
 249         unsigned char    sbm_hwaddr[ETHER_ADDR_LEN];
 250
 251         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
 252         sbmacdma_t       sbm_rxdma;
 253         int              rx_hw_checksum;
 254         int              sbe_idx;
 255 };
 256
 257
 258 /**********************************************************************
 259  *  Externs
 260  ********************************************************************* */
 261
 262 /**********************************************************************
 263  *  Prototypes
 264  ********************************************************************* */
 265
 266 static void sbdma_initctx(sbmacdma_t *d,
 267                           struct sbmac_softc *s,
 268                           int chan,
 269                           int txrx,
 270                           int maxdescr);
 271 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
 272 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
 273 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
 274 static void sbdma_emptyring(sbmacdma_t *d);
 275 static void sbdma_fillring(sbmacdma_t *d);
 276 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 277 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 278 static int sbmac_initctx(struct sbmac_softc *s);
 279 static void sbmac_channel_start(struct sbmac_softc *s);
 280 static void sbmac_channel_stop(struct sbmac_softc *s);
 281 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
 282 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
 283 static uint64_t sbmac_addr2reg(unsigned char *ptr);
 284 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
 285 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 286 static void sbmac_setmulti(struct sbmac_softc *sc);
 287 static int sbmac_init(struct net_device *dev, int idx);
 288 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
 289 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
 290
 291 static int sbmac_open(struct net_device *dev);
 292 static void sbmac_timer(unsigned long data);
 293 static void sbmac_tx_timeout (struct net_device *dev);
 294 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
 295 static void sbmac_set_rx_mode(struct net_device *dev);
 296 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 297 static int sbmac_close(struct net_device *dev);
 298 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
 299 static int sbmac_mii_probe(struct net_device *dev);
 300
 301 static void sbmac_mii_sync(struct sbmac_softc *s);
 302 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
 303 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
 304 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 305                             unsigned int regval);
 306
 307
 308 /**********************************************************************
 309  *  Globals
 310  ********************************************************************* */
 311
 312 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
 313
 314
 315 /**********************************************************************
 316  *  MDIO constants
 317  ********************************************************************* */
 318
 319 #define MII_COMMAND_START       0x01
 320 #define MII_COMMAND_READ        0x02
 321 #define MII_COMMAND_WRITE       0x01
 322 #define MII_COMMAND_ACK         0x02
 323
 324 #define BMCR_RESET     0x8000
 325 #define BMCR_LOOPBACK  0x4000
 326 #define BMCR_SPEED0    0x2000
 327 #define BMCR_ANENABLE  0x1000
 328 #define BMCR_POWERDOWN 0x0800
 329 #define BMCR_ISOLATE   0x0400
 330 #define BMCR_RESTARTAN 0x0200
 331 #define BMCR_DUPLEX    0x0100
 332 #define BMCR_COLTEST   0x0080
 333 #define BMCR_SPEED1    0x0040
 334 #define BMCR_SPEED1000  BMCR_SPEED1
 335 #define BMCR_SPEED100   BMCR_SPEED0
 336 #define BMCR_SPEED10    0
 337
 338 #define BMSR_100BT4     0x8000
 339 #define BMSR_100BT_FDX  0x4000
 340 #define BMSR_100BT_HDX  0x2000
 341 #define BMSR_10BT_FDX   0x1000
 342 #define BMSR_10BT_HDX   0x0800
 343 #define BMSR_100BT2_FDX 0x0400
 344 #define BMSR_100BT2_HDX 0x0200
 345 #define BMSR_1000BT_XSR 0x0100
 346 #define BMSR_PRESUP     0x0040
 347 #define BMSR_ANCOMPLT   0x0020
 348 #define BMSR_REMFAULT   0x0010
 349 #define BMSR_AUTONEG    0x0008
 350 #define BMSR_LINKSTAT   0x0004
 351 #define BMSR_JABDETECT  0x0002
 352 #define BMSR_EXTCAPAB   0x0001
 353
 354 #define PHYIDR1         0x2000
 355 #define PHYIDR2         0x5C60
 356
 357 #define ANAR_NP         0x8000
 358 #define ANAR_RF         0x2000
 359 #define ANAR_ASYPAUSE   0x0800
 360 #define ANAR_PAUSE      0x0400
 361 #define ANAR_T4         0x0200
 362 #define ANAR_TXFD       0x0100
 363 #define ANAR_TXHD       0x0080
 364 #define ANAR_10FD       0x0040
 365 #define ANAR_10HD       0x0020
 366 #define ANAR_PSB        0x0001
 367
 368 #define ANLPAR_NP       0x8000
 369 #define ANLPAR_ACK      0x4000
 370 #define ANLPAR_RF       0x2000
 371 #define ANLPAR_ASYPAUSE 0x0800
 372 #define ANLPAR_PAUSE    0x0400
 373 #define ANLPAR_T4       0x0200
 374 #define ANLPAR_TXFD     0x0100
 375 #define ANLPAR_TXHD     0x0080
 376 #define ANLPAR_10FD     0x0040
 377 #define ANLPAR_10HD     0x0020
 378 #define ANLPAR_PSB      0x0001  /* 802.3 */
 379
 380 #define ANER_PDF        0x0010
 381 #define ANER_LPNPABLE   0x0008
 382 #define ANER_NPABLE     0x0004
 383 #define ANER_PAGERX     0x0002
 384 #define ANER_LPANABLE   0x0001
 385
 386 #define ANNPTR_NP       0x8000
 387 #define ANNPTR_MP       0x2000
 388 #define ANNPTR_ACK2     0x1000
 389 #define ANNPTR_TOGTX    0x0800
 390 #define ANNPTR_CODE     0x0008
 391
 392 #define ANNPRR_NP       0x8000
 393 #define ANNPRR_MP       0x2000
 394 #define ANNPRR_ACK3     0x1000
 395 #define ANNPRR_TOGTX    0x0800
 396 #define ANNPRR_CODE     0x0008
 397
 398 #define K1TCR_TESTMODE  0x0000
 399 #define K1TCR_MSMCE     0x1000
 400 #define K1TCR_MSCV      0x0800
 401 #define K1TCR_RPTR      0x0400
 402 #define K1TCR_1000BT_FDX 0x200
 403 #define K1TCR_1000BT_HDX 0x100
 404
 405 #define K1STSR_MSMCFLT  0x8000
 406 #define K1STSR_MSCFGRES 0x4000
 407 #define K1STSR_LRSTAT   0x2000
 408 #define K1STSR_RRSTAT   0x1000
 409 #define K1STSR_LP1KFD   0x0800
 410 #define K1STSR_LP1KHD   0x0400
 411 #define K1STSR_LPASMDIR 0x0200
 412
 413 #define K1SCR_1KX_FDX   0x8000
 414 #define K1SCR_1KX_HDX   0x4000
 415 #define K1SCR_1KT_FDX   0x2000
 416 #define K1SCR_1KT_HDX   0x1000
 417
 418 #define STRAP_PHY1      0x0800
 419 #define STRAP_NCMODE    0x0400
 420 #define STRAP_MANMSCFG  0x0200
 421 #define STRAP_ANENABLE  0x0100
 422 #define STRAP_MSVAL     0x0080
 423 #define STRAP_1KHDXADV  0x0010
 424 #define STRAP_1KFDXADV  0x0008
 425 #define STRAP_100ADV    0x0004
 426 #define STRAP_SPEEDSEL  0x0000
 427 #define STRAP_SPEED100  0x0001
 428
 429 #define PHYSUP_SPEED1000 0x10
 430 #define PHYSUP_SPEED100  0x08
 431 #define PHYSUP_SPEED10   0x00
 432 #define PHYSUP_LINKUP    0x04
 433 #define PHYSUP_FDX       0x02
 434
 435 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
 436 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
 437 #define MII_PHYIDR1     0x02
 438 #define MII_PHYIDR2     0x03
 439
 440 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
 441 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 442
 443
 444 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 445
 446 #define ENABLE          1
 447 #define DISABLE         0
 448
 449 /**********************************************************************
 450  *  SBMAC_MII_SYNC(s)
 451  *
 452  *  Synchronize with the MII - send a pattern of bits to the MII
 453  *  that will guarantee that it is ready to accept a command.
 454  *
 455  *  Input parameters:
 456  *         s - sbmac structure
 457  *
 458  *  Return value:
 459  *         nothing
 460  ********************************************************************* */
 461
 462 static void sbmac_mii_sync(struct sbmac_softc *s)
 463 {
 464         int cnt;
 465         uint64_t bits;
 466         int mac_mdio_genc;
 467
 468         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 469
 470         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 471
 472         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 473
 474         for (cnt = 0; cnt < 32; cnt++) {
 475                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 476                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 477         }
 478 }
 479
 480 /**********************************************************************
 481  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
 482  *
 483  *  Send some bits to the MII.  The bits to be sent are right-
 484  *  justified in the 'data' parameter.
 485  *
 486  *  Input parameters:
 487  *         s - sbmac structure
 488  *         data - data to send
 489  *         bitcnt - number of bits to send
 490  ********************************************************************* */
 491
 492 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
 493 {
 494         int i;
 495         uint64_t bits;
 496         unsigned int curmask;
 497         int mac_mdio_genc;
 498
 499         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 500
 501         bits = M_MAC_MDIO_DIR_OUTPUT;
 502         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 503
 504         curmask = 1 << (bitcnt - 1);
 505
 506         for (i = 0; i < bitcnt; i++) {
 507                 if (data & curmask)
 508                         bits |= M_MAC_MDIO_OUT;
 509                 else bits &= ~M_MAC_MDIO_OUT;
 510                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 511                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 512                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 513                 curmask >>= 1;
 514         }
 515 }
 516
 517
 518
 519 /**********************************************************************
 520  *  SBMAC_MII_READ(s,phyaddr,regidx)
 521  *
 522  *  Read a PHY register.
 523  *
 524  *  Input parameters:
 525  *         s - sbmac structure
 526  *         phyaddr - PHY's address
 527  *         regidx = index of register to read
 528  *
 529  *  Return value:
 530  *         value read, or 0 if an error occurred.
 531  ********************************************************************* */
 532
 533 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
 534 {
 535         int idx;
 536         int error;
 537         int regval;
 538         int mac_mdio_genc;
 539
 540         /*
 541          * Synchronize ourselves so that the PHY knows the next
 542          * thing coming down is a command
 543          */
 544
 545         sbmac_mii_sync(s);
 546
 547         /*
 548          * Send the data to the PHY.  The sequence is
 549          * a "start" command (2 bits)
 550          * a "read" command (2 bits)
 551          * the PHY addr (5 bits)
 552          * the register index (5 bits)
 553          */
 554
 555         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
 556         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
 557         sbmac_mii_senddata(s,phyaddr, 5);
 558         sbmac_mii_senddata(s,regidx, 5);
 559
 560         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 561
 562         /*
 563          * Switch the port around without a clock transition.
 564          */
 565         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 566
 567         /*
 568          * Send out a clock pulse to signal we want the status
 569          */
 570
 571         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 572         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 573
 574         /*
 575          * If an error occurred, the PHY will signal '1' back
 576          */
 577         error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
 578
 579         /*
 580          * Issue an 'idle' clock pulse, but keep the direction
 581          * the same.
 582          */
 583         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 584         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 585
 586         regval = 0;
 587
 588         for (idx = 0; idx < 16; idx++) {
 589                 regval <<= 1;
 590
 591                 if (error == 0) {
 592                         if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
 593                                 regval |= 1;
 594                 }
 595
 596                 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 597                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 598         }
 599
 600         /* Switch back to output */
 601         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
 602
 603         if (error == 0)
 604                 return regval;
 605         return 0;
 606 }
 607
 608
 609 /**********************************************************************
 610  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
 611  *
 612  *  Write a value to a PHY register.
 613  *
 614  *  Input parameters:
 615  *         s - sbmac structure
 616  *         phyaddr - PHY to use
 617  *         regidx - register within the PHY
 618  *         regval - data to write to register
 619  *
 620  *  Return value:
 621  *         nothing
 622  ********************************************************************* */
 623
 624 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 625                             unsigned int regval)
 626 {
 627         int mac_mdio_genc;
 628
 629         sbmac_mii_sync(s);
 630
 631         sbmac_mii_senddata(s,MII_COMMAND_START,2);
 632         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
 633         sbmac_mii_senddata(s,phyaddr, 5);
 634         sbmac_mii_senddata(s,regidx, 5);
 635         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
 636         sbmac_mii_senddata(s,regval,16);
 637
 638         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 639
 640         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
 641 }
 642
 643
 644
 645 /**********************************************************************
 646  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 647  *
 648  *  Initialize a DMA channel context.  Since there are potentially
 649  *  eight DMA channels per MAC, it's nice to do this in a standard
 650  *  way.
 651  *
 652  *  Input parameters:
 653  *         d - sbmacdma_t structure (DMA channel context)
 654  *         s - sbmac_softc structure (pointer to a MAC)
 655  *         chan - channel number (0..1 right now)
 656  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 657  *      maxdescr - number of descriptors
 658  *
 659  *  Return value:
 660  *         nothing
 661  ********************************************************************* */
 662
 663 static void sbdma_initctx(sbmacdma_t *d,
 664                           struct sbmac_softc *s,
 665                           int chan,
 666                           int txrx,
 667                           int maxdescr)
 668 {
 669         /*
 670          * Save away interesting stuff in the structure
 671          */
 672
 673         d->sbdma_eth       = s;
 674         d->sbdma_channel   = chan;
 675         d->sbdma_txdir     = txrx;
 676
 677 #if 0
 678         /* RMON clearing */
 679         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 680 #endif
 681
 682         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
 683         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
 684         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
 685         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
 686         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
 687         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
 688         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
 689         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
 690         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
 691         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
 692         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
 693         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
 694         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
 695         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
 696         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
 697         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
 698         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
 699         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
 700         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
 701         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
 702         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
 703
 704         /*
 705          * initialize register pointers
 706          */
 707
 708         d->sbdma_config0 =
 709                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
 710         d->sbdma_config1 =
 711                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
 712         d->sbdma_dscrbase =
 713                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
 714         d->sbdma_dscrcnt =
 715                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
 716         d->sbdma_curdscr =
 717                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
 718
 719         /*
 720          * Allocate memory for the ring
 721          */
 722
 723         d->sbdma_maxdescr = maxdescr;
 724
 725         d->sbdma_dscrtable = (sbdmadscr_t *)
 726                 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
 727
 728         /*
 729          * The descriptor table must be aligned to at least 16 bytes or the
 730          * MAC will corrupt it.
 731          */
 732         d->sbdma_dscrtable = (sbdmadscr_t *)
 733                 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
 734
 735         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 736
 737         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 738
 739         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
 740
 741         /*
 742          * And context table
 743          */
 744
 745         d->sbdma_ctxtable = (struct sk_buff **)
 746                 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
 747
 748         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
 749
 750 #ifdef CONFIG_SBMAC_COALESCE
 751         /*
 752          * Setup Rx/Tx DMA coalescing defaults
 753          */
 754
 755         if ( int_pktcnt ) {
 756                 d->sbdma_int_pktcnt = int_pktcnt;
 757         } else {
 758                 d->sbdma_int_pktcnt = 1;
 759         }
 760
 761         if ( int_timeout ) {
 762                 d->sbdma_int_timeout = int_timeout;
 763         } else {
 764                 d->sbdma_int_timeout = 0;
 765         }
 766 #endif
 767
 768 }
 769
 770 /**********************************************************************
 771  *  SBDMA_CHANNEL_START(d)
 772  *
 773  *  Initialize the hardware registers for a DMA channel.
 774  *
 775  *  Input parameters:
 776  *         d - DMA channel to init (context must be previously init'd
 777  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 778  *
 779  *  Return value:
 780  *         nothing
 781  ********************************************************************* */
 782
 783 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
 784 {
 785         /*
 786          * Turn on the DMA channel
 787          */
 788
 789 #ifdef CONFIG_SBMAC_COALESCE
 790         __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 791                        0, d->sbdma_config1);
 792         __raw_writeq(M_DMA_EOP_INT_EN |
 793                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 794                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 795                        0, d->sbdma_config0);
 796 #else
 797         __raw_writeq(0, d->sbdma_config1);
 798         __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
 799                        0, d->sbdma_config0);
 800 #endif
 801
 802         __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
 803
 804         /*
 805          * Initialize ring pointers
 806          */
 807
 808         d->sbdma_addptr = d->sbdma_dscrtable;
 809         d->sbdma_remptr = d->sbdma_dscrtable;
 810 }
 811
 812 /**********************************************************************
 813  *  SBDMA_CHANNEL_STOP(d)
 814  *
 815  *  Initialize the hardware registers for a DMA channel.
 816  *
 817  *  Input parameters:
 818  *         d - DMA channel to init (context must be previously init'd
 819  *
 820  *  Return value:
 821  *         nothing
 822  ********************************************************************* */
 823
 824 static void sbdma_channel_stop(sbmacdma_t *d)
 825 {
 826         /*
 827          * Turn off the DMA channel
 828          */
 829
 830         __raw_writeq(0, d->sbdma_config1);
 831
 832         __raw_writeq(0, d->sbdma_dscrbase);
 833
 834         __raw_writeq(0, d->sbdma_config0);
 835
 836         /*
 837          * Zero ring pointers
 838          */
 839
 840         d->sbdma_addptr = NULL;
 841         d->sbdma_remptr = NULL;
 842 }
 843
 844 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
 845 {
 846         unsigned long addr;
 847         unsigned long newaddr;
 848
 849         addr = (unsigned long) skb->data;
 850
 851         newaddr = (addr + power2 - 1) & ~(power2 - 1);
 852
 853         skb_reserve(skb,newaddr-addr+offset);
 854 }
 855
 856
 857 /**********************************************************************
 858  *  SBDMA_ADD_RCVBUFFER(d,sb)
 859  *
 860  *  Add a buffer to the specified DMA channel.   For receive channels,
 861  *  this queues a buffer for inbound packets.
 862  *
 863  *  Input parameters:
 864  *         d - DMA channel descriptor
 865  *         sb - sk_buff to add, or NULL if we should allocate one
 866  *
 867  *  Return value:
 868  *         0 if buffer could not be added (ring is full)
 869  *         1 if buffer added successfully
 870  ********************************************************************* */
 871
 872
 873 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
 874 {
 875         sbdmadscr_t *dsc;
 876         sbdmadscr_t *nextdsc;
 877         struct sk_buff *sb_new = NULL;
 878         int pktsize = ENET_PACKET_SIZE;
 879
 880         /* get pointer to our current place in the ring */
 881
 882         dsc = d->sbdma_addptr;
 883         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 884
 885         /*
 886          * figure out if the ring is full - if the next descriptor
 887          * is the same as the one that we're going to remove from
 888          * the ring, the ring is full
 889          */
 890
 891         if (nextdsc == d->sbdma_remptr) {
 892                 return -ENOSPC;
 893         }
 894
 895         /*
 896          * Allocate a sk_buff if we don't already have one.
 897          * If we do have an sk_buff, reset it so that it's empty.
 898          *
 899          * Note: sk_buffs don't seem to be guaranteed to have any sort
 900          * of alignment when they are allocated.  Therefore, allocate enough
 901          * extra space to make sure that:
 902          *
 903          *    1. the data does not start in the middle of a cache line.
 904          *    2. The data does not end in the middle of a cache line
 905          *    3. The buffer can be aligned such that the IP addresses are
 906          *       naturally aligned.
 907          *
 908          *  Remember, the SOCs MAC writes whole cache lines at a time,
 909          *  without reading the old contents first.  So, if the sk_buff's
 910          *  data portion starts in the middle of a cache line, the SOC
 911          *  DMA will trash the beginning (and ending) portions.
 912          */
 913
 914         if (sb == NULL) {
 915                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
 916                 if (sb_new == NULL) {
 917                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
 918                                d->sbdma_eth->sbm_dev->name);
 919                         return -ENOBUFS;
 920                 }
 921
 922                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
 923
 924                 /* mark skbuff owned by our device */
 925                 sb_new->dev = d->sbdma_eth->sbm_dev;
 926         }
 927         else {
 928                 sb_new = sb;
 929                 /*
 930                  * nothing special to reinit buffer, it's already aligned
 931                  * and sb->data already points to a good place.
 932                  */
 933         }
 934
 935         /*
 936          * fill in the descriptor
 937          */
 938
 939 #ifdef CONFIG_SBMAC_COALESCE
 940         /*
 941          * Do not interrupt per DMA transfer.
 942          */
 943         dsc->dscr_a = virt_to_phys(sb_new->data) |
 944                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
 945 #else
 946         dsc->dscr_a = virt_to_phys(sb_new->data) |
 947                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 948                 M_DMA_DSCRA_INTERRUPT;
 949 #endif
 950
 951         /* receiving: no options */
 952         dsc->dscr_b = 0;
 953
 954         /*
 955          * fill in the context
 956          */
 957
 958         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 959
 960         /*
 961          * point at next packet
 962          */
 963
 964         d->sbdma_addptr = nextdsc;
 965
 966         /*
 967          * Give the buffer to the DMA engine.
 968          */
 969
 970         __raw_writeq(1, d->sbdma_dscrcnt);
 971
 972         return 0;                                       /* we did it */
 973 }
 974
 975 /**********************************************************************
 976  *  SBDMA_ADD_TXBUFFER(d,sb)
 977  *
 978  *  Add a transmit buffer to the specified DMA channel, causing a
 979  *  transmit to start.
 980  *
 981  *  Input parameters:
 982  *         d - DMA channel descriptor
 983  *         sb - sk_buff to add
 984  *
 985  *  Return value:
 986  *         0 transmit queued successfully
 987  *         otherwise error code
 988  ********************************************************************* */
 989
 990
 991 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
 992 {
 993         sbdmadscr_t *dsc;
 994         sbdmadscr_t *nextdsc;
 995         uint64_t phys;
 996         uint64_t ncb;
 997         int length;
 998
 999         /* get pointer to our current place in the ring */
1000
1001         dsc = d->sbdma_addptr;
1002         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1003
1004         /*
1005          * figure out if the ring is full - if the next descriptor
1006          * is the same as the one that we're going to remove from
1007          * the ring, the ring is full
1008          */
1009
1010         if (nextdsc == d->sbdma_remptr) {
1011                 return -ENOSPC;
1012         }
1013
1014         /*
1015          * Under Linux, it's not necessary to copy/coalesce buffers
1016          * like it is on NetBSD.  We think they're all contiguous,
1017          * but that may not be true for GBE.
1018          */
1019
1020         length = sb->len;
1021
1022         /*
1023          * fill in the descriptor.  Note that the number of cache
1024          * blocks in the descriptor is the number of blocks
1025          * *spanned*, so we need to add in the offset (if any)
1026          * while doing the calculation.
1027          */
1028
1029         phys = virt_to_phys(sb->data);
1030         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1031
1032         dsc->dscr_a = phys |
1033                 V_DMA_DSCRA_A_SIZE(ncb) |
1034 #ifndef CONFIG_SBMAC_COALESCE
1035                 M_DMA_DSCRA_INTERRUPT |
1036 #endif
1037                 M_DMA_ETHTX_SOP;
1038
1039         /* transmitting: set outbound options and length */
1040
1041         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1042                 V_DMA_DSCRB_PKT_SIZE(length);
1043
1044         /*
1045          * fill in the context
1046          */
1047
1048         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1049
1050         /*
1051          * point at next packet
1052          */
1053
1054         d->sbdma_addptr = nextdsc;
1055
1056         /*
1057          * Give the buffer to the DMA engine.
1058          */
1059
1060         __raw_writeq(1, d->sbdma_dscrcnt);
1061
1062         return 0;                                       /* we did it */
1063 }
1064
1065
1066
1067
1068 /**********************************************************************
1069  *  SBDMA_EMPTYRING(d)
1070  *
1071  *  Free all allocated sk_buffs on the specified DMA channel;
1072  *
1073  *  Input parameters:
1074  *         d  - DMA channel
1075  *
1076  *  Return value:
1077  *         nothing
1078  ********************************************************************* */
1079
1080 static void sbdma_emptyring(sbmacdma_t *d)
1081 {
1082         int idx;
1083         struct sk_buff *sb;
1084
1085         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1086                 sb = d->sbdma_ctxtable[idx];
1087                 if (sb) {
1088                         dev_kfree_skb(sb);
1089                         d->sbdma_ctxtable[idx] = NULL;
1090                 }
1091         }
1092 }
1093
1094
1095 /**********************************************************************
1096  *  SBDMA_FILLRING(d)
1097  *
1098  *  Fill the specified DMA channel (must be receive channel)
1099  *  with sk_buffs
1100  *
1101  *  Input parameters:
1102  *         d - DMA channel
1103  *
1104  *  Return value:
1105  *         nothing
1106  ********************************************************************* */
1107
1108 static void sbdma_fillring(sbmacdma_t *d)
1109 {
1110         int idx;
1111
1112         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1113                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1114                         break;
1115         }
1116 }
1117
1118
1119 /**********************************************************************
1120  *  SBDMA_RX_PROCESS(sc,d)
1121  *
1122  *  Process "completed" receive buffers on the specified DMA channel.
1123  *  Note that this isn't really ideal for priority channels, since
1124  *  it processes all of the packets on a given channel before
1125  *  returning.
1126  *
1127  *  Input parameters:
1128  *         sc - softc structure
1129  *         d - DMA channel context
1130  *
1131  *  Return value:
1132  *         nothing
1133  ********************************************************************* */
1134
1135 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1136 {
1137         int curidx;
1138         int hwidx;
1139         sbdmadscr_t *dsc;
1140         struct sk_buff *sb;
1141         int len;
1142
1143         for (;;) {
1144                 /*
1145                  * figure out where we are (as an index) and where
1146                  * the hardware is (also as an index)
1147                  *
1148                  * This could be done faster if (for example) the
1149                  * descriptor table was page-aligned and contiguous in
1150                  * both virtual and physical memory -- you could then
1151                  * just compare the low-order bits of the virtual address
1152                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1153                  */
1154
1155                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1156                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1157                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1158
1159                 /*
1160                  * If they're the same, that means we've processed all
1161                  * of the descriptors up to (but not including) the one that
1162                  * the hardware is working on right now.
1163                  */
1164
1165                 if (curidx == hwidx)
1166                         break;
1167
1168                 /*
1169                  * Otherwise, get the packet's sk_buff ptr back
1170                  */
1171
1172                 dsc = &(d->sbdma_dscrtable[curidx]);
1173                 sb = d->sbdma_ctxtable[curidx];
1174                 d->sbdma_ctxtable[curidx] = NULL;
1175
1176                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1177
1178                 /*
1179                  * Check packet status.  If good, process it.
1180                  * If not, silently drop it and put it back on the
1181                  * receive ring.
1182                  */
1183
1184                 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1185
1186                         /*
1187                          * Add a new buffer to replace the old one.  If we fail
1188                          * to allocate a buffer, we're going to drop this
1189                          * packet and put it right back on the receive ring.
1190                          */
1191
1192                         if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1193                                 sc->sbm_stats.rx_dropped++;
1194                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1195                         } else {
1196                                 /*
1197                                  * Set length into the packet
1198                                  */
1199                                 skb_put(sb,len);
1200
1201                                 /*
1202                                  * Buffer has been replaced on the
1203                                  * receive ring.  Pass the buffer to
1204                                  * the kernel
1205                                  */
1206                                 sc->sbm_stats.rx_bytes += len;
1207                                 sc->sbm_stats.rx_packets++;
1208                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1209                                 /* Check hw IPv4/TCP checksum if supported */
1210                                 if (sc->rx_hw_checksum == ENABLE) {
1211                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1212                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1213                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1214                                                 /* don't need to set sb->csum */
1215                                         } else {
1216                                                 sb->ip_summed = CHECKSUM_NONE;
1217                                         }
1218                                 }
1219
1220                                 netif_rx(sb);
1221                         }
1222                 } else {
1223                         /*
1224                          * Packet was mangled somehow.  Just drop it and
1225                          * put it back on the receive ring.
1226                          */
1227                         sc->sbm_stats.rx_errors++;
1228                         sbdma_add_rcvbuffer(d,sb);
1229                 }
1230
1231
1232                 /*
1233                  * .. and advance to the next buffer.
1234                  */
1235
1236                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1237
1238         }
1239 }
1240
1241
1242
1243 /**********************************************************************
1244  *  SBDMA_TX_PROCESS(sc,d)
1245  *
1246  *  Process "completed" transmit buffers on the specified DMA channel.
1247  *  This is normally called within the interrupt service routine.
1248  *  Note that this isn't really ideal for priority channels, since
1249  *  it processes all of the packets on a given channel before
1250  *  returning.
1251  *
1252  *  Input parameters:
1253  *      sc - softc structure
1254  *         d - DMA channel context
1255  *
1256  *  Return value:
1257  *         nothing
1258  ********************************************************************* */
1259
1260 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1261 {
1262         int curidx;
1263         int hwidx;
1264         sbdmadscr_t *dsc;
1265         struct sk_buff *sb;
1266         unsigned long flags;
1267
1268         spin_lock_irqsave(&(sc->sbm_lock), flags);
1269
1270         for (;;) {
1271                 /*
1272                  * figure out where we are (as an index) and where
1273                  * the hardware is (also as an index)
1274                  *
1275                  * This could be done faster if (for example) the
1276                  * descriptor table was page-aligned and contiguous in
1277                  * both virtual and physical memory -- you could then
1278                  * just compare the low-order bits of the virtual address
1279                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1280                  */
1281
1282                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1283                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1284                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1285
1286                 /*
1287                  * If they're the same, that means we've processed all
1288                  * of the descriptors up to (but not including) the one that
1289                  * the hardware is working on right now.
1290                  */
1291
1292                 if (curidx == hwidx)
1293                         break;
1294
1295                 /*
1296                  * Otherwise, get the packet's sk_buff ptr back
1297                  */
1298
1299                 dsc = &(d->sbdma_dscrtable[curidx]);
1300                 sb = d->sbdma_ctxtable[curidx];
1301                 d->sbdma_ctxtable[curidx] = NULL;
1302
1303                 /*
1304                  * Stats
1305                  */
1306
1307                 sc->sbm_stats.tx_bytes += sb->len;
1308                 sc->sbm_stats.tx_packets++;
1309
1310                 /*
1311                  * for transmits, we just free buffers.
1312                  */
1313
1314                 dev_kfree_skb_irq(sb);
1315
1316                 /*
1317                  * .. and advance to the next buffer.
1318                  */
1319
1320                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1321
1322         }
1323
1324         /*
1325          * Decide if we should wake up the protocol or not.
1326          * Other drivers seem to do this when we reach a low
1327          * watermark on the transmit queue.
1328          */
1329
1330         netif_wake_queue(d->sbdma_eth->sbm_dev);
1331
1332         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1333
1334 }
1335
1336
1337
1338 /**********************************************************************
1339  *  SBMAC_INITCTX(s)
1340  *
1341  *  Initialize an Ethernet context structure - this is called
1342  *  once per MAC on the 1250.  Memory is allocated here, so don't
1343  *  call it again from inside the ioctl routines that bring the
1344  *  interface up/down
1345  *
1346  *  Input parameters:
1347  *         s - sbmac context structure
1348  *
1349  *  Return value:
1350  *         0
1351  ********************************************************************* */
1352
1353 static int sbmac_initctx(struct sbmac_softc *s)
1354 {
1355
1356         /*
1357          * figure out the addresses of some ports
1358          */
1359
1360         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1361         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1362         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1363         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1364         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1365         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1366         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1367         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1368
1369         s->sbm_phys[0]   = 1;
1370         s->sbm_phys[1]   = 0;
1371
1372         s->sbm_phy_oldbmsr = 0;
1373         s->sbm_phy_oldanlpar = 0;
1374         s->sbm_phy_oldk1stsr = 0;
1375         s->sbm_phy_oldlinkstat = 0;
1376
1377         /*
1378          * Initialize the DMA channels.  Right now, only one per MAC is used
1379          * Note: Only do this _once_, as it allocates memory from the kernel!
1380          */
1381
1382         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1383         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1384
1385         /*
1386          * initial state is OFF
1387          */
1388
1389         s->sbm_state = sbmac_state_off;
1390
1391         /*
1392          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1393          */
1394
1395         s->sbm_speed = sbmac_speed_10;
1396         s->sbm_duplex = sbmac_duplex_half;
1397         s->sbm_fc = sbmac_fc_disabled;
1398
1399         return 0;
1400 }
1401
1402
1403 static void sbdma_uninitctx(struct sbmacdma_s *d)
1404 {
1405         if (d->sbdma_dscrtable) {
1406                 kfree(d->sbdma_dscrtable);
1407                 d->sbdma_dscrtable = NULL;
1408         }
1409
1410         if (d->sbdma_ctxtable) {
1411                 kfree(d->sbdma_ctxtable);
1412                 d->sbdma_ctxtable = NULL;
1413         }
1414 }
1415
1416
1417 static void sbmac_uninitctx(struct sbmac_softc *sc)
1418 {
1419         sbdma_uninitctx(&(sc->sbm_txdma));
1420         sbdma_uninitctx(&(sc->sbm_rxdma));
1421 }
1422
1423
1424 /**********************************************************************
1425  *  SBMAC_CHANNEL_START(s)
1426  *
1427  *  Start packet processing on this MAC.
1428  *
1429  *  Input parameters:
1430  *         s - sbmac structure
1431  *
1432  *  Return value:
1433  *         nothing
1434  ********************************************************************* */
1435
1436 static void sbmac_channel_start(struct sbmac_softc *s)
1437 {
1438         uint64_t reg;
1439         volatile void __iomem *port;
1440         uint64_t cfg,fifo,framecfg;
1441         int idx, th_value;
1442
1443         /*
1444          * Don't do this if running
1445          */
1446
1447         if (s->sbm_state == sbmac_state_on)
1448                 return;
1449
1450         /*
1451          * Bring the controller out of reset, but leave it off.
1452          */
1453
1454         __raw_writeq(0, s->sbm_macenable);
1455
1456         /*
1457          * Ignore all received packets
1458          */
1459
1460         __raw_writeq(0, s->sbm_rxfilter);
1461
1462         /*
1463          * Calculate values for various control registers.
1464          */
1465
1466         cfg = M_MAC_RETRY_EN |
1467                 M_MAC_TX_HOLD_SOP_EN |
1468                 V_MAC_TX_PAUSE_CNT_16K |
1469                 M_MAC_AP_STAT_EN |
1470                 M_MAC_FAST_SYNC |
1471                 M_MAC_SS_EN |
1472                 0;
1473
1474         /*
1475          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1476          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1477          * Use a larger RD_THRSH for gigabit
1478          */
1479         if (periph_rev >= 2)
1480                 th_value = 64;
1481         else
1482                 th_value = 28;
1483
1484         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1485                 ((s->sbm_speed == sbmac_speed_1000)
1486                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1487                 V_MAC_TX_RL_THRSH(4) |
1488                 V_MAC_RX_PL_THRSH(4) |
1489                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1490                 V_MAC_RX_PL_THRSH(4) |
1491                 V_MAC_RX_RL_THRSH(8) |
1492                 0;
1493
1494         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1495                 V_MAC_MAX_FRAMESZ_DEFAULT |
1496                 V_MAC_BACKOFF_SEL(1);
1497
1498         /*
1499          * Clear out the hash address map
1500          */
1501
1502         port = s->sbm_base + R_MAC_HASH_BASE;
1503         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1504                 __raw_writeq(0, port);
1505                 port += sizeof(uint64_t);
1506         }
1507
1508         /*
1509          * Clear out the exact-match table
1510          */
1511
1512         port = s->sbm_base + R_MAC_ADDR_BASE;
1513         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1514                 __raw_writeq(0, port);
1515                 port += sizeof(uint64_t);
1516         }
1517
1518         /*
1519          * Clear out the DMA Channel mapping table registers
1520          */
1521
1522         port = s->sbm_base + R_MAC_CHUP0_BASE;
1523         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1524                 __raw_writeq(0, port);
1525                 port += sizeof(uint64_t);
1526         }
1527
1528
1529         port = s->sbm_base + R_MAC_CHLO0_BASE;
1530         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1531                 __raw_writeq(0, port);
1532                 port += sizeof(uint64_t);
1533         }
1534
1535         /*
1536          * Program the hardware address.  It goes into the hardware-address
1537          * register as well as the first filter register.
1538          */
1539
1540         reg = sbmac_addr2reg(s->sbm_hwaddr);
1541
1542         port = s->sbm_base + R_MAC_ADDR_BASE;
1543         __raw_writeq(reg, port);
1544         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1545
1546 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1547         /*
1548          * Pass1 SOCs do not receive packets addressed to the
1549          * destination address in the R_MAC_ETHERNET_ADDR register.
1550          * Set the value to zero.
1551          */
1552         __raw_writeq(0, port);
1553 #else
1554         __raw_writeq(reg, port);
1555 #endif
1556
1557         /*
1558          * Set the receive filter for no packets, and write values
1559          * to the various config registers
1560          */
1561
1562         __raw_writeq(0, s->sbm_rxfilter);
1563         __raw_writeq(0, s->sbm_imr);
1564         __raw_writeq(framecfg, s->sbm_framecfg);
1565         __raw_writeq(fifo, s->sbm_fifocfg);
1566         __raw_writeq(cfg, s->sbm_maccfg);
1567
1568         /*
1569          * Initialize DMA channels (rings should be ok now)
1570          */
1571
1572         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1573         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1574
1575         /*
1576          * Configure the speed, duplex, and flow control
1577          */
1578
1579         sbmac_set_speed(s,s->sbm_speed);
1580         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1581
1582         /*
1583          * Fill the receive ring
1584          */
1585
1586         sbdma_fillring(&(s->sbm_rxdma));
1587
1588         /*
1589          * Turn on the rest of the bits in the enable register
1590          */
1591
1592         __raw_writeq(M_MAC_RXDMA_EN0 |
1593                        M_MAC_TXDMA_EN0 |
1594                        M_MAC_RX_ENABLE |
1595                        M_MAC_TX_ENABLE, s->sbm_macenable);
1596
1597
1598
1599
1600 #ifdef CONFIG_SBMAC_COALESCE
1601         /*
1602          * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1603          */
1604         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1605                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1606 #else
1607         /*
1608          * Accept any kind of interrupt on TX and RX DMA channel 0
1609          */
1610         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1611                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1612 #endif
1613
1614         /*
1615          * Enable receiving unicasts and broadcasts
1616          */
1617
1618         __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1619
1620         /*
1621          * we're running now.
1622          */
1623
1624         s->sbm_state = sbmac_state_on;
1625
1626         /*
1627          * Program multicast addresses
1628          */
1629
1630         sbmac_setmulti(s);
1631
1632         /*
1633          * If channel was in promiscuous mode before, turn that on
1634          */
1635
1636         if (s->sbm_devflags & IFF_PROMISC) {
1637                 sbmac_promiscuous_mode(s,1);
1638         }
1639
1640 }
1641
1642
1643 /**********************************************************************
1644  *  SBMAC_CHANNEL_STOP(s)
1645  *
1646  *  Stop packet processing on this MAC.
1647  *
1648  *  Input parameters:
1649  *         s - sbmac structure
1650  *
1651  *  Return value:
1652  *         nothing
1653  ********************************************************************* */
1654
1655 static void sbmac_channel_stop(struct sbmac_softc *s)
1656 {
1657         /* don't do this if already stopped */
1658
1659         if (s->sbm_state == sbmac_state_off)
1660                 return;
1661
1662         /* don't accept any packets, disable all interrupts */
1663
1664         __raw_writeq(0, s->sbm_rxfilter);
1665         __raw_writeq(0, s->sbm_imr);
1666
1667         /* Turn off ticker */
1668
1669         /* XXX */
1670
1671         /* turn off receiver and transmitter */
1672
1673         __raw_writeq(0, s->sbm_macenable);
1674
1675         /* We're stopped now. */
1676
1677         s->sbm_state = sbmac_state_off;
1678
1679         /*
1680          * Stop DMA channels (rings should be ok now)
1681          */
1682
1683         sbdma_channel_stop(&(s->sbm_rxdma));
1684         sbdma_channel_stop(&(s->sbm_txdma));
1685
1686         /* Empty the receive and transmit rings */
1687
1688         sbdma_emptyring(&(s->sbm_rxdma));
1689         sbdma_emptyring(&(s->sbm_txdma));
1690
1691 }
1692
1693 /**********************************************************************
1694  *  SBMAC_SET_CHANNEL_STATE(state)
1695  *
1696  *  Set the channel's state ON or OFF
1697  *
1698  *  Input parameters:
1699  *         state - new state
1700  *
1701  *  Return value:
1702  *         old state
1703  ********************************************************************* */
1704 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1705                                              sbmac_state_t state)
1706 {
1707         sbmac_state_t oldstate = sc->sbm_state;
1708
1709         /*
1710          * If same as previous state, return
1711          */
1712
1713         if (state == oldstate) {
1714                 return oldstate;
1715         }
1716
1717         /*
1718          * If new state is ON, turn channel on
1719          */
1720
1721         if (state == sbmac_state_on) {
1722                 sbmac_channel_start(sc);
1723         }
1724         else {
1725                 sbmac_channel_stop(sc);
1726         }
1727
1728         /*
1729          * Return previous state
1730          */
1731
1732         return oldstate;
1733 }
1734
1735
1736 /**********************************************************************
1737  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1738  *
1739  *  Turn on or off promiscuous mode
1740  *
1741  *  Input parameters:
1742  *         sc - softc
1743  *      onoff - 1 to turn on, 0 to turn off
1744  *
1745  *  Return value:
1746  *         nothing
1747  ********************************************************************* */
1748
1749 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1750 {
1751         uint64_t reg;
1752
1753         if (sc->sbm_state != sbmac_state_on)
1754                 return;
1755
1756         if (onoff) {
1757                 reg = __raw_readq(sc->sbm_rxfilter);
1758                 reg |= M_MAC_ALLPKT_EN;
1759                 __raw_writeq(reg, sc->sbm_rxfilter);
1760         }
1761         else {
1762                 reg = __raw_readq(sc->sbm_rxfilter);
1763                 reg &= ~M_MAC_ALLPKT_EN;
1764                 __raw_writeq(reg, sc->sbm_rxfilter);
1765         }
1766 }
1767
1768 /**********************************************************************
1769  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1770  *
1771  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1772  *
1773  *  Input parameters:
1774  *         sc - softc
1775  *
1776  *  Return value:
1777  *         nothing
1778  ********************************************************************* */
1779
1780 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1781 {
1782         uint64_t reg;
1783
1784         /* Hard code the off set to 15 for now */
1785         reg = __raw_readq(sc->sbm_rxfilter);
1786         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1787         __raw_writeq(reg, sc->sbm_rxfilter);
1788
1789         /* read system identification to determine revision */
1790         if (periph_rev >= 2) {
1791                 sc->rx_hw_checksum = ENABLE;
1792         } else {
1793                 sc->rx_hw_checksum = DISABLE;
1794         }
1795 }
1796
1797
1798 /**********************************************************************
1799  *  SBMAC_ADDR2REG(ptr)
1800  *
1801  *  Convert six bytes into the 64-bit register value that
1802  *  we typically write into the SBMAC's address/mcast registers
1803  *
1804  *  Input parameters:
1805  *         ptr - pointer to 6 bytes
1806  *
1807  *  Return value:
1808  *         register value
1809  ********************************************************************* */
1810
1811 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1812 {
1813         uint64_t reg = 0;
1814
1815         ptr += 6;
1816
1817         reg |= (uint64_t) *(--ptr);
1818         reg <<= 8;
1819         reg |= (uint64_t) *(--ptr);
1820         reg <<= 8;
1821         reg |= (uint64_t) *(--ptr);
1822         reg <<= 8;
1823         reg |= (uint64_t) *(--ptr);
1824         reg <<= 8;
1825         reg |= (uint64_t) *(--ptr);
1826         reg <<= 8;
1827         reg |= (uint64_t) *(--ptr);
1828
1829         return reg;
1830 }
1831
1832
1833 /**********************************************************************
1834  *  SBMAC_SET_SPEED(s,speed)
1835  *
1836  *  Configure LAN speed for the specified MAC.
1837  *  Warning: must be called when MAC is off!
1838  *
1839  *  Input parameters:
1840  *         s - sbmac structure
1841  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1842  *
1843  *  Return value:
1844  *         1 if successful
1845  *      0 indicates invalid parameters
1846  ********************************************************************* */
1847
1848 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1849 {
1850         uint64_t cfg;
1851         uint64_t framecfg;
1852
1853         /*
1854          * Save new current values
1855          */
1856
1857         s->sbm_speed = speed;
1858
1859         if (s->sbm_state == sbmac_state_on)
1860                 return 0;       /* save for next restart */
1861
1862         /*
1863          * Read current register values
1864          */
1865
1866         cfg = __raw_readq(s->sbm_maccfg);
1867         framecfg = __raw_readq(s->sbm_framecfg);
1868
1869         /*
1870          * Mask out the stuff we want to change
1871          */
1872
1873         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1874         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1875                       M_MAC_SLOT_SIZE);
1876
1877         /*
1878          * Now add in the new bits
1879          */
1880
1881         switch (speed) {
1882         case sbmac_speed_10:
1883                 framecfg |= V_MAC_IFG_RX_10 |
1884                         V_MAC_IFG_TX_10 |
1885                         K_MAC_IFG_THRSH_10 |
1886                         V_MAC_SLOT_SIZE_10;
1887                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1888                 break;
1889
1890         case sbmac_speed_100:
1891                 framecfg |= V_MAC_IFG_RX_100 |
1892                         V_MAC_IFG_TX_100 |
1893                         V_MAC_IFG_THRSH_100 |
1894                         V_MAC_SLOT_SIZE_100;
1895                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1896                 break;
1897
1898         case sbmac_speed_1000:
1899                 framecfg |= V_MAC_IFG_RX_1000 |
1900                         V_MAC_IFG_TX_1000 |
1901                         V_MAC_IFG_THRSH_1000 |
1902                         V_MAC_SLOT_SIZE_1000;
1903                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1904                 break;
1905
1906         case sbmac_speed_auto:          /* XXX not implemented */
1907                 /* fall through */
1908         default:
1909                 return 0;
1910         }
1911
1912         /*
1913          * Send the bits back to the hardware
1914          */
1915
1916         __raw_writeq(framecfg, s->sbm_framecfg);
1917         __raw_writeq(cfg, s->sbm_maccfg);
1918
1919         return 1;
1920 }
1921
1922 /**********************************************************************
1923  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1924  *
1925  *  Set Ethernet duplex and flow control options for this MAC
1926  *  Warning: must be called when MAC is off!
1927  *
1928  *  Input parameters:
1929  *         s - sbmac structure
1930  *         duplex - duplex setting (see sbmac_duplex_t)
1931  *         fc - flow control setting (see sbmac_fc_t)
1932  *
1933  *  Return value:
1934  *         1 if ok
1935  *         0 if an invalid parameter combination was specified
1936  ********************************************************************* */
1937
1938 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1939 {
1940         uint64_t cfg;
1941
1942         /*
1943          * Save new current values
1944          */
1945
1946         s->sbm_duplex = duplex;
1947         s->sbm_fc = fc;
1948
1949         if (s->sbm_state == sbmac_state_on)
1950                 return 0;       /* save for next restart */
1951
1952         /*
1953          * Read current register values
1954          */
1955
1956         cfg = __raw_readq(s->sbm_maccfg);
1957
1958         /*
1959          * Mask off the stuff we're about to change
1960          */
1961
1962         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1963
1964
1965         switch (duplex) {
1966         case sbmac_duplex_half:
1967                 switch (fc) {
1968                 case sbmac_fc_disabled:
1969                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1970                         break;
1971
1972                 case sbmac_fc_collision:
1973                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1974                         break;
1975
1976                 case sbmac_fc_carrier:
1977                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1978                         break;
1979
1980                 case sbmac_fc_auto:             /* XXX not implemented */
1981                         /* fall through */
1982                 case sbmac_fc_frame:            /* not valid in half duplex */
1983                 default:                        /* invalid selection */
1984                         return 0;
1985                 }
1986                 break;
1987
1988         case sbmac_duplex_full:
1989                 switch (fc) {
1990                 case sbmac_fc_disabled:
1991                         cfg |= V_MAC_FC_CMD_DISABLED;
1992                         break;
1993
1994                 case sbmac_fc_frame:
1995                         cfg |= V_MAC_FC_CMD_ENABLED;
1996                         break;
1997
1998                 case sbmac_fc_collision:        /* not valid in full duplex */
1999                 case sbmac_fc_carrier:          /* not valid in full duplex */
2000                 case sbmac_fc_auto:             /* XXX not implemented */
2001                         /* fall through */
2002                 default:
2003                         return 0;
2004                 }
2005                 break;
2006         case sbmac_duplex_auto:
2007                 /* XXX not implemented */
2008                 break;
2009         }
2010
2011         /*
2012          * Send the bits back to the hardware
2013          */
2014
2015         __raw_writeq(cfg, s->sbm_maccfg);
2016
2017         return 1;
2018 }
2019
2020
2021
2022
2023 /**********************************************************************
2024  *  SBMAC_INTR()
2025  *
2026  *  Interrupt handler for MAC interrupts
2027  *
2028  *  Input parameters:
2029  *         MAC structure
2030  *
2031  *  Return value:
2032  *         nothing
2033  ********************************************************************* */
2034 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2035 {
2036         struct net_device *dev = (struct net_device *) dev_instance;
2037         struct sbmac_softc *sc = netdev_priv(dev);
2038         uint64_t isr;
2039         int handled = 0;
2040
2041         for (;;) {
2042
2043                 /*
2044                  * Read the ISR (this clears the bits in the real
2045                  * register, except for counter addr)
2046                  */
2047
2048                 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2049
2050                 if (isr == 0)
2051                         break;
2052
2053                 handled = 1;
2054
2055                 /*
2056                  * Transmits on channel 0
2057                  */
2058
2059                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2060                         sbdma_tx_process(sc,&(sc->sbm_txdma));
2061                 }
2062
2063                 /*
2064                  * Receives on channel 0
2065                  */
2066
2067                 /*
2068                  * It's important to test all the bits (or at least the
2069                  * EOP_SEEN bit) when deciding to do the RX process
2070                  * particularly when coalescing, to make sure we
2071                  * take care of the following:
2072                  *
2073                  * If you have some packets waiting (have been received
2074                  * but no interrupt) and get a TX interrupt before
2075                  * the RX timer or counter expires, reading the ISR
2076                  * above will clear the timer and counter, and you
2077                  * won't get another interrupt until a packet shows
2078                  * up to start the timer again.  Testing
2079                  * EOP_SEEN here takes care of this case.
2080                  * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2081                  */
2082
2083
2084                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2085                         sbdma_rx_process(sc,&(sc->sbm_rxdma));
2086                 }
2087         }
2088         return IRQ_RETVAL(handled);
2089 }
2090
2091
2092 /**********************************************************************
2093  *  SBMAC_START_TX(skb,dev)
2094  *
2095  *  Start output on the specified interface.  Basically, we
2096  *  queue as many buffers as we can until the ring fills up, or
2097  *  we run off the end of the queue, whichever comes first.
2098  *
2099  *  Input parameters:
2100  *
2101  *
2102  *  Return value:
2103  *         nothing
2104  ********************************************************************* */
2105 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2106 {
2107         struct sbmac_softc *sc = netdev_priv(dev);
2108
2109         /* lock eth irq */
2110         spin_lock_irq (&sc->sbm_lock);
2111
2112         /*
2113          * Put the buffer on the transmit ring.  If we
2114          * don't have room, stop the queue.
2115          */
2116
2117         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2118                 /* XXX save skb that we could not send */
2119                 netif_stop_queue(dev);
2120                 spin_unlock_irq(&sc->sbm_lock);
2121
2122                 return 1;
2123         }
2124
2125         dev->trans_start = jiffies;
2126
2127         spin_unlock_irq (&sc->sbm_lock);
2128
2129         return 0;
2130 }
2131
2132 /**********************************************************************
2133  *  SBMAC_SETMULTI(sc)
2134  *
2135  *  Reprogram the multicast table into the hardware, given
2136  *  the list of multicasts associated with the interface
2137  *  structure.
2138  *
2139  *  Input parameters:
2140  *         sc - softc
2141  *
2142  *  Return value:
2143  *         nothing
2144  ********************************************************************* */
2145
2146 static void sbmac_setmulti(struct sbmac_softc *sc)
2147 {
2148         uint64_t reg;
2149         volatile void __iomem *port;
2150         int idx;
2151         struct dev_mc_list *mclist;
2152         struct net_device *dev = sc->sbm_dev;
2153
2154         /*
2155          * Clear out entire multicast table.  We do this by nuking
2156          * the entire hash table and all the direct matches except
2157          * the first one, which is used for our station address
2158          */
2159
2160         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2161                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2162                 __raw_writeq(0, port);
2163         }
2164
2165         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2166                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2167                 __raw_writeq(0, port);
2168         }
2169
2170         /*
2171          * Clear the filter to say we don't want any multicasts.
2172          */
2173
2174         reg = __raw_readq(sc->sbm_rxfilter);
2175         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2176         __raw_writeq(reg, sc->sbm_rxfilter);
2177
2178         if (dev->flags & IFF_ALLMULTI) {
2179                 /*
2180                  * Enable ALL multicasts.  Do this by inverting the
2181                  * multicast enable bit.
2182                  */
2183                 reg = __raw_readq(sc->sbm_rxfilter);
2184                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2185                 __raw_writeq(reg, sc->sbm_rxfilter);
2186                 return;
2187         }
2188
2189
2190         /*
2191          * Progam new multicast entries.  For now, only use the
2192          * perfect filter.  In the future we'll need to use the
2193          * hash filter if the perfect filter overflows
2194          */
2195
2196         /* XXX only using perfect filter for now, need to use hash
2197          * XXX if the table overflows */
2198
2199         idx = 1;                /* skip station address */
2200         mclist = dev->mc_list;
2201         while (mclist && (idx < MAC_ADDR_COUNT)) {
2202                 reg = sbmac_addr2reg(mclist->dmi_addr);
2203                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2204                 __raw_writeq(reg, port);
2205                 idx++;
2206                 mclist = mclist->next;
2207         }
2208
2209         /*
2210          * Enable the "accept multicast bits" if we programmed at least one
2211          * multicast.
2212          */
2213
2214         if (idx > 1) {
2215                 reg = __raw_readq(sc->sbm_rxfilter);
2216                 reg |= M_MAC_MCAST_EN;
2217                 __raw_writeq(reg, sc->sbm_rxfilter);
2218         }
2219 }
2220
2221
2222
2223 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2224 /**********************************************************************
2225  *  SBMAC_PARSE_XDIGIT(str)
2226  *
2227  *  Parse a hex digit, returning its value
2228  *
2229  *  Input parameters:
2230  *         str - character
2231  *
2232  *  Return value:
2233  *         hex value, or -1 if invalid
2234  ********************************************************************* */
2235
2236 static int sbmac_parse_xdigit(char str)
2237 {
2238         int digit;
2239
2240         if ((str >= '0') && (str <= '9'))
2241                 digit = str - '0';
2242         else if ((str >= 'a') && (str <= 'f'))
2243                 digit = str - 'a' + 10;
2244         else if ((str >= 'A') && (str <= 'F'))
2245                 digit = str - 'A' + 10;
2246         else
2247                 return -1;
2248
2249         return digit;
2250 }
2251
2252 /**********************************************************************
2253  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2254  *
2255  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2256  *  Ethernet address.
2257  *
2258  *  Input parameters:
2259  *         str - string
2260  *         hwaddr - pointer to hardware address
2261  *
2262  *  Return value:
2263  *         0 if ok, else -1
2264  ********************************************************************* */
2265
2266 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2267 {
2268         int digit1,digit2;
2269         int idx = 6;
2270
2271         while (*str && (idx > 0)) {
2272                 digit1 = sbmac_parse_xdigit(*str);
2273                 if (digit1 < 0)
2274                         return -1;
2275                 str++;
2276                 if (!*str)
2277                         return -1;
2278
2279                 if ((*str == ':') || (*str == '-')) {
2280                         digit2 = digit1;
2281                         digit1 = 0;
2282                 }
2283                 else {
2284                         digit2 = sbmac_parse_xdigit(*str);
2285                         if (digit2 < 0)
2286                                 return -1;
2287                         str++;
2288                 }
2289
2290                 *hwaddr++ = (digit1 << 4) | digit2;
2291                 idx--;
2292
2293                 if (*str == '-')
2294                         str++;
2295                 if (*str == ':')
2296                         str++;
2297         }
2298         return 0;
2299 }
2300 #endif
2301
2302 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2303 {
2304         if (new_mtu >  ENET_PACKET_SIZE)
2305                 return -EINVAL;
2306         _dev->mtu = new_mtu;
2307         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2308         return 0;
2309 }
2310
2311 /**********************************************************************
2312  *  SBMAC_INIT(dev)
2313  *
2314  *  Attach routine - init hardware and hook ourselves into linux
2315  *
2316  *  Input parameters:
2317  *         dev - net_device structure
2318  *
2319  *  Return value:
2320  *         status
2321  ********************************************************************* */
2322
2323 static int sbmac_init(struct net_device *dev, int idx)
2324 {
2325         struct sbmac_softc *sc;
2326         unsigned char *eaddr;
2327         uint64_t ea_reg;
2328         int i;
2329         int err;
2330
2331         sc = netdev_priv(dev);
2332
2333         /* Determine controller base address */
2334
2335         sc->sbm_base = IOADDR(dev->base_addr);
2336         sc->sbm_dev = dev;
2337         sc->sbe_idx = idx;
2338
2339         eaddr = sc->sbm_hwaddr;
2340
2341         /*
2342          * Read the ethernet address.  The firwmare left this programmed
2343          * for us in the ethernet address register for each mac.
2344          */
2345
2346         ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2347         __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2348         for (i = 0; i < 6; i++) {
2349                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2350                 ea_reg >>= 8;
2351         }
2352
2353         for (i = 0; i < 6; i++) {
2354                 dev->dev_addr[i] = eaddr[i];
2355         }
2356
2357
2358         /*
2359          * Init packet size
2360          */
2361
2362         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2363
2364         /*
2365          * Initialize context (get pointers to registers and stuff), then
2366          * allocate the memory for the descriptor tables.
2367          */
2368
2369         sbmac_initctx(sc);
2370
2371         /*
2372          * Set up Linux device callins
2373          */
2374
2375         spin_lock_init(&(sc->sbm_lock));
2376
2377         dev->open               = sbmac_open;
2378         dev->hard_start_xmit    = sbmac_start_tx;
2379         dev->stop               = sbmac_close;
2380         dev->get_stats          = sbmac_get_stats;
2381         dev->set_multicast_list = sbmac_set_rx_mode;
2382         dev->do_ioctl           = sbmac_mii_ioctl;
2383         dev->tx_timeout         = sbmac_tx_timeout;
2384         dev->watchdog_timeo     = TX_TIMEOUT;
2385
2386         dev->change_mtu         = sb1250_change_mtu;
2387
2388         /* This is needed for PASS2 for Rx H/W checksum feature */
2389         sbmac_set_iphdr_offset(sc);
2390
2391         err = register_netdev(dev);
2392         if (err)
2393                 goto out_uninit;
2394
2395         if (sc->rx_hw_checksum == ENABLE) {
2396                 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2397                         sc->sbm_dev->name);
2398         }
2399
2400         /*
2401          * Display Ethernet address (this is called during the config
2402          * process so we need to finish off the config message that
2403          * was being displayed)
2404          */
2405         printk(KERN_INFO
2406                "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2407                dev->name, dev->base_addr,
2408                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2409
2410
2411         return 0;
2412
2413 out_uninit:
2414         sbmac_uninitctx(sc);
2415
2416         return err;
2417 }
2418
2419
2420 static int sbmac_open(struct net_device *dev)
2421 {
2422         struct sbmac_softc *sc = netdev_priv(dev);
2423
2424         if (debug > 1) {
2425                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2426         }
2427
2428         /*
2429          * map/route interrupt (clear status first, in case something
2430          * weird is pending; we haven't initialized the mac registers
2431          * yet)
2432          */
2433
2434         __raw_readq(sc->sbm_isr);
2435         if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
2436                 return -EBUSY;
2437
2438         /*
2439          * Probe phy address
2440          */
2441
2442         if(sbmac_mii_probe(dev) == -1) {
2443                 printk("%s: failed to probe PHY.\n", dev->name);
2444                 return -EINVAL;
2445         }
2446
2447         /*
2448          * Configure default speed
2449          */
2450
2451         sbmac_mii_poll(sc,noisy_mii);
2452
2453         /*
2454          * Turn on the channel
2455          */
2456
2457         sbmac_set_channel_state(sc,sbmac_state_on);
2458
2459         /*
2460          * XXX Station address is in dev->dev_addr
2461          */
2462
2463         if (dev->if_port == 0)
2464                 dev->if_port = 0;
2465
2466         netif_start_queue(dev);
2467
2468         sbmac_set_rx_mode(dev);
2469
2470         /* Set the timer to check for link beat. */
2471         init_timer(&sc->sbm_timer);
2472         sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2473         sc->sbm_timer.data = (unsigned long)dev;
2474         sc->sbm_timer.function = &sbmac_timer;
2475         add_timer(&sc->sbm_timer);
2476
2477         return 0;
2478 }
2479
2480 static int sbmac_mii_probe(struct net_device *dev)
2481 {
2482         int i;
2483         struct sbmac_softc *s = netdev_priv(dev);
2484         u16 bmsr, id1, id2;
2485         u32 vendor, device;
2486
2487         for (i=1; i<31; i++) {
2488         bmsr = sbmac_mii_read(s, i, MII_BMSR);
2489                 if (bmsr != 0) {
2490                         s->sbm_phys[0] = i;
2491                         id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2492                         id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2493                         vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2494                         device = (id2 >> 4) & 0x3f;
2495
2496                         printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2497                                 dev->name, i, vendor, device);
2498                         return i;
2499                 }
2500         }
2501         return -1;
2502 }
2503
2504
2505 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2506 {
2507     int bmsr,bmcr,k1stsr,anlpar;
2508     int chg;
2509     char buffer[100];
2510     char *p = buffer;
2511
2512     /* Read the mode status and mode control registers. */
2513     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2514     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2515
2516     /* get the link partner status */
2517     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2518
2519     /* if supported, read the 1000baseT register */
2520     if (bmsr & BMSR_1000BT_XSR) {
2521         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2522         }
2523     else {
2524         k1stsr = 0;
2525         }
2526
2527     chg = 0;
2528
2529     if ((bmsr & BMSR_LINKSTAT) == 0) {
2530         /*
2531          * If link status is down, clear out old info so that when
2532          * it comes back up it will force us to reconfigure speed
2533          */
2534         s->sbm_phy_oldbmsr = 0;
2535         s->sbm_phy_oldanlpar = 0;
2536         s->sbm_phy_oldk1stsr = 0;
2537         return 0;
2538         }
2539
2540     if ((s->sbm_phy_oldbmsr != bmsr) ||
2541         (s->sbm_phy_oldanlpar != anlpar) ||
2542         (s->sbm_phy_oldk1stsr != k1stsr)) {
2543         if (debug > 1) {
2544             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2545                s->sbm_dev->name,
2546                s->sbm_phy_oldbmsr,bmsr,
2547                s->sbm_phy_oldanlpar,anlpar,
2548                s->sbm_phy_oldk1stsr,k1stsr);
2549             }
2550         s->sbm_phy_oldbmsr = bmsr;
2551         s->sbm_phy_oldanlpar = anlpar;
2552         s->sbm_phy_oldk1stsr = k1stsr;
2553         chg = 1;
2554         }
2555
2556     if (chg == 0)
2557             return 0;
2558
2559     p += sprintf(p,"Link speed: ");
2560
2561     if (k1stsr & K1STSR_LP1KFD) {
2562         s->sbm_speed = sbmac_speed_1000;
2563         s->sbm_duplex = sbmac_duplex_full;
2564         s->sbm_fc = sbmac_fc_frame;
2565         p += sprintf(p,"1000BaseT FDX");
2566         }
2567     else if (k1stsr & K1STSR_LP1KHD) {
2568         s->sbm_speed = sbmac_speed_1000;
2569         s->sbm_duplex = sbmac_duplex_half;
2570         s->sbm_fc = sbmac_fc_disabled;
2571         p += sprintf(p,"1000BaseT HDX");
2572         }
2573     else if (anlpar & ANLPAR_TXFD) {
2574         s->sbm_speed = sbmac_speed_100;
2575         s->sbm_duplex = sbmac_duplex_full;
2576         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2577         p += sprintf(p,"100BaseT FDX");
2578         }
2579     else if (anlpar & ANLPAR_TXHD) {
2580         s->sbm_speed = sbmac_speed_100;
2581         s->sbm_duplex = sbmac_duplex_half;
2582         s->sbm_fc = sbmac_fc_disabled;
2583         p += sprintf(p,"100BaseT HDX");
2584         }
2585     else if (anlpar & ANLPAR_10FD) {
2586         s->sbm_speed = sbmac_speed_10;
2587         s->sbm_duplex = sbmac_duplex_full;
2588         s->sbm_fc = sbmac_fc_frame;
2589         p += sprintf(p,"10BaseT FDX");
2590         }
2591     else if (anlpar & ANLPAR_10HD) {
2592         s->sbm_speed = sbmac_speed_10;
2593         s->sbm_duplex = sbmac_duplex_half;
2594         s->sbm_fc = sbmac_fc_collision;
2595         p += sprintf(p,"10BaseT HDX");
2596         }
2597     else {
2598         p += sprintf(p,"Unknown");
2599         }
2600
2601     if (noisy) {
2602             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2603             }
2604
2605     return 1;
2606 }
2607
2608
2609 static void sbmac_timer(unsigned long data)
2610 {
2611         struct net_device *dev = (struct net_device *)data;
2612         struct sbmac_softc *sc = netdev_priv(dev);
2613         int next_tick = HZ;
2614         int mii_status;
2615
2616         spin_lock_irq (&sc->sbm_lock);
2617
2618         /* make IFF_RUNNING follow the MII status bit "Link established" */
2619         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2620
2621         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2622                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2623                 if (mii_status & BMSR_LINKSTAT) {
2624                         netif_carrier_on(dev);
2625                 }
2626                 else {
2627                         netif_carrier_off(dev);
2628                 }
2629         }
2630
2631         /*
2632          * Poll the PHY to see what speed we should be running at
2633          */
2634
2635         if (sbmac_mii_poll(sc,noisy_mii)) {
2636                 if (sc->sbm_state != sbmac_state_off) {
2637                         /*
2638                          * something changed, restart the channel
2639                          */
2640                         if (debug > 1) {
2641                                 printk("%s: restarting channel because speed changed\n",
2642                                        sc->sbm_dev->name);
2643                         }
2644                         sbmac_channel_stop(sc);
2645                         sbmac_channel_start(sc);
2646                 }
2647         }
2648
2649         spin_unlock_irq (&sc->sbm_lock);
2650
2651         sc->sbm_timer.expires = jiffies + next_tick;
2652         add_timer(&sc->sbm_timer);
2653 }
2654
2655
2656 static void sbmac_tx_timeout (struct net_device *dev)
2657 {
2658         struct sbmac_softc *sc = netdev_priv(dev);
2659
2660         spin_lock_irq (&sc->sbm_lock);
2661
2662
2663         dev->trans_start = jiffies;
2664         sc->sbm_stats.tx_errors++;
2665
2666         spin_unlock_irq (&sc->sbm_lock);
2667
2668         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2669 }
2670
2671
2672
2673
2674 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2675 {
2676         struct sbmac_softc *sc = netdev_priv(dev);
2677         unsigned long flags;
2678
2679         spin_lock_irqsave(&sc->sbm_lock, flags);
2680
2681         /* XXX update other stats here */
2682
2683         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2684
2685         return &sc->sbm_stats;
2686 }
2687
2688
2689
2690 static void sbmac_set_rx_mode(struct net_device *dev)
2691 {
2692         unsigned long flags;
2693         int msg_flag = 0;
2694         struct sbmac_softc *sc = netdev_priv(dev);
2695
2696         spin_lock_irqsave(&sc->sbm_lock, flags);
2697         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2698                 /*
2699                  * Promiscuous changed.
2700                  */
2701
2702                 if (dev->flags & IFF_PROMISC) {
2703                         /* Unconditionally log net taps. */
2704                         msg_flag = 1;
2705                         sbmac_promiscuous_mode(sc,1);
2706                 }
2707                 else {
2708                         msg_flag = 2;
2709                         sbmac_promiscuous_mode(sc,0);
2710                 }
2711         }
2712         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2713
2714         if (msg_flag) {
2715                 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2716                        dev->name,(msg_flag==1)?"en":"dis");
2717         }
2718
2719         /*
2720          * Program the multicasts.  Do this every time.
2721          */
2722
2723         sbmac_setmulti(sc);
2724
2725 }
2726
2727 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2728 {
2729         struct sbmac_softc *sc = netdev_priv(dev);
2730         u16 *data = (u16 *)&rq->ifr_ifru;
2731         unsigned long flags;
2732         int retval;
2733
2734         spin_lock_irqsave(&sc->sbm_lock, flags);
2735         retval = 0;
2736
2737         switch(cmd) {
2738         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2739                 data[0] = sc->sbm_phys[0] & 0x1f;
2740                 /* Fall Through */
2741         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2742                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2743                 break;
2744         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2745                 if (!capable(CAP_NET_ADMIN)) {
2746                         retval = -EPERM;
2747                         break;
2748                 }
2749                 if (debug > 1) {
2750                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2751                        data[0],data[1],data[2]);
2752                     }
2753                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2754                 break;
2755         default:
2756                 retval = -EOPNOTSUPP;
2757         }
2758
2759         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2760         return retval;
2761 }
2762
2763 static int sbmac_close(struct net_device *dev)
2764 {
2765         struct sbmac_softc *sc = netdev_priv(dev);
2766         unsigned long flags;
2767         int irq;
2768
2769         sbmac_set_channel_state(sc,sbmac_state_off);
2770
2771         del_timer_sync(&sc->sbm_timer);
2772
2773         spin_lock_irqsave(&sc->sbm_lock, flags);
2774
2775         netif_stop_queue(dev);
2776
2777         if (debug > 1) {
2778                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2779         }
2780
2781         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2782
2783         irq = dev->irq;
2784         synchronize_irq(irq);
2785         free_irq(irq, dev);
2786
2787         sbdma_emptyring(&(sc->sbm_txdma));
2788         sbdma_emptyring(&(sc->sbm_rxdma));
2789
2790         return 0;
2791 }
2792
2793
2794
2795 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2796 static void
2797 sbmac_setup_hwaddr(int chan,char *addr)
2798 {
2799         uint8_t eaddr[6];
2800         uint64_t val;
2801         unsigned long port;
2802
2803         port = A_MAC_CHANNEL_BASE(chan);
2804         sbmac_parse_hwaddr(addr,eaddr);
2805         val = sbmac_addr2reg(eaddr);
2806         __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2807         val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2808 }
2809 #endif
2810
2811 static struct net_device *dev_sbmac[MAX_UNITS];
2812
2813 static int __init
2814 sbmac_init_module(void)
2815 {
2816         int idx;
2817         struct net_device *dev;
2818         unsigned long port;
2819         int chip_max_units;
2820
2821         /*
2822          * For bringup when not using the firmware, we can pre-fill
2823          * the MAC addresses using the environment variables
2824          * specified in this file (or maybe from the config file?)
2825          */
2826 #ifdef SBMAC_ETH0_HWADDR
2827         sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2828 #endif
2829 #ifdef SBMAC_ETH1_HWADDR
2830         sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2831 #endif
2832 #ifdef SBMAC_ETH2_HWADDR
2833         sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2834 #endif
2835
2836         /*
2837          * Walk through the Ethernet controllers and find
2838          * those who have their MAC addresses set.
2839          */
2840         switch (soc_type) {
2841         case K_SYS_SOC_TYPE_BCM1250:
2842         case K_SYS_SOC_TYPE_BCM1250_ALT:
2843                 chip_max_units = 3;
2844                 break;
2845         case K_SYS_SOC_TYPE_BCM1120:
2846         case K_SYS_SOC_TYPE_BCM1125:
2847         case K_SYS_SOC_TYPE_BCM1125H:
2848         case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2849                 chip_max_units = 2;
2850                 break;
2851         default:
2852                 chip_max_units = 0;
2853                 break;
2854         }
2855         if (chip_max_units > MAX_UNITS)
2856                 chip_max_units = MAX_UNITS;
2857
2858         for (idx = 0; idx < chip_max_units; idx++) {
2859
2860                 /*
2861                  * This is the base address of the MAC.
2862                  */
2863
2864                 port = A_MAC_CHANNEL_BASE(idx);
2865
2866                 /*
2867                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2868                  * value for us by the firmware if we're going to use this MAC.
2869                  * If we find a zero, skip this MAC.
2870                  */
2871
2872                 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2873                 if (sbmac_orig_hwaddr[idx] == 0) {
2874                         printk(KERN_DEBUG "sbmac: not configuring MAC at "
2875                                "%lx\n", port);
2876                     continue;
2877                 }
2878
2879                 /*
2880                  * Okay, cool.  Initialize this MAC.
2881                  */
2882
2883                 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2884                 if (!dev)
2885                         return -ENOMEM; /* return ENOMEM */
2886
2887                 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2888
2889                 dev->irq = K_INT_MAC_0 + idx;
2890                 dev->base_addr = port;
2891                 dev->mem_end = 0;
2892                 if (sbmac_init(dev, idx)) {
2893                         port = A_MAC_CHANNEL_BASE(idx);
2894                         __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2895                         free_netdev(dev);
2896                         continue;
2897                 }
2898                 dev_sbmac[idx] = dev;
2899         }
2900         return 0;
2901 }
2902
2903
2904 static void __exit
2905 sbmac_cleanup_module(void)
2906 {
2907         struct net_device *dev;
2908         int idx;
2909
2910         for (idx = 0; idx < MAX_UNITS; idx++) {
2911                 struct sbmac_softc *sc;
2912                 dev = dev_sbmac[idx];
2913                 if (!dev)
2914                         continue;
2915
2916                 sc = netdev_priv(dev);
2917                 unregister_netdev(dev);
2918                 sbmac_uninitctx(sc);
2919                 free_netdev(dev);
2920         }
2921 }
2922
2923 module_init(sbmac_init_module);
2924 module_exit(sbmac_cleanup_module);