1 /******************************************************************************
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
6 * See the file "skfddi.c" for further information.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * The information in this file is provided "AS IS" without warranty.
15 ******************************************************************************/
19 Physical Connection Management
23 * Hardware independent state machine implemantation
24 * The following external SMT functions are referenced :
30 * The following external HW dependent functions are referenced :
35 * The following HW dependent events are required :
49 #include "h/supern_2.h"
51 #include "h/smtstate.h"
54 static const char ID_sccs[] = "@(#)pcmplc.c 2.55 99/08/05 (C) SK " ;
58 extern int snmp_fddi_trap(
60 struct s_smc * smc, int type, int index
65 extern int plc_is_installed(
76 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
77 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
78 #define ACTIONS(x) (x|AFLAG)
96 * symbolic state names
98 static const char * const pcm_states[] = {
99 "PC0_OFF","PC1_BREAK","PC2_TRACE","PC3_CONNECT","PC4_NEXT",
100 "PC5_SIGNAL","PC6_JOIN","PC7_VERIFY","PC8_ACTIVE","PC9_MAINT"
104 * symbolic event names
106 static const char * const pcm_events[] = {
107 "NONE","PC_START","PC_STOP","PC_LOOP","PC_JOIN","PC_SIGNAL",
108 "PC_REJECT","PC_MAINT","PC_TRACE","PC_PDR",
109 "PC_ENABLE","PC_DISABLE",
110 "PC_QLS","PC_ILS","PC_MLS","PC_HLS","PC_LS_PDR","PC_LS_NONE",
111 "PC_TIMEOUT_TB_MAX","PC_TIMEOUT_TB_MIN",
112 "PC_TIMEOUT_C_MIN","PC_TIMEOUT_T_OUT",
113 "PC_TIMEOUT_TL_MIN","PC_TIMEOUT_T_NEXT","PC_TIMEOUT_LCT",
120 * PCL-S control register
121 * this register in the PLC-S controls the scrambling parameters
123 #define PLCS_CONTROL_C_U 0
124 #define PLCS_CONTROL_C_S (PL_C_SDOFF_ENABLE | PL_C_SDON_ENABLE | \
126 #define PLCS_FASSERT_U 0
127 #define PLCS_FASSERT_S 0xFd76 /* 52.0 us */
128 #define PLCS_FDEASSERT_U 0
129 #define PLCS_FDEASSERT_S 0
132 * PCL-S control register
133 * this register in the PLC-S controls the scrambling parameters
134 * can be patched for ANSI compliance if standard changes
136 static const u_char plcs_control_c_u[17] = "PLC_CNTRL_C_U=\0\0" ;
137 static const u_char plcs_control_c_s[17] = "PLC_CNTRL_C_S=\01\02" ;
139 #define PLCS_CONTROL_C_U (plcs_control_c_u[14] | (plcs_control_c_u[15]<<8))
140 #define PLCS_CONTROL_C_S (plcs_control_c_s[14] | (plcs_control_c_s[15]<<8))
141 #endif /* nMOT_ELM */
146 /* struct definition see 'cmtdef.h' (also used by CFM) */
157 #define LCT_LEM_MAX 255
160 * PLC timing parameter
163 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
164 #define SLOW_TL_MIN PLC_MS(6)
165 #define SLOW_C_MIN PLC_MS(10)
167 static const struct plt {
168 int timer ; /* relative plc timer address */
169 int para ; /* default timing parameters */
171 { PL_C_MIN, SLOW_C_MIN }, /* min t. to remain Connect State */
172 { PL_TL_MIN, SLOW_TL_MIN }, /* min t. to transmit a Line State */
173 { PL_TB_MIN, TP_TB_MIN }, /* min break time */
174 { PL_T_OUT, TP_T_OUT }, /* Signaling timeout */
175 { PL_LC_LENGTH, TP_LC_LENGTH }, /* Link Confidence Test Time */
176 { PL_T_SCRUB, TP_T_SCRUB }, /* Scrub Time == MAC TVX time ! */
177 { PL_NS_MAX, TP_NS_MAX }, /* max t. that noise is tolerated */
186 * Do we need the EBUF error during signaling, too, to detect SUPERNET_3
189 static int plc_imsk_na = PL_PCM_CODE | PL_TRACE_PROP | PL_PCM_BREAK |
190 PL_PCM_ENABLED | PL_SELF_TEST | PL_EBUF_ERR;
191 #else /* SUPERNET_3 */
193 * We do NOT need the elasticity buffer error during signaling.
195 static int plc_imsk_na = PL_PCM_CODE | PL_TRACE_PROP | PL_PCM_BREAK |
196 PL_PCM_ENABLED | PL_SELF_TEST ;
197 #endif /* SUPERNET_3 */
198 static int plc_imsk_act = PL_PCM_CODE | PL_TRACE_PROP | PL_PCM_BREAK |
199 PL_PCM_ENABLED | PL_SELF_TEST | PL_EBUF_ERR;
201 /* external functions */
202 void all_selection_criteria ();
204 /* internal functions */
205 static void pcm_fsm() ;
206 static void pc_rcode_actions() ;
207 static void pc_tcode_actions() ;
208 static void reset_lem_struct() ;
209 static void plc_init() ;
210 static void sm_ph_lem_start() ;
211 static void sm_ph_lem_stop() ;
212 static void sm_ph_linestate() ;
213 static void real_init_plc() ;
216 * SMT timer interface
219 static void start_pcm_timer0(smc,value,event,phy)
225 phy->timer0_exp = FALSE ; /* clear timer event flag */
226 smt_timer_start(smc,&phy->pcm_timer0,value,
227 EV_TOKEN(EVENT_PCM+phy->np,event)) ;
230 * SMT timer interface
233 static void stop_pcm_timer0(smc,phy)
237 if (phy->pcm_timer0.tm_active)
238 smt_timer_stop(smc,&phy->pcm_timer0) ;
242 init PCM state machine (called by driver)
243 clear all PCM vars and flags
251 struct fddi_mib_p *mib ;
253 for (np = 0,phy = smc->y ; np < NUMPHYS ; np++,phy++) {
254 /* Indicates the type of PHY being used */
256 mib->fddiPORTPCMState = ACTIONS(PC0_OFF) ;
258 switch (smc->s.sas) {
261 mib->fddiPORTMy_Type = (np == PS) ? TS : TM ;
264 mib->fddiPORTMy_Type = (np == PA) ? TA :
265 (np == PB) ? TB : TM ;
268 mib->fddiPORTMy_Type = TM ;
272 mib->fddiPORTMy_Type = (np == PS) ? TS : TNONE ;
273 mib->fddiPORTHardwarePresent = (np == PS) ? TRUE :
276 smc->y[PA].mib->fddiPORTPCMState = PC0_OFF ;
278 smc->y[PB].mib->fddiPORTPCMState = PC0_OFF ;
282 mib->fddiPORTMy_Type = (np == PB) ? TB : TA ;
289 phy->pmd_scramble = 0 ;
290 switch (phy->pmd_type[PMD_SK_PMD]) {
292 mib->fddiPORTPMDClass = MIB_PMDCLASS_MULTI ;
295 mib->fddiPORTPMDClass = MIB_PMDCLASS_LCF ;
298 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
301 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
302 phy->pmd_scramble = TRUE ;
305 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
306 phy->pmd_scramble = TRUE ;
309 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE1 ;
312 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE2 ;
315 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE2 ;
318 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE1 ;
321 mib->fddiPORTPMDClass = MIB_PMDCLASS_UNKNOWN ;
324 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
327 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
330 mib->fddiPORTPMDClass = MIB_PMDCLASS_UNKNOWN ;
334 * A and B port can be on primary and secondary path
336 switch (mib->fddiPORTMy_Type) {
338 mib->fddiPORTAvailablePaths |= MIB_PATH_S ;
339 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
340 mib->fddiPORTRequestedPaths[2] =
342 MIB_P_PATH_CON_ALTER |
343 MIB_P_PATH_SEC_PREFER ;
344 mib->fddiPORTRequestedPaths[3] =
346 MIB_P_PATH_CON_ALTER |
347 MIB_P_PATH_SEC_PREFER |
351 mib->fddiPORTAvailablePaths |= MIB_PATH_S ;
352 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
353 mib->fddiPORTRequestedPaths[2] =
355 MIB_P_PATH_PRIM_PREFER ;
356 mib->fddiPORTRequestedPaths[3] =
358 MIB_P_PATH_PRIM_PREFER |
359 MIB_P_PATH_CON_PREFER |
363 mib->fddiPORTAvailablePaths |= MIB_PATH_S ;
364 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
365 mib->fddiPORTRequestedPaths[2] =
367 MIB_P_PATH_CON_ALTER |
368 MIB_P_PATH_PRIM_PREFER ;
369 mib->fddiPORTRequestedPaths[3] =
371 MIB_P_PATH_CON_ALTER |
372 MIB_P_PATH_PRIM_PREFER ;
375 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
376 mib->fddiPORTRequestedPaths[2] =
378 MIB_P_PATH_SEC_ALTER |
379 MIB_P_PATH_PRIM_ALTER ;
380 mib->fddiPORTRequestedPaths[3] = 0 ;
384 phy->pc_lem_fail = FALSE ;
385 mib->fddiPORTPCMStateX = mib->fddiPORTPCMState ;
386 mib->fddiPORTLCTFail_Ct = 0 ;
387 mib->fddiPORTBS_Flag = 0 ;
388 mib->fddiPORTCurrentPath = MIB_PATH_ISOLATED ;
389 mib->fddiPORTNeighborType = TNONE ;
395 phy->phy_name = '0' + np - PM ;
397 phy->phy_name = 'A' + np ;
398 phy->wc_flag = FALSE ; /* set by SMT */
399 memset((char *)&phy->lem,0,sizeof(struct lem_counter)) ;
400 reset_lem_struct(phy) ;
401 memset((char *)&phy->plc,0,sizeof(struct s_plc)) ;
402 phy->plc.p_state = PS_OFF ;
403 for (i = 0 ; i < NUMBITS ; i++) {
417 * this is an obsolete public entry point that has to remain
418 * for compat. It is used by various drivers.
419 * the work is now done in real_init_plc()
420 * which is called from pcm_init() ;
424 static void real_init_plc(smc)
429 for (p = 0 ; p < NUMPHYS ; p++)
433 static void plc_init(smc,p)
439 int rev ; /* Revision of PLC-x */
442 /* transit PCM state machine to MAINT state */
443 outpw(PLC(p,PL_CNTRL_B),0) ;
444 outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ;
445 outpw(PLC(p,PL_CNTRL_A),0) ;
448 * if PLC-S then set control register C
451 rev = inpw(PLC(p,PL_STATUS_A)) & PLC_REV_MASK ;
452 if (rev != PLC_REVISION_A)
455 if (smc->y[p].pmd_scramble) {
456 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_S) ;
458 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_S) ;
459 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_S) ;
463 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_U) ;
465 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_U) ;
466 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_U) ;
474 for ( i = 0 ; pltm[i].timer; i++) /* set timer parameter reg */
475 outpw(PLC(p,pltm[i].timer),pltm[i].para) ;
477 (void)inpw(PLC(p,PL_INTR_EVENT)) ; /* clear interrupt event reg */
478 plc_clear_irq(smc,p) ;
479 outpw(PLC(p,PL_INTR_MASK),plc_imsk_na); /* enable non active irq's */
482 * if PCM is configured for class s, it will NOT go to the
483 * REMOVE state if offline (page 3-36;)
484 * in the concentrator, all inactive PHYS always must be in
486 * there's no real need to use this feature at all ..
489 if ((smc->s.sas == SMT_SAS) && (p == PS)) {
490 outpw(PLC(p,PL_CNTRL_B),PL_CLASS_S) ;
496 * control PCM state machine
498 static void plc_go_state(smc,p,state)
508 port = (HW_PTR) (PLC(p,PL_CNTRL_B)) ;
509 val = inpw(port) & ~(PL_PCM_CNTRL | PL_MAINT) ;
511 outpw(port,val | state) ;
515 * read current line state (called by ECM & PCM)
517 int sm_pm_get_ls(smc,phy)
524 if (!plc_is_installed(smc,phy))
528 state = inpw(PLC(phy,PL_STATUS_A)) & PL_LINE_ST ;
552 static int plc_send_bits(smc,phy,len)
557 int np = phy->np ; /* PHY index */
563 /* create bit vector */
564 for (i = len-1,n = 0 ; i >= 0 ; i--) {
565 n = (n<<1) | phy->t_val[phy->bitn+i] ;
567 if (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL) {
569 printf("PL_PCM_SIGNAL is set\n") ;
573 /* write bit[n] & length = 1 to regs */
574 outpw(PLC(np,PL_VECTOR_LEN),len-1) ; /* len=nr-1 */
575 outpw(PLC(np,PL_XMIT_VECTOR),n) ;
579 if (smc->debug.d_plc & 0x80)
581 if (debug.d_plc & 0x80)
583 printf("SIGNALING bit %d .. %d\n",phy->bitn,phy->bitn+len-1) ;
592 void plc_config_mux(smc,mux)
596 if (smc->s.sas != SMT_DAS)
598 if (mux == MUX_WRAPB) {
599 SETMASK(PLC(PA,PL_CNTRL_B),PL_CONFIG_CNTRL,PL_CONFIG_CNTRL) ;
600 SETMASK(PLC(PA,PL_CNTRL_A),PL_SC_REM_LOOP,PL_SC_REM_LOOP) ;
603 CLEAR(PLC(PA,PL_CNTRL_B),PL_CONFIG_CNTRL) ;
604 CLEAR(PLC(PA,PL_CNTRL_A),PL_SC_REM_LOOP) ;
606 CLEAR(PLC(PB,PL_CNTRL_B),PL_CONFIG_CNTRL) ;
607 CLEAR(PLC(PB,PL_CNTRL_A),PL_SC_REM_LOOP) ;
612 called by dispatcher & fddi_init() (driver)
618 void pcm(smc,np,event)
626 struct fddi_mib_p *mib ;
630 * ignore 2nd PHY if SAS
632 if ((np != PS) && (smc->s.sas == SMT_SAS))
637 oldstate = mib->fddiPORTPCMState ;
639 DB_PCM("PCM %c: state %s",
641 (mib->fddiPORTPCMState & AFLAG) ? "ACTIONS " : "") ;
642 DB_PCM("%s, event %s\n",
643 pcm_states[mib->fddiPORTPCMState & ~AFLAG],
645 state = mib->fddiPORTPCMState ;
646 pcm_fsm(smc,phy,event) ;
648 } while (state != mib->fddiPORTPCMState) ;
650 * because the PLC does the bit signaling for us,
651 * we're always in SIGNAL state
652 * the MIB want's to see CONNECT
653 * we therefore fake an entry in the MIB
655 if (state == PC5_SIGNAL)
656 mib->fddiPORTPCMStateX = PC3_CONNECT ;
658 mib->fddiPORTPCMStateX = state ;
664 if ( mib->fddiPORTPCMState != oldstate &&
665 ((oldstate == PC8_ACTIVE) || (mib->fddiPORTPCMState == PC8_ACTIVE))) {
666 smt_srf_event(smc,SMT_EVENT_PORT_PATH_CHANGE,
667 (int) (INDEX_PORT+ phy->np),0) ;
672 /* check whether a snmp-trap has to be sent */
674 if ( mib->fddiPORTPCMState != oldstate ) {
675 /* a real state change took place */
676 DB_SNMP ("PCM from %d to %d\n", oldstate, mib->fddiPORTPCMState);
677 if ( mib->fddiPORTPCMState == PC0_OFF ) {
678 /* send first trap */
679 snmp_fddi_trap (smc, 1, (int) mib->fddiPORTIndex );
680 } else if ( oldstate == PC0_OFF ) {
681 /* send second trap */
682 snmp_fddi_trap (smc, 2, (int) mib->fddiPORTIndex );
683 } else if ( mib->fddiPORTPCMState != PC2_TRACE &&
684 oldstate == PC8_ACTIVE ) {
685 /* send third trap */
686 snmp_fddi_trap (smc, 3, (int) mib->fddiPORTIndex );
687 } else if ( mib->fddiPORTPCMState == PC8_ACTIVE ) {
688 /* send fourth trap */
689 snmp_fddi_trap (smc, 4, (int) mib->fddiPORTIndex );
694 pcm_state_change(smc,np,state) ;
700 static void pcm_fsm(smc,phy,cmd)
706 int np = phy->np ; /* PHY index */
708 struct fddi_mib_p *mib ;
710 u_short plc_rev ; /* Revision of the plc */
711 #endif /* nMOT_ELM */
717 * general transitions independent of state
722 if (mib->fddiPORTPCMState != PC9_MAINT) {
724 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
725 FDDI_PORT_EVENT, (u_long) FDDI_PORT_STOP,
726 smt_get_port_event_word(smc));
731 if (mib->fddiPORTPCMState != PC9_MAINT)
732 GO_STATE(PC1_BREAK) ;
736 GO_STATE(PC9_MAINT) ;
737 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
738 FDDI_PORT_EVENT, (u_long) FDDI_PORT_DISABLED,
739 smt_get_port_event_word(smc));
741 case PC_TIMEOUT_LCT :
742 /* if long or extended LCT */
743 stop_pcm_timer0(smc,phy) ;
744 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
745 /* end of LCT is indicate by PCM_CODE (initiate PCM event) */
749 switch(mib->fddiPORTPCMState) {
750 case ACTIONS(PC0_OFF) :
751 stop_pcm_timer0(smc,phy) ;
752 outpw(PLC(np,PL_CNTRL_A),0) ;
753 CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
754 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
755 sm_ph_lem_stop(smc,np) ; /* disable LEM */
756 phy->cf_loop = FALSE ;
757 phy->cf_join = FALSE ;
758 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
759 plc_go_state(smc,np,PL_PCM_STOP) ;
760 mib->fddiPORTConnectState = PCM_DISABLED ;
765 if (cmd == PC_MAINT) {
766 GO_STATE(PC9_MAINT) ;
770 case ACTIONS(PC1_BREAK) :
771 /* Stop the LCT timer if we came from Signal state */
772 stop_pcm_timer0(smc,phy) ;
774 plc_go_state(smc,np,0) ;
775 CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
776 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
777 sm_ph_lem_stop(smc,np) ; /* disable LEM */
779 * if vector is already loaded, go to OFF to clear PCM_SIGNAL
782 if (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL) {
783 plc_go_state(smc,np,PL_PCM_STOP) ;
788 * Go to OFF state in any case.
790 plc_go_state(smc,np,PL_PCM_STOP) ;
792 if (mib->fddiPORTPC_Withhold == PC_WH_NONE)
793 mib->fddiPORTConnectState = PCM_CONNECTING ;
794 phy->cf_loop = FALSE ;
795 phy->cf_join = FALSE ;
796 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
797 phy->ls_flag = FALSE ;
798 phy->pc_mode = PM_NONE ; /* needed by CFM */
799 phy->bitn = 0 ; /* bit signaling start bit */
800 for (i = 0 ; i < 3 ; i++)
801 pc_tcode_actions(smc,i,phy) ;
803 /* Set the non-active interrupt mask register */
804 outpw(PLC(np,PL_INTR_MASK),plc_imsk_na) ;
807 * If the LCT was stopped. There might be a
808 * PCM_CODE interrupt event present.
809 * This must be cleared.
811 (void)inpw(PLC(np,PL_INTR_EVENT)) ;
813 /* Get the plc revision for revision dependent code */
814 plc_rev = inpw(PLC(np,PL_STATUS_A)) & PLC_REV_MASK ;
816 if (plc_rev != PLC_REV_SN3)
820 * No supernet III PLC, so set Xmit verctor and
821 * length BEFORE starting the state machine.
823 if (plc_send_bits(smc,phy,3)) {
829 * Now give the Start command.
830 * - The start command shall be done before setting the bits
831 * to be signaled. (In PLC-S description and PLCS in SN3.
832 * - The start command shall be issued AFTER setting the
833 * XMIT vector and the XMIT length register.
835 * We do it exactly according this specs for the old PLC and
836 * the new PLCS inside the SN3.
837 * For the usual PLCS we try it the way it is done for the
838 * old PLC and set the XMIT registers again, if the PLC is
839 * not in SIGNAL state. This is done according to an PLCS
843 plc_go_state(smc,np,PL_PCM_START) ;
846 * workaround for PLC-S eng. sample errata
849 if (!(inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL))
851 if (((inpw(PLC(np,PL_STATUS_A)) & PLC_REV_MASK) !=
853 !(inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL))
854 #endif /* nMOT_ELM */
857 * Set register again (PLCS errata) or the first time
860 (void) plc_send_bits(smc,phy,3) ;
866 GO_STATE(PC5_SIGNAL) ;
867 plc->p_state = PS_BIT3 ;
874 case ACTIONS(PC2_TRACE) :
875 plc_go_state(smc,np,PL_PCM_TRACE) ;
881 case PC3_CONNECT : /* these states are done by hardware */
885 case ACTIONS(PC5_SIGNAL) :
888 if ((cmd != PC_SIGNAL) && (cmd != PC_TIMEOUT_LCT))
890 switch (plc->p_state) {
892 for (i = 0 ; i <= 2 ; i++)
893 pc_rcode_actions(smc,i,phy) ;
894 pc_tcode_actions(smc,3,phy) ;
895 plc->p_state = PS_BIT4 ;
899 if (plc_send_bits(smc,phy,1)) {
904 pc_rcode_actions(smc,3,phy) ;
905 for (i = 4 ; i <= 6 ; i++)
906 pc_tcode_actions(smc,i,phy) ;
907 plc->p_state = PS_BIT7 ;
911 if (plc_send_bits(smc,phy,3)) {
916 for (i = 3 ; i <= 6 ; i++)
917 pc_rcode_actions(smc,i,phy) ;
918 plc->p_state = PS_LCT ;
922 sm_ph_lem_start(smc,np,(int)smc->s.lct_short) ; /* enable LEM */
924 i = inpw(PLC(np,PL_CNTRL_B)) & ~PL_PC_LOOP ;
925 outpw(PLC(np,PL_CNTRL_B),i) ; /* must be cleared */
926 outpw(PLC(np,PL_CNTRL_B),i | PL_RLBP) ;
929 /* check for local LCT failure */
930 pc_tcode_actions(smc,7,phy) ;
934 plc->p_state = PS_BIT8 ;
938 if (plc_send_bits(smc,phy,1)) {
943 /* check for remote LCT failure */
944 pc_rcode_actions(smc,7,phy) ;
945 if (phy->t_val[7] || phy->r_val[7]) {
946 plc_go_state(smc,np,PL_PCM_STOP) ;
947 GO_STATE(PC1_BREAK) ;
950 for (i = 8 ; i <= 9 ; i++)
951 pc_tcode_actions(smc,i,phy) ;
952 plc->p_state = PS_JOIN ;
956 if (plc_send_bits(smc,phy,2)) {
961 for (i = 8 ; i <= 9 ; i++)
962 pc_rcode_actions(smc,i,phy) ;
963 plc->p_state = PS_ACTIVE ;
969 case ACTIONS(PC6_JOIN) :
971 * prevent mux error when going from WRAP_A to WRAP_B
973 if (smc->s.sas == SMT_DAS && np == PB &&
974 (smc->y[PA].pc_mode == PM_TREE ||
975 smc->y[PB].pc_mode == PM_TREE)) {
976 SETMASK(PLC(np,PL_CNTRL_A),
977 PL_SC_REM_LOOP,PL_SC_REM_LOOP) ;
978 SETMASK(PLC(np,PL_CNTRL_B),
979 PL_CONFIG_CNTRL,PL_CONFIG_CNTRL) ;
981 SETMASK(PLC(np,PL_CNTRL_B),PL_PC_JOIN,PL_PC_JOIN) ;
982 SETMASK(PLC(np,PL_CNTRL_B),PL_PC_JOIN,PL_PC_JOIN) ;
987 switch (plc->p_state) {
991 phy->cf_join = TRUE ;
992 queue_event(smc,EVENT_CFM,CF_JOIN+np) ; ;
995 GO_STATE(PC8_ACTIVE) ;
997 if (cmd == PC_TRACE) {
998 GO_STATE(PC2_TRACE) ;
1008 case ACTIONS(PC8_ACTIVE) :
1012 sm_ph_lem_start(smc,(int)phy->np,LCT_LEM_MAX) ;
1014 phy->tr_flag = FALSE ;
1015 mib->fddiPORTConnectState = PCM_ACTIVE ;
1017 /* Set the active interrupt mask register */
1018 outpw(PLC(np,PL_INTR_MASK),plc_imsk_act) ;
1023 /*PC81 is done by PL_TNE_EXPIRED irq */
1025 if (cmd == PC_TRACE) {
1026 GO_STATE(PC2_TRACE) ;
1029 /*PC88c: is done by TRACE_PROP irq */
1032 case ACTIONS(PC9_MAINT) :
1033 stop_pcm_timer0(smc,phy) ;
1034 CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
1035 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
1036 CLEAR(PLC(np,PL_INTR_MASK),PL_LE_CTR) ; /* disable LEM int. */
1037 sm_ph_lem_stop(smc,np) ; /* disable LEM */
1038 phy->cf_loop = FALSE ;
1039 phy->cf_join = FALSE ;
1040 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
1041 plc_go_state(smc,np,PL_PCM_STOP) ;
1042 mib->fddiPORTConnectState = PCM_DISABLED ;
1043 SETMASK(PLC(np,PL_CNTRL_B),PL_MAINT,PL_MAINT) ;
1044 sm_ph_linestate(smc,np,(int) MIB2LS(mib->fddiPORTMaint_LS)) ;
1045 outpw(PLC(np,PL_CNTRL_A),PL_SC_BYPASS) ;
1049 DB_PCMN(1,"PCM %c : MAINT\n",phy->phy_name,0) ;
1051 if (cmd == PC_ENABLE) {
1058 SMT_PANIC(smc,SMT_E0118, SMT_E0118_MSG) ;
1064 * force line state on a PHY output (only in MAINT state)
1066 static void sm_ph_linestate(smc,phy,ls)
1075 cntrl = (inpw(PLC(phy,PL_CNTRL_B)) & ~PL_MAINT_LS) |
1076 PL_PCM_STOP | PL_MAINT ;
1078 case PC_QLS: /* Force Quiet */
1079 cntrl |= PL_M_QUI0 ;
1081 case PC_MLS: /* Force Master */
1082 cntrl |= PL_M_MASTR ;
1084 case PC_HLS: /* Force Halt */
1085 cntrl |= PL_M_HALT ;
1088 case PC_ILS: /* Force Idle */
1089 cntrl |= PL_M_IDLE ;
1091 case PC_LS_PDR: /* Enable repeat filter */
1092 cntrl |= PL_M_TPDR ;
1095 outpw(PLC(phy,PL_CNTRL_B),cntrl) ;
1099 static void reset_lem_struct(phy)
1102 struct lem_counter *lem = &phy->lem ;
1104 phy->mib->fddiPORTLer_Estimate = 15 ;
1105 lem->lem_float_ber = 15 * 100 ;
1109 * link error monitor
1111 static void lem_evaluate(smc,phy)
1117 struct lem_counter *lem = &phy->lem ;
1118 struct fddi_mib_p *mib ;
1126 errors = inpw(PLC(((int) phy->np),PL_LINK_ERR_CTR)) ;
1127 lem->lem_errors += errors ;
1128 mib->fddiPORTLem_Ct += errors ;
1130 errors = lem->lem_errors ;
1132 * calculation is called on a intervall of 8 seconds
1133 * -> this means, that one error in 8 sec. is one of 8*125*10E6
1134 * the same as BER = 10E-9
1136 * -> 9 errors in 8 seconds mean:
1137 * BER = 9 * 10E-9 and this is
1138 * < 10E-8, so the limit of 10E-8 is not reached!
1141 if (!errors) ber = 15 ;
1142 else if (errors <= 9) ber = 9 ;
1143 else if (errors <= 99) ber = 8 ;
1144 else if (errors <= 999) ber = 7 ;
1145 else if (errors <= 9999) ber = 6 ;
1146 else if (errors <= 99999) ber = 5 ;
1147 else if (errors <= 999999) ber = 4 ;
1148 else if (errors <= 9999999) ber = 3 ;
1149 else if (errors <= 99999999) ber = 2 ;
1150 else if (errors <= 999999999) ber = 1 ;
1157 lem->lem_float_ber = lem->lem_float_ber * 7 + ber * 3 ;
1158 lem->lem_float_ber /= 10 ;
1159 mib->fddiPORTLer_Estimate = lem->lem_float_ber / 100 ;
1160 if (mib->fddiPORTLer_Estimate < 4) {
1161 mib->fddiPORTLer_Estimate = 4 ;
1164 if (lem->lem_errors) {
1165 DB_PCMN(1,"LEM %c :\n",phy->np == PB? 'B' : 'A',0) ;
1166 DB_PCMN(1,"errors : %ld\n",lem->lem_errors,0) ;
1167 DB_PCMN(1,"sum_errors : %ld\n",mib->fddiPORTLem_Ct,0) ;
1168 DB_PCMN(1,"current BER : 10E-%d\n",ber/100,0) ;
1169 DB_PCMN(1,"float BER : 10E-(%d/100)\n",lem->lem_float_ber,0) ;
1170 DB_PCMN(1,"avg. BER : 10E-%d\n",
1171 mib->fddiPORTLer_Estimate,0) ;
1174 lem->lem_errors = 0L ;
1177 cond = (mib->fddiPORTLer_Estimate <= mib->fddiPORTLer_Alarm) ?
1179 #ifdef SMT_EXT_CUTOFF
1180 smt_ler_alarm_check(smc,phy,cond) ;
1181 #endif /* nSMT_EXT_CUTOFF */
1182 if (cond != mib->fddiPORTLerFlag) {
1183 smt_srf_event(smc,SMT_COND_PORT_LER,
1184 (int) (INDEX_PORT+ phy->np) ,cond) ;
1188 if ( mib->fddiPORTLer_Estimate <= mib->fddiPORTLer_Cutoff) {
1189 phy->pc_lem_fail = TRUE ; /* flag */
1190 mib->fddiPORTLem_Reject_Ct++ ;
1192 * "forgive 10e-2" if we cutoff so we can come
1195 lem->lem_float_ber += 2*100 ;
1199 DB_PCMN(1,"PCM: LER cutoff on port %d cutoff %d\n",
1200 phy->np, mib->fddiPORTLer_Cutoff) ;
1202 #ifdef SMT_EXT_CUTOFF
1203 smt_port_off_event(smc,phy->np);
1204 #else /* nSMT_EXT_CUTOFF */
1205 queue_event(smc,(int)(EVENT_PCM+phy->np),PC_START) ;
1206 #endif /* nSMT_EXT_CUTOFF */
1211 * called by SMT to calculate LEM bit error rate
1213 void sm_lem_evaluate(smc)
1218 for (np = 0 ; np < NUMPHYS ; np++)
1219 lem_evaluate(smc,&smc->y[np]) ;
1222 static void lem_check_lct(smc,phy)
1226 struct lem_counter *lem = &phy->lem ;
1227 struct fddi_mib_p *mib ;
1232 phy->pc_lem_fail = FALSE ; /* flag */
1233 errors = inpw(PLC(((int)phy->np),PL_LINK_ERR_CTR)) ;
1234 lem->lem_errors += errors ;
1235 mib->fddiPORTLem_Ct += errors ;
1236 if (lem->lem_errors) {
1237 switch(phy->lc_test) {
1239 if (lem->lem_errors >= smc->s.lct_short)
1240 phy->pc_lem_fail = TRUE ;
1243 if (lem->lem_errors >= smc->s.lct_medium)
1244 phy->pc_lem_fail = TRUE ;
1247 if (lem->lem_errors >= smc->s.lct_long)
1248 phy->pc_lem_fail = TRUE ;
1251 if (lem->lem_errors >= smc->s.lct_extended)
1252 phy->pc_lem_fail = TRUE ;
1255 DB_PCMN(1," >>errors : %d\n",lem->lem_errors,0) ;
1257 if (phy->pc_lem_fail) {
1258 mib->fddiPORTLCTFail_Ct++ ;
1259 mib->fddiPORTLem_Reject_Ct++ ;
1262 mib->fddiPORTLCTFail_Ct = 0 ;
1268 static void sm_ph_lem_start(smc,np,threshold)
1273 struct lem_counter *lem = &smc->y[np].lem ;
1276 lem->lem_errors = 0L ;
1278 /* Do NOT reset mib->fddiPORTLer_Estimate here. It is called too
1282 outpw(PLC(np,PL_LE_THRESHOLD),threshold) ;
1283 (void)inpw(PLC(np,PL_LINK_ERR_CTR)) ; /* clear error counter */
1286 SETMASK(PLC(np,PL_INTR_MASK),PL_LE_CTR,PL_LE_CTR) ;
1289 static void sm_ph_lem_stop(smc,np)
1293 struct lem_counter *lem = &smc->y[np].lem ;
1296 CLEAR(PLC(np,PL_INTR_MASK),PL_LE_CTR) ;
1300 void sm_pm_ls_latch(smc,phy,on_off)
1303 int on_off; /* en- or disable ident. ls */
1307 phy = phy ; on_off = on_off ;
1313 * receive actions are called AFTER the bit n is received,
1314 * i.e. if pc_rcode_actions(5) is called, bit 6 is the next bit to be received
1318 * PCM pseudo code 5.1 .. 6.1
1320 static void pc_rcode_actions(smc,bit,phy)
1325 struct fddi_mib_p *mib ;
1329 DB_PCMN(1,"SIG rec %x %x: \n", bit,phy->r_val[bit] ) ;
1338 if (phy->r_val[1] == 0 && phy->r_val[2] == 0)
1339 mib->fddiPORTNeighborType = TA ;
1340 else if (phy->r_val[1] == 0 && phy->r_val[2] == 1)
1341 mib->fddiPORTNeighborType = TB ;
1342 else if (phy->r_val[1] == 1 && phy->r_val[2] == 0)
1343 mib->fddiPORTNeighborType = TS ;
1344 else if (phy->r_val[1] == 1 && phy->r_val[2] == 1)
1345 mib->fddiPORTNeighborType = TM ;
1348 if (mib->fddiPORTMy_Type == TM &&
1349 mib->fddiPORTNeighborType == TM) {
1350 DB_PCMN(1,"PCM %c : E100 withhold M-M\n",
1352 mib->fddiPORTPC_Withhold = PC_WH_M_M ;
1353 RS_SET(smc,RS_EVENT) ;
1355 else if (phy->t_val[3] || phy->r_val[3]) {
1356 mib->fddiPORTPC_Withhold = PC_WH_NONE ;
1357 if (mib->fddiPORTMy_Type == TM ||
1358 mib->fddiPORTNeighborType == TM)
1359 phy->pc_mode = PM_TREE ;
1361 phy->pc_mode = PM_PEER ;
1363 /* reevaluate the selection criteria (wc_flag) */
1364 all_selection_criteria (smc);
1367 mib->fddiPORTPC_Withhold = PC_WH_PATH ;
1371 mib->fddiPORTPC_Withhold = PC_WH_OTHER ;
1372 RS_SET(smc,RS_EVENT) ;
1373 DB_PCMN(1,"PCM %c : E101 withhold other\n",
1376 phy->twisted = ((mib->fddiPORTMy_Type != TS) &&
1377 (mib->fddiPORTMy_Type != TM) &&
1378 (mib->fddiPORTNeighborType ==
1379 mib->fddiPORTMy_Type)) ;
1381 DB_PCMN(1,"PCM %c : E102 !!! TWISTED !!!\n",
1388 if (phy->t_val[4] || phy->r_val[4]) {
1389 if ((phy->t_val[4] && phy->t_val[5]) ||
1390 (phy->r_val[4] && phy->r_val[5]) )
1391 phy->lc_test = LC_EXTENDED ;
1393 phy->lc_test = LC_LONG ;
1395 else if (phy->t_val[5] || phy->r_val[5])
1396 phy->lc_test = LC_MEDIUM ;
1398 phy->lc_test = LC_SHORT ;
1399 switch (phy->lc_test) {
1400 case LC_SHORT : /* 50ms */
1401 outpw(PLC((int)phy->np,PL_LC_LENGTH), TP_LC_LENGTH ) ;
1402 phy->t_next[7] = smc->s.pcm_lc_short ;
1404 case LC_MEDIUM : /* 500ms */
1405 outpw(PLC((int)phy->np,PL_LC_LENGTH), TP_LC_LONGLN ) ;
1406 phy->t_next[7] = smc->s.pcm_lc_medium ;
1409 SETMASK(PLC((int)phy->np,PL_CNTRL_B),PL_LONG,PL_LONG) ;
1410 phy->t_next[7] = smc->s.pcm_lc_long ;
1413 SETMASK(PLC((int)phy->np,PL_CNTRL_B),PL_LONG,PL_LONG) ;
1414 phy->t_next[7] = smc->s.pcm_lc_extended ;
1417 if (phy->t_next[7] > smc->s.pcm_lc_medium) {
1418 start_pcm_timer0(smc,phy->t_next[7],PC_TIMEOUT_LCT,phy);
1420 DB_PCMN(1,"LCT timer = %ld us\n", phy->t_next[7], 0) ;
1421 phy->t_next[9] = smc->s.pcm_t_next_9 ;
1424 if (phy->t_val[6]) {
1425 phy->cf_loop = TRUE ;
1427 phy->td_flag = TRUE ;
1430 if (phy->t_val[7] || phy->r_val[7]) {
1431 DB_PCMN(1,"PCM %c : E103 LCT fail %s\n",
1432 phy->phy_name,phy->t_val[7]? "local":"remote") ;
1433 queue_event(smc,(int)(EVENT_PCM+phy->np),PC_START) ;
1437 if (phy->t_val[8] || phy->r_val[8]) {
1439 phy->cf_loop = TRUE ;
1440 phy->td_flag = TRUE ;
1444 if (phy->r_val[9]) {
1445 /* neighbor intends to have MAC on output */ ;
1446 mib->fddiPORTMacIndicated.R_val = TRUE ;
1449 /* neighbor does not intend to have MAC on output */ ;
1450 mib->fddiPORTMacIndicated.R_val = FALSE ;
1457 * PCM pseudo code 5.1 .. 6.1
1459 static void pc_tcode_actions(smc,bit,phy)
1465 struct fddi_mib_p *mib ;
1471 phy->t_val[0] = 0 ; /* no escape used */
1474 if (mib->fddiPORTMy_Type == TS || mib->fddiPORTMy_Type == TM)
1480 if (mib->fddiPORTMy_Type == TB || mib->fddiPORTMy_Type == TM)
1490 type = mib->fddiPORTMy_Type ;
1491 ne = mib->fddiPORTNeighborType ;
1492 policy = smc->mib.fddiSMTConnectionPolicy ;
1494 phy->t_val[3] = 1 ; /* Accept connection */
1498 ((policy & POLICY_AA) && ne == TA) ||
1499 ((policy & POLICY_AB) && ne == TB) ||
1500 ((policy & POLICY_AS) && ne == TS) ||
1501 ((policy & POLICY_AM) && ne == TM) )
1502 phy->t_val[3] = 0 ; /* Reject */
1506 ((policy & POLICY_BA) && ne == TA) ||
1507 ((policy & POLICY_BB) && ne == TB) ||
1508 ((policy & POLICY_BS) && ne == TS) ||
1509 ((policy & POLICY_BM) && ne == TM) )
1510 phy->t_val[3] = 0 ; /* Reject */
1514 ((policy & POLICY_SA) && ne == TA) ||
1515 ((policy & POLICY_SB) && ne == TB) ||
1516 ((policy & POLICY_SS) && ne == TS) ||
1517 ((policy & POLICY_SM) && ne == TM) )
1518 phy->t_val[3] = 0 ; /* Reject */
1522 ((policy & POLICY_MA) && ne == TA) ||
1523 ((policy & POLICY_MB) && ne == TB) ||
1524 ((policy & POLICY_MS) && ne == TS) ||
1525 ((policy & POLICY_MM) && ne == TM) )
1526 phy->t_val[3] = 0 ; /* Reject */
1531 * detect undesirable connection attempt event
1533 if ( (type == TA && ne == TA ) ||
1534 (type == TA && ne == TS ) ||
1535 (type == TB && ne == TB ) ||
1536 (type == TB && ne == TS ) ||
1537 (type == TS && ne == TA ) ||
1538 (type == TS && ne == TB ) ) {
1539 smt_srf_event(smc,SMT_EVENT_PORT_CONNECTION,
1540 (int) (INDEX_PORT+ phy->np) ,0) ;
1546 if (mib->fddiPORTPC_Withhold == PC_WH_NONE) {
1547 if (phy->pc_lem_fail) {
1548 phy->t_val[4] = 1 ; /* long */
1553 if (mib->fddiPORTLCTFail_Ct > 0)
1554 phy->t_val[5] = 1 ; /* medium */
1556 phy->t_val[5] = 0 ; /* short */
1559 * Implementers choice: use medium
1560 * instead of short when undesired
1561 * connection attempt is made.
1564 phy->t_val[5] = 1 ; /* medium */
1566 mib->fddiPORTConnectState = PCM_CONNECTING ;
1569 mib->fddiPORTConnectState = PCM_STANDBY ;
1570 phy->t_val[4] = 1 ; /* extended */
1577 /* we do NOT have a MAC for LCT */
1581 phy->cf_loop = FALSE ;
1582 lem_check_lct(smc,phy) ;
1583 if (phy->pc_lem_fail) {
1584 DB_PCMN(1,"PCM %c : E104 LCT failed\n",
1592 phy->t_val[8] = 0 ; /* Don't request MAC loopback */
1596 if ((mib->fddiPORTPC_Withhold != PC_WH_NONE) ||
1597 ((smc->s.sas == SMT_DAS) && (phy->wc_flag))) {
1598 queue_event(smc,EVENT_PCM+np,PC_START) ;
1601 phy->t_val[9] = FALSE ;
1602 switch (smc->s.sas) {
1605 * MAC intended on output
1607 if (phy->pc_mode == PM_TREE) {
1608 if ((np == PB) || ((np == PA) &&
1609 (smc->y[PB].mib->fddiPORTConnectState !=
1611 phy->t_val[9] = TRUE ;
1615 phy->t_val[9] = TRUE ;
1620 phy->t_val[9] = TRUE ;
1625 * MAC intended on output
1628 phy->t_val[9] = TRUE ;
1632 mib->fddiPORTMacIndicated.T_val = phy->t_val[9] ;
1635 DB_PCMN(1,"SIG snd %x %x: \n", bit,phy->t_val[bit] ) ;
1639 * return status twisted (called by SMT)
1641 int pcm_status_twisted(smc)
1645 if (smc->s.sas != SMT_DAS)
1647 if (smc->y[PA].twisted && (smc->y[PA].mib->fddiPORTPCMState == PC8_ACTIVE))
1649 if (smc->y[PB].twisted && (smc->y[PB].mib->fddiPORTPCMState == PC8_ACTIVE))
1655 * return status (called by SMT)
1661 void pcm_status_state(smc,np,type,state,remote,mac)
1669 struct s_phy *phy = &smc->y[np] ;
1670 struct fddi_mib_p *mib ;
1674 /* remote PHY type and MAC - set only if active */
1676 *type = mib->fddiPORTMy_Type ; /* our PHY type */
1677 *state = mib->fddiPORTConnectState ;
1678 *remote = mib->fddiPORTNeighborType ;
1680 switch(mib->fddiPORTPCMState) {
1682 *mac = mib->fddiPORTMacIndicated.R_val ;
1688 * return rooted station status (called by SMT)
1690 int pcm_rooted_station(smc)
1695 for (n = 0 ; n < NUMPHYS ; n++) {
1696 if (smc->y[n].mib->fddiPORTPCMState == PC8_ACTIVE &&
1697 smc->y[n].mib->fddiPORTNeighborType == TM)
1704 * Interrupt actions for PLC & PCM events
1706 void plc_irq(smc,np,cmd)
1708 int np; /* PHY index */
1711 struct s_phy *phy = &smc->y[np] ;
1712 struct s_plc *plc = &phy->plc ;
1716 #endif /* SUPERNET_3 */
1719 if (np >= smc->s.numphys) {
1723 if (cmd & PL_EBUF_ERR) { /* elastic buff. det. over-|underflow*/
1725 * Check whether the SRF Condition occurred.
1727 if (!plc->ebuf_cont && phy->mib->fddiPORTPCMState == PC8_ACTIVE){
1729 * This is the real Elasticity Error.
1730 * More than one in a row are treated as a
1732 * Only count this in the active state.
1734 phy->mib->fddiPORTEBError_Ct ++ ;
1739 if (plc->ebuf_cont <= 1000) {
1741 * Prevent counter from being wrapped after
1742 * hanging years in that interrupt.
1744 plc->ebuf_cont++ ; /* Ebuf continous error */
1748 if (plc->ebuf_cont == 1000 &&
1749 ((inpw(PLC(np,PL_STATUS_A)) & PLC_REV_MASK) ==
1752 * This interrupt remeained high for at least
1753 * 1000 consecutive interrupt calls.
1755 * This is caused by a hardware error of the
1756 * ORION part of the Supernet III chipset.
1758 * Disable this bit from the mask.
1760 corr_mask = (plc_imsk_na & ~PL_EBUF_ERR) ;
1761 outpw(PLC(np,PL_INTR_MASK),corr_mask);
1764 * Disconnect from the ring.
1765 * Call the driver with the reset indication.
1767 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
1770 * Make an error log entry.
1772 SMT_ERR_LOG(smc,SMT_E0136, SMT_E0136_MSG) ;
1775 * Indicate the Reset.
1777 drv_reset_indication(smc) ;
1779 #endif /* SUPERNET_3 */
1781 /* Reset the continous error variable */
1782 plc->ebuf_cont = 0 ; /* reset Ebuf continous error */
1784 if (cmd & PL_PHYINV) { /* physical layer invalid signal */
1787 if (cmd & PL_VSYM_CTR) { /* violation symbol counter has incr.*/
1790 if (cmd & PL_MINI_CTR) { /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
1793 if (cmd & PL_LE_CTR) { /* link error event counter */
1797 * note: PL_LINK_ERR_CTR MUST be read to clear it
1799 j = inpw(PLC(np,PL_LE_THRESHOLD)) ;
1800 i = inpw(PLC(np,PL_LINK_ERR_CTR)) ;
1803 /* wrapped around */
1807 if (phy->lem.lem_on) {
1808 /* Note: Lem errors shall only be counted when
1809 * link is ACTIVE or LCT is active.
1811 phy->lem.lem_errors += i ;
1812 phy->mib->fddiPORTLem_Ct += i ;
1815 if (cmd & PL_TPC_EXPIRED) { /* TPC timer reached zero */
1816 if (plc->p_state == PS_LCT) {
1824 if (cmd & PL_LS_MATCH) { /* LS == LS in PLC_CNTRL_B's MATCH_LS*/
1825 switch (inpw(PLC(np,PL_CNTRL_B)) & PL_MATCH_LS) {
1826 case PL_I_IDLE : phy->curr_ls = PC_ILS ; break ;
1827 case PL_I_HALT : phy->curr_ls = PC_HLS ; break ;
1828 case PL_I_MASTR : phy->curr_ls = PC_MLS ; break ;
1829 case PL_I_QUIET : phy->curr_ls = PC_QLS ; break ;
1832 if (cmd & PL_PCM_BREAK) { /* PCM has entered the BREAK state */
1835 reason = inpw(PLC(np,PL_STATUS_B)) & PL_BREAK_REASON ;
1838 case PL_B_PCS : plc->b_pcs++ ; break ;
1839 case PL_B_TPC : plc->b_tpc++ ; break ;
1840 case PL_B_TNE : plc->b_tne++ ; break ;
1841 case PL_B_QLS : plc->b_qls++ ; break ;
1842 case PL_B_ILS : plc->b_ils++ ; break ;
1843 case PL_B_HLS : plc->b_hls++ ; break ;
1846 /*jd 05-Aug-1999 changed: Bug #10419 */
1847 DB_PCMN(1,"PLC %d: MDcF = %x\n", np, smc->e.DisconnectFlag);
1848 if (smc->e.DisconnectFlag == FALSE) {
1849 DB_PCMN(1,"PLC %d: restart (reason %x)\n", np, reason);
1850 queue_event(smc,EVENT_PCM+np,PC_START) ;
1853 DB_PCMN(1,"PLC %d: NO!! restart (reason %x)\n", np, reason);
1858 * If both CODE & ENABLE are set ignore enable
1860 if (cmd & PL_PCM_CODE) { /* receive last sign.-bit | LCT complete */
1861 queue_event(smc,EVENT_PCM+np,PC_SIGNAL) ;
1862 n = inpw(PLC(np,PL_RCV_VECTOR)) ;
1863 for (i = 0 ; i < plc->p_bits ; i++) {
1864 phy->r_val[plc->p_start+i] = n & 1 ;
1868 else if (cmd & PL_PCM_ENABLED) { /* asserted SC_JOIN, scrub.completed*/
1869 queue_event(smc,EVENT_PCM+np,PC_JOIN) ;
1871 if (cmd & PL_TRACE_PROP) { /* MLS while PC8_ACTIV || PC2_TRACE */
1873 if (!phy->tr_flag) {
1874 DB_PCMN(1,"PCM : irq TRACE_PROP %d %d\n",
1875 np,smc->mib.fddiSMTECMState) ;
1876 phy->tr_flag = TRUE ;
1877 smc->e.trace_prop |= ENTITY_BIT(ENTITY_PHY(np)) ;
1878 queue_event(smc,EVENT_ECM,EC_TRACE_PROP) ;
1882 * filter PLC glitch ???
1883 * QLS || HLS only while in PC2_TRACE state
1885 if ((cmd & PL_SELF_TEST) && (phy->mib->fddiPORTPCMState == PC2_TRACE)) {
1887 if (smc->e.path_test == PT_PASSED) {
1888 DB_PCMN(1,"PCM : state = %s %d\n", get_pcmstate(smc,np),
1889 phy->mib->fddiPORTPCMState) ;
1891 smc->e.path_test = PT_PENDING ;
1892 queue_event(smc,EVENT_ECM,EC_PATH_TEST) ;
1895 if (cmd & PL_TNE_EXPIRED) { /* TNE: length of noise events */
1896 /* break_required (TNE > NS_Max) */
1897 if (phy->mib->fddiPORTPCMState == PC8_ACTIVE) {
1898 if (!phy->tr_flag) {
1899 DB_PCMN(1,"PCM %c : PC81 %s\n",phy->phy_name,"NSE");
1900 queue_event(smc,EVENT_PCM+np,PC_START) ;
1906 if (cmd & PL_NP_ERR) { /* NP has requested to r/w an inv reg*/
1912 /* pin inactiv (GND) */
1913 if (cmd & PL_PARITY_ERR) { /* p. error dedected on TX9-0 inp */
1916 if (cmd & PL_LSDO) { /* carrier detected */
1922 void pcm_set_lct_short(smc,n)
1926 if (n <= 0 || n > 1000)
1928 smc->s.lct_short = n ;
1935 void pcm_get_state(smc,state)
1937 struct smt_state *state ;
1940 struct pcm_state *pcs ;
1945 struct fddi_mib_p *mib ;
1947 for (i = 0, phy = smc->y, pcs = state->pcm_state ; i < NUMPHYS ;
1948 i++ , phy++, pcs++ ) {
1950 pcs->pcm_type = (u_char) mib->fddiPORTMy_Type ;
1951 pcs->pcm_state = (u_char) mib->fddiPORTPCMState ;
1952 pcs->pcm_mode = phy->pc_mode ;
1953 pcs->pcm_neighbor = (u_char) mib->fddiPORTNeighborType ;
1954 pcs->pcm_bsf = mib->fddiPORTBS_Flag ;
1955 pcs->pcm_lsf = phy->ls_flag ;
1956 pcs->pcm_lct_fail = (u_char) mib->fddiPORTLCTFail_Ct ;
1957 pcs->pcm_ls_rx = LS2MIB(sm_pm_get_ls(smc,i)) ;
1958 for (ii = 0, rbits = tbits = 0 ; ii < NUMBITS ; ii++) {
1961 if (phy->r_val[NUMBITS-1-ii])
1963 if (phy->t_val[NUMBITS-1-ii])
1966 pcs->pcm_r_val = rbits ;
1967 pcs->pcm_t_val = tbits ;
1971 int get_pcm_state(smc,np)
1979 switch (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_STATE) {
1980 case PL_PC0 : pcs = PC_STOP ; break ;
1981 case PL_PC1 : pcs = PC_START ; break ;
1982 case PL_PC2 : pcs = PC_TRACE ; break ;
1983 case PL_PC3 : pcs = PC_SIGNAL ; break ;
1984 case PL_PC4 : pcs = PC_SIGNAL ; break ;
1985 case PL_PC5 : pcs = PC_SIGNAL ; break ;
1986 case PL_PC6 : pcs = PC_JOIN ; break ;
1987 case PL_PC7 : pcs = PC_JOIN ; break ;
1988 case PL_PC8 : pcs = PC_ENABLE ; break ;
1989 case PL_PC9 : pcs = PC_MAINT ; break ;
1990 default : pcs = PC_DISABLE ; break ;
1995 char *get_linestate(smc,np)
2003 switch (inpw(PLC(np,PL_STATUS_A)) & PL_LINE_ST) {
2004 case PL_L_NLS : ls = "NOISE" ; break ;
2005 case PL_L_ALS : ls = "ACTIV" ; break ;
2006 case PL_L_UND : ls = "UNDEF" ; break ;
2007 case PL_L_ILS4: ls = "ILS 4" ; break ;
2008 case PL_L_QLS : ls = "QLS" ; break ;
2009 case PL_L_MLS : ls = "MLS" ; break ;
2010 case PL_L_HLS : ls = "HLS" ; break ;
2011 case PL_L_ILS16:ls = "ILS16" ; break ;
2013 default: ls = "unknown" ; break ;
2019 char *get_pcmstate(smc,np)
2027 switch (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_STATE) {
2028 case PL_PC0 : pcs = "OFF" ; break ;
2029 case PL_PC1 : pcs = "BREAK" ; break ;
2030 case PL_PC2 : pcs = "TRACE" ; break ;
2031 case PL_PC3 : pcs = "CONNECT"; break ;
2032 case PL_PC4 : pcs = "NEXT" ; break ;
2033 case PL_PC5 : pcs = "SIGNAL" ; break ;
2034 case PL_PC6 : pcs = "JOIN" ; break ;
2035 case PL_PC7 : pcs = "VERIFY" ; break ;
2036 case PL_PC8 : pcs = "ACTIV" ; break ;
2037 case PL_PC9 : pcs = "MAINT" ; break ;
2038 default : pcs = "UNKNOWN" ; break ;
2049 for (np = 0 ; np < NUMPHYS ; np++) {
2050 plc = &smc->y[np].plc ;
2051 printf("PHY %d:\tERRORS\t\t\tBREAK_REASONS\t\tSTATES:\n",np) ;
2052 printf("\tsoft_error: %ld \t\tPC_Start : %ld\n",
2053 plc->soft_err,plc->b_pcs);
2054 printf("\tparity_err: %ld \t\tTPC exp. : %ld\t\tLine: %s\n",
2055 plc->parity_err,plc->b_tpc,get_linestate(smc,np)) ;
2056 printf("\tebuf_error: %ld \t\tTNE exp. : %ld\n",
2057 plc->ebuf_err,plc->b_tne) ;
2058 printf("\tphyinvalid: %ld \t\tQLS det. : %ld\t\tPCM : %s\n",
2059 plc->phyinv,plc->b_qls,get_pcmstate(smc,np)) ;
2060 printf("\tviosym_ctr: %ld \t\tILS det. : %ld\n",
2061 plc->vsym_ctr,plc->b_ils) ;
2062 printf("\tmingap_ctr: %ld \t\tHLS det. : %ld\n",
2063 plc->mini_ctr,plc->b_hls) ;
2064 printf("\tnodepr_err: %ld\n",plc->np_err) ;
2065 printf("\tTPC_exp : %ld\n",plc->tpc_exp) ;
2066 printf("\tLEM_err : %ld\n",smc->y[np].lem.lem_errors) ;
2072 void pcm_lem_dump(smc)
2077 struct fddi_mib_p *mib ;
2079 char *entostring() ;
2081 printf("PHY errors BER\n") ;
2082 printf("----------------------\n") ;
2083 for (i = 0,phy = smc->y ; i < NUMPHYS ; i++,phy++) {
2084 if (!plc_is_installed(smc,i))
2087 printf("%s\t%ld\t10E-%d\n",
2088 entostring(smc,ENTITY_PHY(i)),
2089 mib->fddiPORTLem_Ct,
2090 mib->fddiPORTLer_Estimate) ;