1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 * Support for Apple GMAC and assorted PHYs by
7 * Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Get rid of all those nasty mdelay's and replace them
11 * with schedule_timeout.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/fcntl.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34 #include <linux/random.h>
35 #include <linux/workqueue.h>
36 #include <linux/if_vlan.h>
38 #include <asm/system.h>
39 #include <asm/bitops.h>
41 #include <asm/byteorder.h>
42 #include <asm/uaccess.h>
46 #include <asm/idprom.h>
47 #include <asm/openprom.h>
48 #include <asm/oplib.h>
52 #ifdef CONFIG_PPC_PMAC
53 #include <asm/pci-bridge.h>
55 #include <asm/machdep.h>
56 #include <asm/pmac_feature.h>
59 #include "sungem_phy.h"
62 /* Stripping FCS is causing problems, disabled for now */
65 #define DEFAULT_MSG (NETIF_MSG_DRV | \
69 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
70 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
71 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
73 #define DRV_NAME "sungem"
74 #define DRV_VERSION "0.98"
75 #define DRV_RELDATE "8/24/03"
76 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
78 static char version[] __devinitdata =
79 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
81 MODULE_AUTHOR(DRV_AUTHOR);
82 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
83 MODULE_LICENSE("GPL");
85 #define GEM_MODULE_NAME "gem"
86 #define PFX GEM_MODULE_NAME ": "
88 static struct pci_device_id gem_pci_tbl[] = {
89 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
92 /* These models only differ from the original GEM in
93 * that their tx/rx fifos are of a different size and
94 * they only support 10/100 speeds. -DaveM
96 * Apple's GMAC does support gigabit on machines with
97 * the BCM54xx PHYs. -BenH
99 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
101 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
103 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
105 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
107 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
114 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
121 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
122 cmd |= (reg << 18) & MIF_FRAME_REGAD;
123 cmd |= (MIF_FRAME_TAMSB);
124 writel(cmd, gp->regs + MIF_FRAME);
127 cmd = readl(gp->regs + MIF_FRAME);
128 if (cmd & MIF_FRAME_TALSB)
137 return cmd & MIF_FRAME_DATA;
140 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
142 struct gem *gp = dev->priv;
143 return __phy_read(gp, mii_id, reg);
146 static inline u16 phy_read(struct gem *gp, int reg)
148 return __phy_read(gp, gp->mii_phy_addr, reg);
151 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
158 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
159 cmd |= (reg << 18) & MIF_FRAME_REGAD;
160 cmd |= (MIF_FRAME_TAMSB);
161 cmd |= (val & MIF_FRAME_DATA);
162 writel(cmd, gp->regs + MIF_FRAME);
165 cmd = readl(gp->regs + MIF_FRAME);
166 if (cmd & MIF_FRAME_TALSB)
173 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
175 struct gem *gp = dev->priv;
176 __phy_write(gp, mii_id, reg, val & 0xffff);
179 static inline void phy_write(struct gem *gp, int reg, u16 val)
181 __phy_write(gp, gp->mii_phy_addr, reg, val);
184 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
186 if (netif_msg_intr(gp))
187 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
190 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
192 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
195 if (netif_msg_intr(gp))
196 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
197 gp->dev->name, pcs_istat);
199 if (!(pcs_istat & PCS_ISTAT_LSC)) {
200 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
205 /* The link status bit latches on zero, so you must
206 * read it twice in such a case to see a transition
207 * to the link being up.
209 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
210 if (!(pcs_miistat & PCS_MIISTAT_LS))
212 (readl(gp->regs + PCS_MIISTAT) &
215 if (pcs_miistat & PCS_MIISTAT_ANC) {
216 /* The remote-fault indication is only valid
217 * when autoneg has completed.
219 if (pcs_miistat & PCS_MIISTAT_RF)
220 printk(KERN_INFO "%s: PCS AutoNEG complete, "
221 "RemoteFault\n", dev->name);
223 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
227 if (pcs_miistat & PCS_MIISTAT_LS) {
228 printk(KERN_INFO "%s: PCS link is now up.\n",
230 netif_carrier_on(gp->dev);
232 printk(KERN_INFO "%s: PCS link is now down.\n",
234 netif_carrier_off(gp->dev);
235 /* If this happens and the link timer is not running,
236 * reset so we re-negotiate.
238 if (!timer_pending(&gp->link_timer))
245 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
247 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
249 if (netif_msg_intr(gp))
250 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
251 gp->dev->name, txmac_stat);
253 /* Defer timer expiration is quite normal,
254 * don't even log the event.
256 if ((txmac_stat & MAC_TXSTAT_DTE) &&
257 !(txmac_stat & ~MAC_TXSTAT_DTE))
260 if (txmac_stat & MAC_TXSTAT_URUN) {
261 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
263 gp->net_stats.tx_fifo_errors++;
266 if (txmac_stat & MAC_TXSTAT_MPE) {
267 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
269 gp->net_stats.tx_errors++;
272 /* The rest are all cases of one of the 16-bit TX
275 if (txmac_stat & MAC_TXSTAT_NCE)
276 gp->net_stats.collisions += 0x10000;
278 if (txmac_stat & MAC_TXSTAT_ECE) {
279 gp->net_stats.tx_aborted_errors += 0x10000;
280 gp->net_stats.collisions += 0x10000;
283 if (txmac_stat & MAC_TXSTAT_LCE) {
284 gp->net_stats.tx_aborted_errors += 0x10000;
285 gp->net_stats.collisions += 0x10000;
288 /* We do not keep track of MAC_TXSTAT_FCE and
289 * MAC_TXSTAT_PCE events.
294 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
295 * so we do the following.
297 * If any part of the reset goes wrong, we return 1 and that causes the
298 * whole chip to be reset.
300 static int gem_rxmac_reset(struct gem *gp)
302 struct net_device *dev = gp->dev;
307 /* First, reset MAC RX. */
308 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
309 gp->regs + MAC_RXCFG);
310 for (limit = 0; limit < 5000; limit++) {
311 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
316 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
317 "chip.\n", dev->name);
321 /* Second, disable RX DMA. */
322 writel(0, gp->regs + RXDMA_CFG);
323 for (limit = 0; limit < 5000; limit++) {
324 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
329 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
330 "chip.\n", dev->name);
336 /* Execute RX reset command. */
337 writel(gp->swrst_base | GREG_SWRST_RXRST,
338 gp->regs + GREG_SWRST);
339 for (limit = 0; limit < 5000; limit++) {
340 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
345 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
346 "whole chip.\n", dev->name);
350 /* Refresh the RX ring. */
351 for (i = 0; i < RX_RING_SIZE; i++) {
352 struct gem_rxd *rxd = &gp->init_block->rxd[i];
354 if (gp->rx_skbs[i] == NULL) {
355 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
356 "whole chip.\n", dev->name);
360 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
362 gp->rx_new = gp->rx_old = 0;
364 /* Now we must reprogram the rest of RX unit. */
365 desc_dma = (u64) gp->gblock_dvma;
366 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
367 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
368 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
369 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
370 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
371 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
372 writel(val, gp->regs + RXDMA_CFG);
373 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
374 writel(((5 & RXDMA_BLANK_IPKTS) |
375 ((8 << 12) & RXDMA_BLANK_ITIME)),
376 gp->regs + RXDMA_BLANK);
378 writel(((5 & RXDMA_BLANK_IPKTS) |
379 ((4 << 12) & RXDMA_BLANK_ITIME)),
380 gp->regs + RXDMA_BLANK);
381 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
382 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
383 writel(val, gp->regs + RXDMA_PTHRESH);
384 val = readl(gp->regs + RXDMA_CFG);
385 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
386 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
387 val = readl(gp->regs + MAC_RXCFG);
388 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
393 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
395 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
398 if (netif_msg_intr(gp))
399 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
400 gp->dev->name, rxmac_stat);
402 if (rxmac_stat & MAC_RXSTAT_OFLW) {
403 u32 smac = readl(gp->regs + MAC_SMACHINE);
405 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
407 gp->net_stats.rx_over_errors++;
408 gp->net_stats.rx_fifo_errors++;
410 ret = gem_rxmac_reset(gp);
413 if (rxmac_stat & MAC_RXSTAT_ACE)
414 gp->net_stats.rx_frame_errors += 0x10000;
416 if (rxmac_stat & MAC_RXSTAT_CCE)
417 gp->net_stats.rx_crc_errors += 0x10000;
419 if (rxmac_stat & MAC_RXSTAT_LCE)
420 gp->net_stats.rx_length_errors += 0x10000;
422 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
428 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
430 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
432 if (netif_msg_intr(gp))
433 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
434 gp->dev->name, mac_cstat);
436 /* This interrupt is just for pause frame and pause
437 * tracking. It is useful for diagnostics and debug
438 * but probably by default we will mask these events.
440 if (mac_cstat & MAC_CSTAT_PS)
443 if (mac_cstat & MAC_CSTAT_PRCV)
444 gp->pause_last_time_recvd = (mac_cstat >> 16);
449 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
451 u32 mif_status = readl(gp->regs + MIF_STATUS);
452 u32 reg_val, changed_bits;
454 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
455 changed_bits = (mif_status & MIF_STATUS_STAT);
457 gem_handle_mif_event(gp, reg_val, changed_bits);
462 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
464 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
466 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
467 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
468 printk(KERN_ERR "%s: PCI error [%04x] ",
469 dev->name, pci_estat);
471 if (pci_estat & GREG_PCIESTAT_BADACK)
472 printk("<No ACK64# during ABS64 cycle> ");
473 if (pci_estat & GREG_PCIESTAT_DTRTO)
474 printk("<Delayed transaction timeout> ");
475 if (pci_estat & GREG_PCIESTAT_OTHER)
479 pci_estat |= GREG_PCIESTAT_OTHER;
480 printk(KERN_ERR "%s: PCI error\n", dev->name);
483 if (pci_estat & GREG_PCIESTAT_OTHER) {
486 /* Interrogate PCI config space for the
489 pci_read_config_word(gp->pdev, PCI_STATUS,
491 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
492 dev->name, pci_cfg_stat);
493 if (pci_cfg_stat & PCI_STATUS_PARITY)
494 printk(KERN_ERR "%s: PCI parity error detected.\n",
496 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
497 printk(KERN_ERR "%s: PCI target abort.\n",
499 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
500 printk(KERN_ERR "%s: PCI master acks target abort.\n",
502 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
503 printk(KERN_ERR "%s: PCI master abort.\n",
505 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
506 printk(KERN_ERR "%s: PCI system error SERR#.\n",
508 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
509 printk(KERN_ERR "%s: PCI parity error.\n",
512 /* Write the error bits back to clear them. */
513 pci_cfg_stat &= (PCI_STATUS_PARITY |
514 PCI_STATUS_SIG_TARGET_ABORT |
515 PCI_STATUS_REC_TARGET_ABORT |
516 PCI_STATUS_REC_MASTER_ABORT |
517 PCI_STATUS_SIG_SYSTEM_ERROR |
518 PCI_STATUS_DETECTED_PARITY);
519 pci_write_config_word(gp->pdev,
520 PCI_STATUS, pci_cfg_stat);
523 /* For all PCI errors, we should reset the chip. */
527 /* All non-normal interrupt conditions get serviced here.
528 * Returns non-zero if we should just exit the interrupt
529 * handler right now (ie. if we reset the card which invalidates
530 * all of the other original irq status bits).
532 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
534 if (gem_status & GREG_STAT_RXNOBUF) {
535 /* Frame arrived, no free RX buffers available. */
536 if (netif_msg_rx_err(gp))
537 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
539 gp->net_stats.rx_dropped++;
542 if (gem_status & GREG_STAT_RXTAGERR) {
543 /* corrupt RX tag framing */
544 if (netif_msg_rx_err(gp))
545 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
547 gp->net_stats.rx_errors++;
552 if (gem_status & GREG_STAT_PCS) {
553 if (gem_pcs_interrupt(dev, gp, gem_status))
557 if (gem_status & GREG_STAT_TXMAC) {
558 if (gem_txmac_interrupt(dev, gp, gem_status))
562 if (gem_status & GREG_STAT_RXMAC) {
563 if (gem_rxmac_interrupt(dev, gp, gem_status))
567 if (gem_status & GREG_STAT_MAC) {
568 if (gem_mac_interrupt(dev, gp, gem_status))
572 if (gem_status & GREG_STAT_MIF) {
573 if (gem_mif_interrupt(dev, gp, gem_status))
577 if (gem_status & GREG_STAT_PCIERR) {
578 if (gem_pci_interrupt(dev, gp, gem_status))
585 gp->reset_task_pending = 2;
586 schedule_work(&gp->reset_task);
591 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
595 if (netif_msg_intr(gp))
596 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
597 gp->dev->name, gem_status);
600 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
601 while (entry != limit) {
608 if (netif_msg_tx_done(gp))
609 printk(KERN_DEBUG "%s: tx done, slot %d\n",
610 gp->dev->name, entry);
611 skb = gp->tx_skbs[entry];
612 if (skb_shinfo(skb)->nr_frags) {
613 int last = entry + skb_shinfo(skb)->nr_frags;
617 last &= (TX_RING_SIZE - 1);
619 walk = NEXT_TX(walk);
628 gp->tx_skbs[entry] = NULL;
629 gp->net_stats.tx_bytes += skb->len;
631 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
632 txd = &gp->init_block->txd[entry];
634 dma_addr = le64_to_cpu(txd->buffer);
635 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
637 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
638 entry = NEXT_TX(entry);
641 gp->net_stats.tx_packets++;
642 dev_kfree_skb_irq(skb);
646 if (netif_queue_stopped(dev) &&
647 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
648 netif_wake_queue(dev);
651 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
653 int cluster_start, curr, count, kick;
655 cluster_start = curr = (gp->rx_new & ~(4 - 1));
659 while (curr != limit) {
660 curr = NEXT_RX(curr);
662 struct gem_rxd *rxd =
663 &gp->init_block->rxd[cluster_start];
665 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
667 cluster_start = NEXT_RX(cluster_start);
668 if (cluster_start == curr)
677 writel(kick, gp->regs + RXDMA_KICK);
681 static void gem_rx(struct gem *gp)
686 if (netif_msg_intr(gp))
687 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
688 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
692 done = readl(gp->regs + RXDMA_DONE);
694 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
696 u64 status = cpu_to_le64(rxd->status_word);
700 if ((status & RXDCTRL_OWN) != 0)
703 /* When writing back RX descriptor, GEM writes status
704 * then buffer address, possibly in seperate transactions.
705 * If we don't wait for the chip to write both, we could
706 * post a new buffer to this descriptor then have GEM spam
707 * on the buffer address. We sync on the RX completion
708 * register to prevent this from happening.
711 done = readl(gp->regs + RXDMA_DONE);
716 skb = gp->rx_skbs[entry];
718 len = (status & RXDCTRL_BUFSZ) >> 16;
719 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
720 gp->net_stats.rx_errors++;
722 gp->net_stats.rx_length_errors++;
723 if (len & RXDCTRL_BAD)
724 gp->net_stats.rx_crc_errors++;
726 /* We'll just return it to GEM. */
728 gp->net_stats.rx_dropped++;
732 dma_addr = cpu_to_le64(rxd->buffer);
733 if (len > RX_COPY_THRESHOLD) {
734 struct sk_buff *new_skb;
736 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
737 if (new_skb == NULL) {
741 pci_unmap_page(gp->pdev, dma_addr,
742 RX_BUF_ALLOC_SIZE(gp),
744 gp->rx_skbs[entry] = new_skb;
745 new_skb->dev = gp->dev;
746 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
747 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
748 virt_to_page(new_skb->data),
749 offset_in_page(new_skb->data),
750 RX_BUF_ALLOC_SIZE(gp),
751 PCI_DMA_FROMDEVICE));
752 skb_reserve(new_skb, RX_OFFSET);
754 /* Trim the original skb for the netif. */
757 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
759 if (copy_skb == NULL) {
764 copy_skb->dev = gp->dev;
765 skb_reserve(copy_skb, 2);
766 skb_put(copy_skb, len);
767 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
768 memcpy(copy_skb->data, skb->data, len);
769 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
771 /* We'll reuse the original ring buffer. */
775 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
776 skb->ip_summed = CHECKSUM_HW;
777 skb->protocol = eth_type_trans(skb, gp->dev);
780 gp->net_stats.rx_packets++;
781 gp->net_stats.rx_bytes += len;
782 gp->dev->last_rx = jiffies;
785 entry = NEXT_RX(entry);
788 gem_post_rxds(gp, entry);
793 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
797 static irqreturn_t gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
799 struct net_device *dev = dev_id;
800 struct gem *gp = dev->priv;
801 u32 gem_status = readl(gp->regs + GREG_STAT);
803 /* Swallow interrupts when shutting the chip down */
804 if (gp->hw_running == 0)
807 spin_lock(&gp->lock);
809 if (gem_status & GREG_STAT_ABNORMAL) {
810 if (gem_abnormal_irq(dev, gp, gem_status))
813 if (gem_status & (GREG_STAT_TXALL | GREG_STAT_TXINTME))
814 gem_tx(dev, gp, gem_status);
815 if (gem_status & GREG_STAT_RXDONE)
819 spin_unlock(&gp->lock);
824 static void gem_tx_timeout(struct net_device *dev)
826 struct gem *gp = dev->priv;
828 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
829 if (!gp->hw_running) {
830 printk("%s: hrm.. hw not running !\n", dev->name);
833 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
835 readl(gp->regs + TXDMA_CFG),
836 readl(gp->regs + MAC_TXSTAT),
837 readl(gp->regs + MAC_TXCFG));
838 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
840 readl(gp->regs + RXDMA_CFG),
841 readl(gp->regs + MAC_RXSTAT),
842 readl(gp->regs + MAC_RXCFG));
844 spin_lock_irq(&gp->lock);
846 gp->reset_task_pending = 2;
847 schedule_work(&gp->reset_task);
849 spin_unlock_irq(&gp->lock);
852 static __inline__ int gem_intme(int entry)
854 /* Algorithm: IRQ every 1/2 of descriptors. */
855 if (!(entry & ((TX_RING_SIZE>>1)-1)))
861 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
863 struct gem *gp = dev->priv;
868 if (skb->ip_summed == CHECKSUM_HW) {
869 u64 csum_start_off, csum_stuff_off;
871 csum_start_off = (u64) (skb->h.raw - skb->data);
872 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
874 ctrl = (TXDCTRL_CENAB |
875 (csum_start_off << 15) |
876 (csum_stuff_off << 21));
879 spin_lock_irq(&gp->lock);
881 /* This is a hard error, log it. */
882 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
883 netif_stop_queue(dev);
884 spin_unlock_irq(&gp->lock);
885 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
891 gp->tx_skbs[entry] = skb;
893 if (skb_shinfo(skb)->nr_frags == 0) {
894 struct gem_txd *txd = &gp->init_block->txd[entry];
899 mapping = pci_map_page(gp->pdev,
900 virt_to_page(skb->data),
901 offset_in_page(skb->data),
902 len, PCI_DMA_TODEVICE);
903 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
904 if (gem_intme(entry))
905 ctrl |= TXDCTRL_INTME;
906 txd->buffer = cpu_to_le64(mapping);
908 txd->control_word = cpu_to_le64(ctrl);
909 entry = NEXT_TX(entry);
914 dma_addr_t first_mapping;
915 int frag, first_entry = entry;
918 if (gem_intme(entry))
919 intme |= TXDCTRL_INTME;
921 /* We must give this initial chunk to the device last.
922 * Otherwise we could race with the device.
924 first_len = skb_headlen(skb);
925 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
926 offset_in_page(skb->data),
927 first_len, PCI_DMA_TODEVICE);
928 entry = NEXT_TX(entry);
930 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
931 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
936 len = this_frag->size;
937 mapping = pci_map_page(gp->pdev,
939 this_frag->page_offset,
940 len, PCI_DMA_TODEVICE);
942 if (frag == skb_shinfo(skb)->nr_frags - 1)
943 this_ctrl |= TXDCTRL_EOF;
945 txd = &gp->init_block->txd[entry];
946 txd->buffer = cpu_to_le64(mapping);
948 txd->control_word = cpu_to_le64(this_ctrl | len);
950 if (gem_intme(entry))
951 intme |= TXDCTRL_INTME;
953 entry = NEXT_TX(entry);
955 txd = &gp->init_block->txd[first_entry];
956 txd->buffer = cpu_to_le64(first_mapping);
959 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
963 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
964 netif_stop_queue(dev);
966 if (netif_msg_tx_queued(gp))
967 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
968 dev->name, entry, skb->len);
970 writel(gp->tx_new, gp->regs + TXDMA_KICK);
971 spin_unlock_irq(&gp->lock);
973 dev->trans_start = jiffies;
978 /* Jumbo-grams don't seem to work :-( */
979 #define GEM_MIN_MTU 68
981 #define GEM_MAX_MTU 1500
983 #define GEM_MAX_MTU 9000
986 static int gem_change_mtu(struct net_device *dev, int new_mtu)
988 struct gem *gp = dev->priv;
990 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
993 if (!netif_running(dev) || !netif_device_present(dev)) {
994 /* We'll just catch it later when the
995 * device is up'd or resumed.
1001 spin_lock_irq(&gp->lock);
1003 gp->reset_task_pending = 1;
1004 schedule_work(&gp->reset_task);
1005 spin_unlock_irq(&gp->lock);
1007 flush_scheduled_work();
1012 #define STOP_TRIES 32
1014 /* Must be invoked under gp->lock. */
1015 static void gem_stop(struct gem *gp)
1020 /* Make sure we won't get any more interrupts */
1021 writel(0xffffffff, gp->regs + GREG_IMASK);
1023 /* Reset the chip */
1024 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1025 gp->regs + GREG_SWRST);
1031 val = readl(gp->regs + GREG_SWRST);
1034 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1037 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1040 /* Must be invoked under gp->lock. */
1041 static void gem_start_dma(struct gem *gp)
1045 /* We are ready to rock, turn everything on. */
1046 val = readl(gp->regs + TXDMA_CFG);
1047 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1048 val = readl(gp->regs + RXDMA_CFG);
1049 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1050 val = readl(gp->regs + MAC_TXCFG);
1051 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1052 val = readl(gp->regs + MAC_RXCFG);
1053 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1055 (void) readl(gp->regs + MAC_RXCFG);
1058 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
1060 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1065 /* Must be invoked under gp->lock. */
1066 // XXX dbl check what that function should do when called on PCS PHY
1067 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1069 u32 advertise, features;
1074 if (gp->phy_type != phy_mii_mdio0 &&
1075 gp->phy_type != phy_mii_mdio1)
1078 /* Setup advertise */
1079 if (found_mii_phy(gp))
1080 features = gp->phy_mii.def->features;
1084 advertise = features & ADVERTISE_MASK;
1085 if (gp->phy_mii.advertising != 0)
1086 advertise &= gp->phy_mii.advertising;
1088 autoneg = gp->want_autoneg;
1089 speed = gp->phy_mii.speed;
1090 duplex = gp->phy_mii.duplex;
1092 /* Setup link parameters */
1095 if (ep->autoneg == AUTONEG_ENABLE) {
1096 advertise = ep->advertising;
1101 duplex = ep->duplex;
1105 /* Sanitize settings based on PHY capabilities */
1106 if ((features & SUPPORTED_Autoneg) == 0)
1108 if (speed == SPEED_1000 &&
1109 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1111 if (speed == SPEED_100 &&
1112 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1114 if (duplex == DUPLEX_FULL &&
1115 !(features & (SUPPORTED_1000baseT_Full |
1116 SUPPORTED_100baseT_Full |
1117 SUPPORTED_10baseT_Full)))
1118 duplex = DUPLEX_HALF;
1122 /* If HW is down, we don't try to actually setup the PHY, we
1123 * just store the settings
1125 if (!gp->hw_running) {
1126 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1127 gp->phy_mii.speed = speed;
1128 gp->phy_mii.duplex = duplex;
1132 /* Configure PHY & start aneg */
1133 gp->want_autoneg = autoneg;
1135 if (found_mii_phy(gp))
1136 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1137 gp->lstate = link_aneg;
1139 if (found_mii_phy(gp))
1140 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1141 gp->lstate = link_force_ok;
1145 gp->timer_ticks = 0;
1146 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1149 /* A link-up condition has occurred, initialize and enable the
1152 * Must be invoked under gp->lock.
1154 static int gem_set_link_modes(struct gem *gp)
1157 int full_duplex, speed, pause;
1163 if (found_mii_phy(gp)) {
1164 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1166 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1167 speed = gp->phy_mii.speed;
1168 pause = gp->phy_mii.pause;
1169 } else if (gp->phy_type == phy_serialink ||
1170 gp->phy_type == phy_serdes) {
1171 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1173 if (pcs_lpa & PCS_MIIADV_FD)
1178 if (netif_msg_link(gp))
1179 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1180 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1182 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1184 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1186 /* MAC_TXCFG_NBO must be zero. */
1188 writel(val, gp->regs + MAC_TXCFG);
1190 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1192 (gp->phy_type == phy_mii_mdio0 ||
1193 gp->phy_type == phy_mii_mdio1)) {
1194 val |= MAC_XIFCFG_DISE;
1195 } else if (full_duplex) {
1196 val |= MAC_XIFCFG_FLED;
1199 if (speed == SPEED_1000)
1200 val |= (MAC_XIFCFG_GMII);
1202 writel(val, gp->regs + MAC_XIFCFG);
1204 /* If gigabit and half-duplex, enable carrier extension
1205 * mode. Else, disable it.
1207 if (speed == SPEED_1000 && !full_duplex) {
1208 val = readl(gp->regs + MAC_TXCFG);
1209 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1211 val = readl(gp->regs + MAC_RXCFG);
1212 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1214 val = readl(gp->regs + MAC_TXCFG);
1215 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1217 val = readl(gp->regs + MAC_RXCFG);
1218 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1221 if (gp->phy_type == phy_serialink ||
1222 gp->phy_type == phy_serdes) {
1223 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1225 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1229 if (netif_msg_link(gp)) {
1231 printk(KERN_INFO "%s: Pause is enabled "
1232 "(rxfifo: %d off: %d on: %d)\n",
1238 printk(KERN_INFO "%s: Pause is disabled\n",
1244 writel(512, gp->regs + MAC_STIME);
1246 writel(64, gp->regs + MAC_STIME);
1247 val = readl(gp->regs + MAC_MCCFG);
1249 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1251 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1252 writel(val, gp->regs + MAC_MCCFG);
1259 /* Must be invoked under gp->lock. */
1260 static int gem_mdio_link_not_up(struct gem *gp)
1262 switch (gp->lstate) {
1263 case link_force_ret:
1264 if (netif_msg_link(gp))
1265 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1266 " forced mode\n", gp->dev->name);
1267 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1268 gp->last_forced_speed, DUPLEX_HALF);
1269 gp->timer_ticks = 5;
1270 gp->lstate = link_force_ok;
1273 /* We try forced modes after a failed aneg only on PHYs that don't
1274 * have "magic_aneg" bit set, which means they internally do the
1275 * while forced-mode thingy. On these, we just restart aneg
1277 if (gp->phy_mii.def->magic_aneg)
1279 if (netif_msg_link(gp))
1280 printk(KERN_INFO "%s: switching to forced 100bt\n",
1282 /* Try forced modes. */
1283 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1285 gp->timer_ticks = 5;
1286 gp->lstate = link_force_try;
1288 case link_force_try:
1289 /* Downgrade from 100 to 10 Mbps if necessary.
1290 * If already at 10Mbps, warn user about the
1291 * situation every 10 ticks.
1293 if (gp->phy_mii.speed == SPEED_100) {
1294 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1296 gp->timer_ticks = 5;
1297 if (netif_msg_link(gp))
1298 printk(KERN_INFO "%s: switching to forced 10bt\n",
1308 static void gem_init_rings(struct gem *);
1309 static void gem_init_hw(struct gem *, int);
1311 static void gem_reset_task(void *data)
1313 struct gem *gp = (struct gem *) data;
1315 /* The link went down, we reset the ring, but keep
1316 * DMA stopped. Todo: Use this function for reset
1320 spin_lock_irq(&gp->lock);
1322 if (gp->hw_running && gp->opened) {
1323 /* Make sure we don't get interrupts or tx packets */
1324 netif_stop_queue(gp->dev);
1326 writel(0xffffffff, gp->regs + GREG_IMASK);
1328 /* Reset the chip & rings */
1333 (gp->reset_task_pending == 2));
1335 netif_wake_queue(gp->dev);
1337 gp->reset_task_pending = 0;
1339 spin_unlock_irq(&gp->lock);
1342 static void gem_link_timer(unsigned long data)
1344 struct gem *gp = (struct gem *) data;
1345 int restart_aneg = 0;
1347 if (!gp->hw_running)
1350 spin_lock_irq(&gp->lock);
1352 /* If the link of task is still pending, we just
1353 * reschedule the link timer
1355 if (gp->reset_task_pending)
1358 if (gp->phy_type == phy_serialink ||
1359 gp->phy_type == phy_serdes) {
1360 u32 val = readl(gp->regs + PCS_MIISTAT);
1362 if (!(val & PCS_MIISTAT_LS))
1363 val = readl(gp->regs + PCS_MIISTAT);
1365 if ((val & PCS_MIISTAT_LS) != 0) {
1366 gp->lstate = link_up;
1367 netif_carrier_on(gp->dev);
1369 (void)gem_set_link_modes(gp);
1373 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1374 /* Ok, here we got a link. If we had it due to a forced
1375 * fallback, and we were configured for autoneg, we do
1376 * retry a short autoneg pass. If you know your hub is
1377 * broken, use ethtool ;)
1379 if (gp->lstate == link_force_try && gp->want_autoneg) {
1380 gp->lstate = link_force_ret;
1381 gp->last_forced_speed = gp->phy_mii.speed;
1382 gp->timer_ticks = 5;
1383 if (netif_msg_link(gp))
1384 printk(KERN_INFO "%s: Got link after fallback, retrying"
1385 " autoneg once...\n", gp->dev->name);
1386 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1387 } else if (gp->lstate != link_up) {
1388 gp->lstate = link_up;
1389 netif_carrier_on(gp->dev);
1390 if (gp->opened && gem_set_link_modes(gp))
1394 /* If the link was previously up, we restart the
1397 if (gp->lstate == link_up) {
1398 gp->lstate = link_down;
1399 if (netif_msg_link(gp))
1400 printk(KERN_INFO "%s: Link down\n",
1402 netif_carrier_off(gp->dev);
1403 gp->reset_task_pending = 2;
1404 schedule_work(&gp->reset_task);
1406 } else if (++gp->timer_ticks > 10) {
1407 if (found_mii_phy(gp))
1408 restart_aneg = gem_mdio_link_not_up(gp);
1414 gem_begin_auto_negotiation(gp, NULL);
1418 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1420 spin_unlock_irq(&gp->lock);
1423 /* Must be invoked under gp->lock. */
1424 static void gem_clean_rings(struct gem *gp)
1426 struct gem_init_block *gb = gp->init_block;
1427 struct sk_buff *skb;
1429 dma_addr_t dma_addr;
1431 for (i = 0; i < RX_RING_SIZE; i++) {
1432 struct gem_rxd *rxd;
1435 if (gp->rx_skbs[i] != NULL) {
1436 skb = gp->rx_skbs[i];
1437 dma_addr = le64_to_cpu(rxd->buffer);
1438 pci_unmap_page(gp->pdev, dma_addr,
1439 RX_BUF_ALLOC_SIZE(gp),
1440 PCI_DMA_FROMDEVICE);
1441 dev_kfree_skb_any(skb);
1442 gp->rx_skbs[i] = NULL;
1444 rxd->status_word = 0;
1449 for (i = 0; i < TX_RING_SIZE; i++) {
1450 if (gp->tx_skbs[i] != NULL) {
1451 struct gem_txd *txd;
1454 skb = gp->tx_skbs[i];
1455 gp->tx_skbs[i] = NULL;
1457 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1458 int ent = i & (TX_RING_SIZE - 1);
1460 txd = &gb->txd[ent];
1461 dma_addr = le64_to_cpu(txd->buffer);
1462 pci_unmap_page(gp->pdev, dma_addr,
1463 le64_to_cpu(txd->control_word) &
1464 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1466 if (frag != skb_shinfo(skb)->nr_frags)
1469 dev_kfree_skb_any(skb);
1474 /* Must be invoked under gp->lock. */
1475 static void gem_init_rings(struct gem *gp)
1477 struct gem_init_block *gb = gp->init_block;
1478 struct net_device *dev = gp->dev;
1480 dma_addr_t dma_addr;
1482 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1484 gem_clean_rings(gp);
1486 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1487 (unsigned)VLAN_ETH_FRAME_LEN);
1489 for (i = 0; i < RX_RING_SIZE; i++) {
1490 struct sk_buff *skb;
1491 struct gem_rxd *rxd = &gb->rxd[i];
1493 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1496 rxd->status_word = 0;
1500 gp->rx_skbs[i] = skb;
1502 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1503 dma_addr = pci_map_page(gp->pdev,
1504 virt_to_page(skb->data),
1505 offset_in_page(skb->data),
1506 RX_BUF_ALLOC_SIZE(gp),
1507 PCI_DMA_FROMDEVICE);
1508 rxd->buffer = cpu_to_le64(dma_addr);
1510 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1511 skb_reserve(skb, RX_OFFSET);
1514 for (i = 0; i < TX_RING_SIZE; i++) {
1515 struct gem_txd *txd = &gb->txd[i];
1517 txd->control_word = 0;
1524 /* Must be invoked under gp->lock. */
1525 static void gem_init_phy(struct gem *gp)
1529 /* Revert MIF CFG setting done on stop_phy */
1530 mifcfg = readl(gp->regs + MIF_CFG);
1531 mifcfg &= ~MIF_CFG_BBMODE;
1532 writel(mifcfg, gp->regs + MIF_CFG);
1534 #ifdef CONFIG_PPC_PMAC
1535 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1538 /* Those delay sucks, the HW seem to love them though, I'll
1539 * serisouly consider breaking some locks here to be able
1540 * to schedule instead
1542 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1543 for (j = 0; j < 3; j++) {
1544 /* Some PHYs used by apple have problem getting back to us,
1545 * we _know_ it's actually at addr 0 or 1, that's a hack, but
1546 * it helps to do that reset now. I suspect some motherboards
1547 * don't wire the PHY reset line properly, thus the PHY doesn't
1548 * come back with the above pmac_call_feature.
1550 gp->mii_phy_addr = 0;
1551 phy_write(gp, MII_BMCR, BMCR_RESET);
1552 gp->mii_phy_addr = 1;
1553 phy_write(gp, MII_BMCR, BMCR_RESET);
1554 /* We should probably break some locks here and schedule... */
1557 /* On K2, we only probe the internal PHY at address 1, other
1558 * addresses tend to return garbage.
1560 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1563 for (i = 0; i < 32; i++) {
1564 gp->mii_phy_addr = i;
1565 if (phy_read(gp, MII_BMCR) != 0xffff)
1569 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1571 gp->mii_phy_addr = 0;
1576 #endif /* CONFIG_PPC_PMAC */
1578 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1579 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1582 /* Init datapath mode register. */
1583 if (gp->phy_type == phy_mii_mdio0 ||
1584 gp->phy_type == phy_mii_mdio1) {
1585 val = PCS_DMODE_MGM;
1586 } else if (gp->phy_type == phy_serialink) {
1587 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1589 val = PCS_DMODE_ESM;
1592 writel(val, gp->regs + PCS_DMODE);
1595 if (gp->phy_type == phy_mii_mdio0 ||
1596 gp->phy_type == phy_mii_mdio1) {
1597 // XXX check for errors
1598 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1601 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1602 gp->phy_mii.def->ops->init(&gp->phy_mii);
1607 /* Reset PCS unit. */
1608 val = readl(gp->regs + PCS_MIICTRL);
1609 val |= PCS_MIICTRL_RST;
1610 writeb(val, gp->regs + PCS_MIICTRL);
1613 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1619 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1622 /* Make sure PCS is disabled while changing advertisement
1625 val = readl(gp->regs + PCS_CFG);
1626 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1627 writel(val, gp->regs + PCS_CFG);
1629 /* Advertise all capabilities except assymetric
1632 val = readl(gp->regs + PCS_MIIADV);
1633 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1634 PCS_MIIADV_SP | PCS_MIIADV_AP);
1635 writel(val, gp->regs + PCS_MIIADV);
1637 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1638 * and re-enable PCS.
1640 val = readl(gp->regs + PCS_MIICTRL);
1641 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1642 val &= ~PCS_MIICTRL_WB;
1643 writel(val, gp->regs + PCS_MIICTRL);
1645 val = readl(gp->regs + PCS_CFG);
1646 val |= PCS_CFG_ENABLE;
1647 writel(val, gp->regs + PCS_CFG);
1649 /* Make sure serialink loopback is off. The meaning
1650 * of this bit is logically inverted based upon whether
1651 * you are in Serialink or SERDES mode.
1653 val = readl(gp->regs + PCS_SCTRL);
1654 if (gp->phy_type == phy_serialink)
1655 val &= ~PCS_SCTRL_LOOP;
1657 val |= PCS_SCTRL_LOOP;
1658 writel(val, gp->regs + PCS_SCTRL);
1662 /* Must be invoked under gp->lock. */
1663 static void gem_init_dma(struct gem *gp)
1665 u64 desc_dma = (u64) gp->gblock_dvma;
1668 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1669 writel(val, gp->regs + TXDMA_CFG);
1671 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1672 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1673 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1675 writel(0, gp->regs + TXDMA_KICK);
1677 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1678 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1679 writel(val, gp->regs + RXDMA_CFG);
1681 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1682 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1684 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1686 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1687 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1688 writel(val, gp->regs + RXDMA_PTHRESH);
1690 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1691 writel(((5 & RXDMA_BLANK_IPKTS) |
1692 ((8 << 12) & RXDMA_BLANK_ITIME)),
1693 gp->regs + RXDMA_BLANK);
1695 writel(((5 & RXDMA_BLANK_IPKTS) |
1696 ((4 << 12) & RXDMA_BLANK_ITIME)),
1697 gp->regs + RXDMA_BLANK);
1700 /* Must be invoked under gp->lock. */
1702 gem_setup_multicast(struct gem *gp)
1707 if ((gp->dev->flags & IFF_ALLMULTI) ||
1708 (gp->dev->mc_count > 256)) {
1709 for (i=0; i<16; i++)
1710 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1711 rxcfg |= MAC_RXCFG_HFE;
1712 } else if (gp->dev->flags & IFF_PROMISC) {
1713 rxcfg |= MAC_RXCFG_PROM;
1717 struct dev_mc_list *dmi = gp->dev->mc_list;
1720 for (i = 0; i < 16; i++)
1723 for (i = 0; i < gp->dev->mc_count; i++) {
1724 char *addrs = dmi->dmi_addr;
1731 crc = ether_crc_le(6, addrs);
1733 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1735 for (i=0; i<16; i++)
1736 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1737 rxcfg |= MAC_RXCFG_HFE;
1743 /* Must be invoked under gp->lock. */
1744 static void gem_init_mac(struct gem *gp)
1746 unsigned char *e = &gp->dev->dev_addr[0];
1748 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1750 writel(0x00, gp->regs + MAC_IPG0);
1751 writel(0x08, gp->regs + MAC_IPG1);
1752 writel(0x04, gp->regs + MAC_IPG2);
1753 writel(0x40, gp->regs + MAC_STIME);
1754 writel(0x40, gp->regs + MAC_MINFSZ);
1756 /* Ethernet payload + header + FCS + optional VLAN tag. */
1757 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1759 writel(0x07, gp->regs + MAC_PASIZE);
1760 writel(0x04, gp->regs + MAC_JAMSIZE);
1761 writel(0x10, gp->regs + MAC_ATTLIM);
1762 writel(0x8808, gp->regs + MAC_MCTYPE);
1764 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1766 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1767 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1768 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1770 writel(0, gp->regs + MAC_ADDR3);
1771 writel(0, gp->regs + MAC_ADDR4);
1772 writel(0, gp->regs + MAC_ADDR5);
1774 writel(0x0001, gp->regs + MAC_ADDR6);
1775 writel(0xc200, gp->regs + MAC_ADDR7);
1776 writel(0x0180, gp->regs + MAC_ADDR8);
1778 writel(0, gp->regs + MAC_AFILT0);
1779 writel(0, gp->regs + MAC_AFILT1);
1780 writel(0, gp->regs + MAC_AFILT2);
1781 writel(0, gp->regs + MAC_AF21MSK);
1782 writel(0, gp->regs + MAC_AF0MSK);
1784 gp->mac_rx_cfg = gem_setup_multicast(gp);
1786 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1788 writel(0, gp->regs + MAC_NCOLL);
1789 writel(0, gp->regs + MAC_FASUCC);
1790 writel(0, gp->regs + MAC_ECOLL);
1791 writel(0, gp->regs + MAC_LCOLL);
1792 writel(0, gp->regs + MAC_DTIMER);
1793 writel(0, gp->regs + MAC_PATMPS);
1794 writel(0, gp->regs + MAC_RFCTR);
1795 writel(0, gp->regs + MAC_LERR);
1796 writel(0, gp->regs + MAC_AERR);
1797 writel(0, gp->regs + MAC_FCSERR);
1798 writel(0, gp->regs + MAC_RXCVERR);
1800 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1801 * them once a link is established.
1803 writel(0, gp->regs + MAC_TXCFG);
1804 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1805 writel(0, gp->regs + MAC_MCCFG);
1806 writel(0, gp->regs + MAC_XIFCFG);
1808 /* Setup MAC interrupts. We want to get all of the interesting
1809 * counter expiration events, but we do not want to hear about
1810 * normal rx/tx as the DMA engine tells us that.
1812 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1813 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1815 /* Don't enable even the PAUSE interrupts for now, we
1816 * make no use of those events other than to record them.
1818 writel(0xffffffff, gp->regs + MAC_MCMASK);
1821 /* Must be invoked under gp->lock. */
1822 static void gem_init_pause_thresholds(struct gem *gp)
1826 /* Calculate pause thresholds. Setting the OFF threshold to the
1827 * full RX fifo size effectively disables PAUSE generation which
1828 * is what we do for 10/100 only GEMs which have FIFOs too small
1829 * to make real gains from PAUSE.
1831 if (gp->rx_fifo_sz <= (2 * 1024)) {
1832 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1834 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1835 int off = (gp->rx_fifo_sz - (max_frame * 2));
1836 int on = off - max_frame;
1838 gp->rx_pause_off = off;
1839 gp->rx_pause_on = on;
1843 /* Configure the chip "burst" DMA mode & enable some
1844 * HW bug fixes on Apple version
1847 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1848 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1849 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1850 cfg |= GREG_CFG_IBURST;
1852 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1853 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1854 writel(cfg, gp->regs + GREG_CFG);
1856 /* If Infinite Burst didn't stick, then use different
1857 * thresholds (and Apple bug fixes don't exist)
1859 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1860 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1861 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1862 writel(cfg, gp->regs + GREG_CFG);
1866 static int gem_check_invariants(struct gem *gp)
1868 struct pci_dev *pdev = gp->pdev;
1871 /* On Apple's sungem, we can't rely on registers as the chip
1872 * was been powered down by the firmware. The PHY is looked
1875 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1876 gp->phy_type = phy_mii_mdio0;
1877 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1878 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1883 mif_cfg = readl(gp->regs + MIF_CFG);
1885 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1886 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1887 /* One of the MII PHYs _must_ be present
1888 * as this chip has no gigabit PHY.
1890 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1891 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1897 /* Determine initial PHY interface type guess. MDIO1 is the
1898 * external PHY and thus takes precedence over MDIO0.
1901 if (mif_cfg & MIF_CFG_MDI1) {
1902 gp->phy_type = phy_mii_mdio1;
1903 mif_cfg |= MIF_CFG_PSELECT;
1904 writel(mif_cfg, gp->regs + MIF_CFG);
1905 } else if (mif_cfg & MIF_CFG_MDI0) {
1906 gp->phy_type = phy_mii_mdio0;
1907 mif_cfg &= ~MIF_CFG_PSELECT;
1908 writel(mif_cfg, gp->regs + MIF_CFG);
1910 gp->phy_type = phy_serialink;
1912 if (gp->phy_type == phy_mii_mdio1 ||
1913 gp->phy_type == phy_mii_mdio0) {
1916 for (i = 0; i < 32; i++) {
1917 gp->mii_phy_addr = i;
1918 if (phy_read(gp, MII_BMCR) != 0xffff)
1922 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
1923 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
1926 gp->phy_type = phy_serdes;
1930 /* Fetch the FIFO configurations now too. */
1931 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1932 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1934 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
1935 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1936 if (gp->tx_fifo_sz != (9 * 1024) ||
1937 gp->rx_fifo_sz != (20 * 1024)) {
1938 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1939 gp->tx_fifo_sz, gp->rx_fifo_sz);
1944 if (gp->tx_fifo_sz != (2 * 1024) ||
1945 gp->rx_fifo_sz != (2 * 1024)) {
1946 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1947 gp->tx_fifo_sz, gp->rx_fifo_sz);
1950 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
1957 /* Must be invoked under gp->lock. */
1958 static void gem_init_hw(struct gem *gp, int restart_link)
1960 /* On Apple's gmac, I initialize the PHY only after
1961 * setting up the chip. It appears the gigabit PHYs
1962 * don't quite like beeing talked to on the GII when
1963 * the chip is not running, I suspect it might not
1964 * be clocked at that point. --BenH
1968 gem_init_pause_thresholds(gp);
1973 /* Default aneg parameters */
1974 gp->timer_ticks = 0;
1975 gp->lstate = link_down;
1976 netif_carrier_off(gp->dev);
1978 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1979 gem_begin_auto_negotiation(gp, NULL);
1981 if (gp->lstate == link_up) {
1982 netif_carrier_on(gp->dev);
1983 gem_set_link_modes(gp);
1988 #ifdef CONFIG_PPC_PMAC
1989 /* Enable the chip's clock and make sure it's config space is
1990 * setup properly. There appear to be no need to restore the
1993 static void gem_apple_powerup(struct gem *gp)
1998 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
2002 mif_cfg = readl(gp->regs + MIF_CFG);
2003 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2004 mif_cfg |= MIF_CFG_MDI0;
2005 writel(mif_cfg, gp->regs + MIF_CFG);
2006 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2007 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2010 /* Turn off the chip's clock */
2011 static void gem_apple_powerdown(struct gem *gp)
2013 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
2016 #endif /* CONFIG_PPC_PMAC */
2018 /* Must be invoked with no lock held. */
2019 static void gem_stop_phy(struct gem *gp)
2022 unsigned long flags;
2024 /* Let the chip settle down a bit, it seems that helps
2025 * for sleep mode on some models
2029 /* Make sure we aren't polling PHY status change. We
2030 * don't currently use that feature though
2032 mifcfg = readl(gp->regs + MIF_CFG);
2033 mifcfg &= ~MIF_CFG_POLL;
2034 writel(mifcfg, gp->regs + MIF_CFG);
2036 if (gp->wake_on_lan) {
2037 /* Setup wake-on-lan */
2039 writel(0, gp->regs + MAC_RXCFG);
2040 (void)readl(gp->regs + MAC_RXCFG);
2041 /* Machine sleep will die in strange ways if we
2042 * dont wait a bit here, looks like the chip takes
2043 * some time to really shut down
2048 writel(0, gp->regs + MAC_TXCFG);
2049 writel(0, gp->regs + MAC_XIFCFG);
2050 writel(0, gp->regs + TXDMA_CFG);
2051 writel(0, gp->regs + RXDMA_CFG);
2053 if (!gp->wake_on_lan) {
2054 spin_lock_irqsave(&gp->lock, flags);
2056 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2057 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2058 spin_unlock_irqrestore(&gp->lock, flags);
2061 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2062 gp->phy_mii.def->ops->suspend(&gp->phy_mii, 0 /* wake on lan options */);
2064 if (!gp->wake_on_lan) {
2065 /* According to Apple, we must set the MDIO pins to this begnign
2066 * state or we may 1) eat more current, 2) damage some PHYs
2068 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2069 writel(0, gp->regs + MIF_BBCLK);
2070 writel(0, gp->regs + MIF_BBDATA);
2071 writel(0, gp->regs + MIF_BBOENAB);
2072 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2073 (void) readl(gp->regs + MAC_XIFCFG);
2077 /* Shut down the chip, must be called with pm_sem held. */
2078 static void gem_shutdown(struct gem *gp)
2080 /* Make us not-running to avoid timers respawning
2086 /* Stop the link timer */
2087 del_timer_sync(&gp->link_timer);
2089 /* Stop the reset task */
2090 while (gp->reset_task_pending)
2093 /* Actually stop the chip */
2094 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2097 #ifdef CONFIG_PPC_PMAC
2098 /* Power down the chip */
2099 gem_apple_powerdown(gp);
2100 #endif /* CONFIG_PPC_PMAC */
2102 unsigned long flags;
2104 spin_lock_irqsave(&gp->lock, flags);
2106 spin_unlock_irqrestore(&gp->lock, flags);
2110 static void gem_pm_task(void *data)
2112 struct gem *gp = (struct gem *) data;
2114 /* We assume if we can't lock the pm_sem, then open() was
2115 * called again (or suspend()), and we can safely ignore
2118 if (down_trylock(&gp->pm_sem))
2121 /* Driver was re-opened or already shut down */
2122 if (gp->opened || !gp->hw_running) {
2132 static void gem_pm_timer(unsigned long data)
2134 struct gem *gp = (struct gem *) data;
2136 schedule_work(&gp->pm_task);
2139 static int gem_open(struct net_device *dev)
2141 struct gem *gp = dev->priv;
2146 hw_was_up = gp->hw_running;
2148 /* Stop the PM timer/task */
2149 del_timer(&gp->pm_timer);
2150 flush_scheduled_work();
2152 /* The power-management semaphore protects the hw_running
2153 * etc. state so it is safe to do this bit without gp->lock
2155 if (!gp->hw_running) {
2156 #ifdef CONFIG_PPC_PMAC
2157 /* First, we need to bring up the chip */
2158 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2159 gem_apple_powerup(gp);
2160 gem_check_invariants(gp);
2162 #endif /* CONFIG_PPC_PMAC */
2164 /* Reset the chip */
2165 spin_lock_irq(&gp->lock);
2167 spin_unlock_irq(&gp->lock);
2172 /* We can now request the interrupt as we know it's masked
2175 if (request_irq(gp->pdev->irq, gem_interrupt,
2176 SA_SHIRQ, dev->name, (void *)dev)) {
2177 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2179 spin_lock_irq(&gp->lock);
2180 #ifdef CONFIG_PPC_PMAC
2181 if (!hw_was_up && gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2182 gem_apple_powerdown(gp);
2183 #endif /* CONFIG_PPC_PMAC */
2184 /* Fire the PM timer that will shut us down in about 10 seconds */
2185 gp->pm_timer.expires = jiffies + 10*HZ;
2186 add_timer(&gp->pm_timer);
2188 spin_unlock_irq(&gp->lock);
2193 spin_lock_irq(&gp->lock);
2195 /* Allocate & setup ring buffers */
2198 /* Init & setup chip hardware */
2199 gem_init_hw(gp, !hw_was_up);
2203 spin_unlock_irq(&gp->lock);
2210 static int gem_close(struct net_device *dev)
2212 struct gem *gp = dev->priv;
2214 /* Make sure we don't get distracted by suspend/resume */
2217 /* Stop traffic, mark us closed */
2218 spin_lock_irq(&gp->lock);
2221 writel(0xffffffff, gp->regs + GREG_IMASK);
2222 netif_stop_queue(dev);
2227 /* Get rid of rings */
2228 gem_clean_rings(gp);
2230 /* Bye, the pm timer will finish the job */
2231 free_irq(gp->pdev->irq, (void *) dev);
2233 spin_unlock_irq(&gp->lock);
2235 /* Fire the PM timer that will shut us down in about 10 seconds */
2236 gp->pm_timer.expires = jiffies + 10*HZ;
2237 add_timer(&gp->pm_timer);
2245 static int gem_suspend(struct pci_dev *pdev, u32 state)
2247 struct net_device *dev = pci_get_drvdata(pdev);
2248 struct gem *gp = dev->priv;
2250 /* We hold the PM semaphore during entire driver
2255 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2256 dev->name, gp->wake_on_lan ? "enabled" : "disabled");
2258 /* If the driver is opened, we stop the DMA */
2260 spin_lock_irq(&gp->lock);
2262 /* Stop traffic, mark us closed */
2263 netif_device_detach(dev);
2265 writel(0xffffffff, gp->regs + GREG_IMASK);
2270 /* Get rid of ring buffers */
2271 gem_clean_rings(gp);
2273 spin_unlock_irq(&gp->lock);
2275 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2276 disable_irq(gp->pdev->irq);
2279 if (gp->hw_running) {
2280 /* Kill PM timer if any */
2281 del_timer_sync(&gp->pm_timer);
2282 flush_scheduled_work();
2290 static int gem_resume(struct pci_dev *pdev)
2292 struct net_device *dev = pci_get_drvdata(pdev);
2293 struct gem *gp = dev->priv;
2295 printk(KERN_INFO "%s: resuming\n", dev->name);
2298 #ifdef CONFIG_PPC_PMAC
2299 /* First, we need to bring up the chip */
2300 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2301 gem_apple_powerup(gp);
2302 gem_check_invariants(gp);
2304 #endif /* CONFIG_PPC_PMAC */
2305 spin_lock_irq(&gp->lock);
2312 spin_unlock_irq(&gp->lock);
2314 netif_device_attach(dev);
2315 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2316 enable_irq(gp->pdev->irq);
2322 #endif /* CONFIG_PM */
2324 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2326 struct gem *gp = dev->priv;
2327 struct net_device_stats *stats = &gp->net_stats;
2329 spin_lock_irq(&gp->lock);
2331 if (gp->hw_running) {
2332 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2333 writel(0, gp->regs + MAC_FCSERR);
2335 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2336 writel(0, gp->regs + MAC_AERR);
2338 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2339 writel(0, gp->regs + MAC_LERR);
2341 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2342 stats->collisions +=
2343 (readl(gp->regs + MAC_ECOLL) +
2344 readl(gp->regs + MAC_LCOLL));
2345 writel(0, gp->regs + MAC_ECOLL);
2346 writel(0, gp->regs + MAC_LCOLL);
2349 spin_unlock_irq(&gp->lock);
2351 return &gp->net_stats;
2354 static void gem_set_multicast(struct net_device *dev)
2356 struct gem *gp = dev->priv;
2357 u32 rxcfg, rxcfg_new;
2360 if (!gp->hw_running)
2363 spin_lock_irq(&gp->lock);
2365 netif_stop_queue(dev);
2367 rxcfg = readl(gp->regs + MAC_RXCFG);
2368 rxcfg_new = gem_setup_multicast(gp);
2370 rxcfg_new |= MAC_RXCFG_SFCS;
2372 gp->mac_rx_cfg = rxcfg_new;
2374 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2375 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2381 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2384 writel(rxcfg, gp->regs + MAC_RXCFG);
2386 netif_wake_queue(dev);
2388 spin_unlock_irq(&gp->lock);
2391 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2393 struct gem *gp = dev->priv;
2395 strcpy(info->driver, DRV_NAME);
2396 strcpy(info->version, DRV_VERSION);
2397 strcpy(info->bus_info, pci_name(gp->pdev));
2400 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2402 struct gem *gp = dev->priv;
2404 if (gp->phy_type == phy_mii_mdio0 ||
2405 gp->phy_type == phy_mii_mdio1) {
2406 if (gp->phy_mii.def)
2407 cmd->supported = gp->phy_mii.def->features;
2409 cmd->supported = (SUPPORTED_10baseT_Half |
2410 SUPPORTED_10baseT_Full);
2412 /* XXX hardcoded stuff for now */
2413 cmd->port = PORT_MII;
2414 cmd->transceiver = XCVR_EXTERNAL;
2415 cmd->phy_address = 0; /* XXX fixed PHYAD */
2417 /* Return current PHY settings */
2418 spin_lock_irq(&gp->lock);
2419 cmd->autoneg = gp->want_autoneg;
2420 cmd->speed = gp->phy_mii.speed;
2421 cmd->duplex = gp->phy_mii.duplex;
2422 cmd->advertising = gp->phy_mii.advertising;
2424 /* If we started with a forced mode, we don't have a default
2425 * advertise set, we need to return something sensible so
2426 * userland can re-enable autoneg properly.
2428 if (cmd->advertising == 0)
2429 cmd->advertising = cmd->supported;
2430 spin_unlock_irq(&gp->lock);
2431 } else { // XXX PCS ?
2433 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2434 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2436 cmd->advertising = cmd->supported;
2438 cmd->duplex = cmd->port = cmd->phy_address =
2439 cmd->transceiver = cmd->autoneg = 0;
2441 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2446 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2448 struct gem *gp = dev->priv;
2450 /* Verify the settings we care about. */
2451 if (cmd->autoneg != AUTONEG_ENABLE &&
2452 cmd->autoneg != AUTONEG_DISABLE)
2455 if (cmd->autoneg == AUTONEG_ENABLE &&
2456 cmd->advertising == 0)
2459 if (cmd->autoneg == AUTONEG_DISABLE &&
2460 ((cmd->speed != SPEED_1000 &&
2461 cmd->speed != SPEED_100 &&
2462 cmd->speed != SPEED_10) ||
2463 (cmd->duplex != DUPLEX_HALF &&
2464 cmd->duplex != DUPLEX_FULL)))
2467 /* Apply settings and restart link process. */
2468 spin_lock_irq(&gp->lock);
2469 gem_begin_auto_negotiation(gp, cmd);
2470 spin_unlock_irq(&gp->lock);
2475 static int gem_nway_reset(struct net_device *dev)
2477 struct gem *gp = dev->priv;
2479 if (!gp->want_autoneg)
2482 /* Restart link process. */
2483 spin_lock_irq(&gp->lock);
2484 gem_begin_auto_negotiation(gp, NULL);
2485 spin_unlock_irq(&gp->lock);
2490 static u32 gem_get_msglevel(struct net_device *dev)
2492 struct gem *gp = dev->priv;
2493 return gp->msg_enable;
2496 static void gem_set_msglevel(struct net_device *dev, u32 value)
2498 struct gem *gp = dev->priv;
2499 gp->msg_enable = value;
2502 static struct ethtool_ops gem_ethtool_ops = {
2503 .get_drvinfo = gem_get_drvinfo,
2504 .get_link = ethtool_op_get_link,
2505 .get_settings = gem_get_settings,
2506 .set_settings = gem_set_settings,
2507 .nway_reset = gem_nway_reset,
2508 .get_msglevel = gem_get_msglevel,
2509 .set_msglevel = gem_set_msglevel,
2512 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2514 struct gem *gp = dev->priv;
2515 struct mii_ioctl_data *data = if_mii(ifr);
2516 int rc = -EOPNOTSUPP;
2518 /* Hold the PM semaphore while doing ioctl's or we may collide
2519 * with open/close and power management and oops.
2524 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2525 data->phy_id = gp->mii_phy_addr;
2526 /* Fallthrough... */
2528 case SIOCGMIIREG: /* Read MII PHY register. */
2529 if (!gp->hw_running)
2532 data->val_out = __phy_read(gp, data->phy_id & 0x1f, data->reg_num & 0x1f);
2537 case SIOCSMIIREG: /* Write MII PHY register. */
2538 if (!capable(CAP_NET_ADMIN))
2540 else if (!gp->hw_running)
2543 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2554 #if (!defined(__sparc__) && !defined(CONFIG_PPC))
2555 /* Fetch MAC address from vital product data of PCI ROM. */
2556 static void find_eth_addr_in_vpd(void *rom_base, int len, unsigned char *dev_addr)
2560 for (this_offset = 0x20; this_offset < len; this_offset++) {
2561 void *p = rom_base + this_offset;
2564 if (readb(p + 0) != 0x90 ||
2565 readb(p + 1) != 0x00 ||
2566 readb(p + 2) != 0x09 ||
2567 readb(p + 3) != 0x4e ||
2568 readb(p + 4) != 0x41 ||
2569 readb(p + 5) != 0x06)
2575 for (i = 0; i < 6; i++)
2576 dev_addr[i] = readb(p + i);
2581 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2586 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2587 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2591 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2592 pci_write_config_dword(pdev, pdev->rom_base_reg,
2593 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2595 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
2596 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
2597 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2602 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
2606 /* Sun MAC prefix then 3 random bytes. */
2610 get_random_bytes(dev_addr + 3, 3);
2613 #endif /* not Sparc and not PPC */
2615 static int __devinit gem_get_device_address(struct gem *gp)
2617 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2618 struct net_device *dev = gp->dev;
2621 #if defined(__sparc__)
2622 struct pci_dev *pdev = gp->pdev;
2623 struct pcidev_cookie *pcp = pdev->sysdata;
2627 node = pcp->prom_node;
2628 if (prom_getproplen(node, "local-mac-address") == 6)
2629 prom_getproperty(node, "local-mac-address",
2635 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2636 #elif defined(CONFIG_PPC_PMAC)
2637 unsigned char *addr;
2639 addr = get_property(gp->of_node, "local-mac-address", NULL);
2642 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2645 memcpy(dev->dev_addr, addr, 6);
2647 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2652 static int __devinit gem_init_one(struct pci_dev *pdev,
2653 const struct pci_device_id *ent)
2655 static int gem_version_printed = 0;
2656 unsigned long gemreg_base, gemreg_len;
2657 struct net_device *dev;
2659 int i, err, pci_using_dac;
2661 if (gem_version_printed++ == 0)
2662 printk(KERN_INFO "%s", version);
2664 /* Apple gmac note: during probe, the chip is powered up by
2665 * the arch code to allow the code below to work (and to let
2666 * the chip be probed on the config space. It won't stay powered
2667 * up until the interface is brought up however, so we can't rely
2668 * on register configuration done at this point.
2670 err = pci_enable_device(pdev);
2672 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2676 pci_set_master(pdev);
2678 /* Configure DMA attributes. */
2680 /* All of the GEM documentation states that 64-bit DMA addressing
2681 * is fully supported and should work just fine. However the
2682 * front end for RIO based GEMs is different and only supports
2683 * 32-bit addressing.
2685 * For now we assume the various PPC GEMs are 32-bit only as well.
2687 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2688 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2689 !pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL)) {
2692 err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
2694 printk(KERN_ERR PFX "No usable DMA configuration, "
2696 goto err_disable_device;
2701 gemreg_base = pci_resource_start(pdev, 0);
2702 gemreg_len = pci_resource_len(pdev, 0);
2704 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2705 printk(KERN_ERR PFX "Cannot find proper PCI device "
2706 "base address, aborting.\n");
2708 goto err_disable_device;
2711 dev = alloc_etherdev(sizeof(*gp));
2713 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
2715 goto err_disable_device;
2717 SET_MODULE_OWNER(dev);
2718 SET_NETDEV_DEV(dev, &pdev->dev);
2722 err = pci_request_regions(pdev, DRV_NAME);
2724 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
2726 goto err_out_free_netdev;
2730 dev->base_addr = (long) pdev;
2733 gp->msg_enable = DEFAULT_MSG;
2735 spin_lock_init(&gp->lock);
2736 init_MUTEX(&gp->pm_sem);
2738 init_timer(&gp->link_timer);
2739 gp->link_timer.function = gem_link_timer;
2740 gp->link_timer.data = (unsigned long) gp;
2742 init_timer(&gp->pm_timer);
2743 gp->pm_timer.function = gem_pm_timer;
2744 gp->pm_timer.data = (unsigned long) gp;
2746 INIT_WORK(&gp->pm_task, gem_pm_task, gp);
2747 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
2749 gp->lstate = link_down;
2750 gp->timer_ticks = 0;
2751 netif_carrier_off(dev);
2753 gp->regs = (unsigned long) ioremap(gemreg_base, gemreg_len);
2754 if (gp->regs == 0UL) {
2755 printk(KERN_ERR PFX "Cannot map device registers, "
2758 goto err_out_free_res;
2761 /* On Apple, we power the chip up now in order for check
2762 * invariants to work, but also because the firmware might
2763 * not have properly shut down the PHY.
2765 #ifdef CONFIG_PPC_PMAC
2766 gp->of_node = pci_device_to_OF_node(pdev);
2767 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2768 gem_apple_powerup(gp);
2770 spin_lock_irq(&gp->lock);
2772 spin_unlock_irq(&gp->lock);
2774 /* Fill up the mii_phy structure (even if we won't use it) */
2775 gp->phy_mii.dev = dev;
2776 gp->phy_mii.mdio_read = _phy_read;
2777 gp->phy_mii.mdio_write = _phy_write;
2779 /* By default, we start with autoneg */
2780 gp->want_autoneg = 1;
2782 if (gem_check_invariants(gp)) {
2784 goto err_out_iounmap;
2787 /* It is guaranteed that the returned buffer will be at least
2788 * PAGE_SIZE aligned.
2790 gp->init_block = (struct gem_init_block *)
2791 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2793 if (!gp->init_block) {
2794 printk(KERN_ERR PFX "Cannot allocate init block, "
2797 goto err_out_iounmap;
2800 if (gem_get_device_address(gp))
2801 goto err_out_free_consistent;
2803 dev->open = gem_open;
2804 dev->stop = gem_close;
2805 dev->hard_start_xmit = gem_start_xmit;
2806 dev->get_stats = gem_get_stats;
2807 dev->set_multicast_list = gem_set_multicast;
2808 dev->do_ioctl = gem_ioctl;
2809 dev->ethtool_ops = &gem_ethtool_ops;
2810 dev->tx_timeout = gem_tx_timeout;
2811 dev->watchdog_timeo = 5 * HZ;
2812 dev->change_mtu = gem_change_mtu;
2813 dev->irq = pdev->irq;
2816 if (register_netdev(dev)) {
2817 printk(KERN_ERR PFX "Cannot register net device, "
2820 goto err_out_free_consistent;
2823 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
2825 for (i = 0; i < 6; i++)
2826 printk("%2.2x%c", dev->dev_addr[i],
2827 i == 5 ? ' ' : ':');
2830 /* Detect & init PHY, start autoneg */
2831 spin_lock_irq(&gp->lock);
2834 gem_begin_auto_negotiation(gp, NULL);
2835 spin_unlock_irq(&gp->lock);
2837 if (gp->phy_type == phy_mii_mdio0 ||
2838 gp->phy_type == phy_mii_mdio1)
2839 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
2840 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
2842 pci_set_drvdata(pdev, dev);
2844 /* GEM can do it all... */
2845 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2847 dev->features |= NETIF_F_HIGHDMA;
2849 /* Fire the PM timer that will shut us down in about 10 seconds */
2850 gp->pm_timer.expires = jiffies + 10*HZ;
2851 add_timer(&gp->pm_timer);
2855 err_out_free_consistent:
2856 pci_free_consistent(pdev,
2857 sizeof(struct gem_init_block),
2863 /* Stop the PM timer & task */
2864 del_timer_sync(&gp->pm_timer);
2865 flush_scheduled_work();
2870 iounmap((void *) gp->regs);
2873 pci_release_regions(pdev);
2875 err_out_free_netdev:
2878 pci_disable_device(pdev);
2883 static void __devexit gem_remove_one(struct pci_dev *pdev)
2885 struct net_device *dev = pci_get_drvdata(pdev);
2888 struct gem *gp = dev->priv;
2890 unregister_netdev(dev);
2893 /* Stop the PM timer & task */
2894 del_timer_sync(&gp->pm_timer);
2895 flush_scheduled_work();
2900 pci_free_consistent(pdev,
2901 sizeof(struct gem_init_block),
2904 iounmap((void *) gp->regs);
2905 pci_release_regions(pdev);
2908 pci_set_drvdata(pdev, NULL);
2912 static struct pci_driver gem_driver = {
2913 .name = GEM_MODULE_NAME,
2914 .id_table = gem_pci_tbl,
2915 .probe = gem_init_one,
2916 .remove = __devexit_p(gem_remove_one),
2918 .suspend = gem_suspend,
2919 .resume = gem_resume,
2920 #endif /* CONFIG_PM */
2923 static int __init gem_init(void)
2925 return pci_module_init(&gem_driver);
2928 static void __exit gem_cleanup(void)
2930 pci_unregister_driver(&gem_driver);
2933 module_init(gem_init);
2934 module_exit(gem_cleanup);