1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
16 #if !defined(PCI_DEVICE_ID_TIGON3_5704S_2)
17 #define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
20 #if !defined(PCI_DEVICE_ID_TIGON3_5705F)
21 #define PCI_DEVICE_ID_TIGON3_5705F 0x166e
24 #if !defined(PCI_DEVICE_ID_TIGON3_5720)
25 #define PCI_DEVICE_ID_TIGON3_5720 0x1658
28 #if !defined(PCI_DEVICE_ID_TIGON3_5721)
29 #define PCI_DEVICE_ID_TIGON3_5721 0x1659
32 #if !defined(PCI_DEVICE_ID_TIGON3_5750)
33 #define PCI_DEVICE_ID_TIGON3_5750 0x1676
36 #if !defined(PCI_DEVICE_ID_TIGON3_5751)
37 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
40 #if !defined(PCI_DEVICE_ID_TIGON3_5750M)
41 #define PCI_DEVICE_ID_TIGON3_5750M 0x167c
44 #if !defined(PCI_DEVICE_ID_TIGON3_5751M)
45 #define PCI_DEVICE_ID_TIGON3_5751M 0x167d
48 #if !defined(PCI_DEVICE_ID_TIGON3_5751F)
49 #define PCI_DEVICE_ID_TIGON3_5751F 0x167e
52 #if !defined(PCI_DEVICE_ID_TIGON3_5789)
53 #define PCI_DEVICE_ID_TIGON3_5789 0x169d
56 #if !defined(PCI_DEVICE_ID_TIGON3_5753)
57 #define PCI_DEVICE_ID_TIGON3_5753 0x16f7
60 #if !defined(PCI_DEVICE_ID_TIGON3_5753M)
61 #define PCI_DEVICE_ID_TIGON3_5753M 0x16fd
64 #if !defined(PCI_DEVICE_ID_TIGON3_5753F)
65 #define PCI_DEVICE_ID_TIGON3_5753F 0x16fe
68 #if !defined(PCI_DEVICE_ID_TIGON3_5781)
69 #define PCI_DEVICE_ID_TIGON3_5781 0x16dd
72 #if !defined(PCI_DEVICE_ID_TIGON3_5752)
73 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
76 #if !defined(PCI_DEVICE_ID_TIGON3_5752M)
77 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
80 #if !defined(PCI_DEVICE_ID_TIGON3_5714)
81 #define PCI_DEVICE_ID_TIGON3_5714 0x1668
84 #if !defined(PCI_DEVICE_ID_TIGON3_5714S)
85 #define PCI_DEVICE_ID_TIGON3_5714S 0x1669
88 #if !defined(PCI_DEVICE_ID_TIGON3_5780)
89 #define PCI_DEVICE_ID_TIGON3_5780 0x166a
92 #if !defined(PCI_DEVICE_ID_TIGON3_5780S)
93 #define PCI_DEVICE_ID_TIGON3_5780S 0x166b
96 #if !defined(PCI_DEVICE_ID_TIGON3_5715)
97 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
100 #if !defined(PCI_DEVICE_ID_TIGON3_5715S)
101 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
104 #if !defined(PCI_DEVICE_ID_TIGON3_5754)
105 #define PCI_DEVICE_ID_TIGON3_5754 0x167a
108 #if !defined(PCI_DEVICE_ID_TIGON3_5754M)
109 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
112 #if !defined(PCI_DEVICE_ID_TIGON3_5755)
113 #define PCI_DEVICE_ID_TIGON3_5755 0x167b
116 #if !defined(PCI_DEVICE_ID_TIGON3_5755M)
117 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
120 #if !defined(PCI_DEVICE_ID_TIGON3_5786)
121 #define PCI_DEVICE_ID_TIGON3_5786 0x169a
124 #if !defined(PCI_DEVICE_ID_TIGON3_5787M)
125 #define PCI_DEVICE_ID_TIGON3_5787M 0x1693
128 #if !defined(PCI_DEVICE_ID_TIGON3_5787)
129 #define PCI_DEVICE_ID_TIGON3_5787 0x169b
132 #if !defined(PCI_DEVICE_ID_APPLE_TIGON3)
133 #define PCI_DEVICE_ID_APPLE_TIGON3 0x1645
136 #if !defined(PCI_DEVICE_ID_APPLE_UNI_N_PCI15)
137 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e
140 #if !defined(PCI_DEVICE_ID_VIA_8385_0)
141 #define PCI_DEVICE_ID_VIA_8385_0 0x3188
144 #if !defined(PCI_DEVICE_ID_AMD_8131_BRIDGE)
145 #define PCI_DEVICE_ID_AMD_8131_BRIDGE 0x7450
148 #if !defined(PCI_DEVICE_ID_SERVERWORKS_EPB)
149 #define PCI_DEVICE_ID_SERVERWORKS_EPB 0x0103
152 #if !defined(PCI_VPD_ADDR)
153 #define PCI_VPD_ADDR 2
154 #define PCI_VPD_DATA 4
158 #define NETDEV_TX_OK 0
161 #ifndef NETDEV_TX_BUSY
162 #define NETDEV_TX_BUSY 1
165 #ifndef NETDEV_TX_LOCKED
166 #define NETDEV_TX_LOCKED -1
171 #define gso_size tso_size
174 #define NETIF_F_TSO6 0
178 #ifndef DMA_64BIT_MASK
179 #define DMA_64BIT_MASK ((u64) 0xffffffffffffffffULL)
180 #define DMA_32BIT_MASK ((u64) 0x00000000ffffffffULL)
183 #ifndef DMA_40BIT_MASK
184 #define DMA_40BIT_MASK ((u64) 0x000000ffffffffffULL)
192 typedef u32 pm_message_t;
193 typedef u32 pci_power_t;
205 typedef void irqreturn_t;
206 #define IRQ_RETVAL(x)
211 #define IRQF_SHARED SA_SHIRQ
214 #ifndef IRQF_SAMPLE_RANDOM
215 #define IRQF_SAMPLE_RANDOM SA_SAMPLE_RANDOM
218 #if (LINUX_VERSION_CODE < 0x020604)
219 #define MODULE_VERSION(version)
222 #if (LINUX_VERSION_CODE <= 0x020600)
223 #define schedule_work(x) schedule_task(x)
224 #define work_struct tq_struct
225 #define INIT_WORK(x, y, z) INIT_TQUEUE(x, y, z)
228 #ifndef ADVERTISE_PAUSE
229 #define ADVERTISE_PAUSE_CAP 0x0400
231 #ifndef ADVERTISE_PAUSE_ASYM
232 #define ADVERTISE_PAUSE_ASYM 0x0800
235 #define LPA_PAUSE_CAP 0x0400
237 #ifndef LPA_PAUSE_ASYM
238 #define LPA_PAUSE_ASYM 0x0800
241 #define MII_CTRL1000 0x9
243 #ifndef BMCR_SPEED1000
244 #define BMCR_SPEED1000 0x40
246 #ifndef ADVERTISE_1000XFULL
247 #define ADVERTISE_1000XFULL 0x20
248 #define ADVERTISE_1000XHALF 0x40
249 #define ADVERTISE_1000XPAUSE 0x80
250 #define ADVERTISE_1000XPSE_ASYM 0x100
251 #define LPA_1000XFULL 0x20
252 #define LPA_1000XHALF 0x40
253 #define LPA_1000XPAUSE 0x80
254 #define LPA_1000XPAUSE_ASYM 0x100
257 #if (LINUX_VERSION_CODE < 0x020605)
258 #define pci_dma_sync_single_for_cpu(pdev, map, len, dir) \
259 pci_dma_sync_single(pdev, map, len, dir)
261 #define pci_dma_sync_single_for_device(pdev, map, len, dir)
264 #if (LINUX_VERSION_CODE < 0x020600)
265 #define pci_get_device(x, y, z) pci_find_device(x, y, z)
266 #define pci_get_slot(x, y) pci_find_slot((x)->number, y)
267 #define pci_dev_put(x)
270 #if (LINUX_VERSION_CODE < 0x020547)
271 #define pci_set_consistent_dma_mask(pdev, mask) (0)
274 #ifndef PCI_CAP_ID_EXP
275 #define PCI_CAP_ID_EXP 0x10
278 #if (LINUX_VERSION_CODE < 0x020612)
279 static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev,
282 struct sk_buff *skb = dev_alloc_skb(length);
288 static inline void netif_tx_lock(struct net_device *dev)
290 spin_lock(&dev->xmit_lock);
291 dev->xmit_lock_owner = smp_processor_id();
294 static inline void netif_tx_unlock(struct net_device *dev)
296 dev->xmit_lock_owner = -1;
297 spin_unlock(&dev->xmit_lock);
302 #if !defined(HAVE_NETDEV_PRIV) && (LINUX_VERSION_CODE != 0x020603) && (LINUX_VERSION_CODE != 0x020604) && (LINUX_VERSION_CODE != 0x20605)
303 static inline void *netdev_priv(struct net_device *dev)
310 static inline void netif_poll_disable(struct net_device *dev)
312 while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) {
314 current->state = TASK_INTERRUPTIBLE;
319 static inline void netif_poll_enable(struct net_device *dev)
321 clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
324 static inline void netif_tx_disable(struct net_device *dev)
326 spin_lock_bh(&dev->xmit_lock);
327 netif_stop_queue(dev);
328 spin_unlock_bh(&dev->xmit_lock);
333 #if (LINUX_VERSION_CODE < 0x2060c)
334 static inline int skb_header_cloned(struct sk_buff *skb) { return 0; }
337 #if (LINUX_VERSION_CODE >= 0x20418) && (LINUX_VERSION_CODE < 0x2060c)
338 static int tg3_set_tx_hw_csum(struct net_device *dev, u32 data)
341 dev->features |= NETIF_F_HW_CSUM;
343 dev->features &= ~NETIF_F_HW_CSUM;
350 #define NETIF_F_LLTX 0
353 #define TG3_64BIT_REG_HIGH 0x00UL
354 #define TG3_64BIT_REG_LOW 0x04UL
356 /* Descriptor block info. */
357 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
358 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
359 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
360 #define BDINFO_FLAGS_DISABLED 0x00000002
361 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
362 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
363 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
364 #define TG3_BDINFO_SIZE 0x10UL
366 #define RX_COPY_THRESHOLD 256
368 #define RX_STD_MAX_SIZE 1536
369 #define RX_STD_MAX_SIZE_5705 512
370 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
372 /* First 256 bytes are a mirror of PCI config space. */
373 #define TG3PCI_VENDOR 0x00000000
374 #define TG3PCI_VENDOR_BROADCOM 0x14e4
375 #define TG3PCI_DEVICE 0x00000002
376 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
377 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
378 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
379 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
380 #define TG3PCI_COMMAND 0x00000004
381 #define TG3PCI_STATUS 0x00000006
382 #define TG3PCI_CCREVID 0x00000008
383 #define TG3PCI_CACHELINESZ 0x0000000c
384 #define TG3PCI_LATTIMER 0x0000000d
385 #define TG3PCI_HEADERTYPE 0x0000000e
386 #define TG3PCI_BIST 0x0000000f
387 #define TG3PCI_BASE0_LOW 0x00000010
388 #define TG3PCI_BASE0_HIGH 0x00000014
389 /* 0x18 --> 0x2c unused */
390 #define TG3PCI_SUBSYSVENID 0x0000002c
391 #define TG3PCI_SUBSYSID 0x0000002e
392 #define TG3PCI_ROMADDR 0x00000030
393 #define TG3PCI_CAPLIST 0x00000034
394 /* 0x35 --> 0x3c unused */
395 #define TG3PCI_IRQ_LINE 0x0000003c
396 #define TG3PCI_IRQ_PIN 0x0000003d
397 #define TG3PCI_MIN_GNT 0x0000003e
398 #define TG3PCI_MAX_LAT 0x0000003f
399 #define TG3PCI_X_CAPS 0x00000040
400 #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
401 #define PCIX_CAPS_SPLIT_MASK 0x00700000
402 #define PCIX_CAPS_SPLIT_SHIFT 20
403 #define PCIX_CAPS_BURST_MASK 0x000c0000
404 #define PCIX_CAPS_BURST_SHIFT 18
405 #define PCIX_CAPS_MAX_BURST_CPIOB 2
406 #define TG3PCI_PM_CAP_PTR 0x00000041
407 #define TG3PCI_X_COMMAND 0x00000042
408 #define TG3PCI_X_STATUS 0x00000044
409 #define TG3PCI_PM_CAP_ID 0x00000048
410 #define TG3PCI_VPD_CAP_PTR 0x00000049
411 #define TG3PCI_PM_CAPS 0x0000004a
412 #define TG3PCI_PM_CTRL_STAT 0x0000004c
413 #define TG3PCI_BR_SUPP_EXT 0x0000004e
414 #define TG3PCI_PM_DATA 0x0000004f
415 #define TG3PCI_VPD_CAP_ID 0x00000050
416 #define TG3PCI_MSI_CAP_PTR 0x00000051
417 #define TG3PCI_VPD_ADDR_FLAG 0x00000052
418 #define VPD_ADDR_FLAG_WRITE 0x00008000
419 #define TG3PCI_VPD_DATA 0x00000054
420 #define TG3PCI_MSI_CAP_ID 0x00000058
421 #define TG3PCI_NXT_CAP_PTR 0x00000059
422 #define TG3PCI_MSI_CTRL 0x0000005a
423 #define TG3PCI_MSI_ADDR_LOW 0x0000005c
424 #define TG3PCI_MSI_ADDR_HIGH 0x00000060
425 #define TG3PCI_MSI_DATA 0x00000064
426 /* 0x66 --> 0x68 unused */
427 #define TG3PCI_MISC_HOST_CTRL 0x00000068
428 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
429 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
430 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
431 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
432 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
433 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
434 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
435 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
436 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
437 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
438 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
439 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
440 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
441 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
442 MISC_HOST_CTRL_CHIPREV_SHIFT)
443 #define CHIPREV_ID_5700_A0 0x7000
444 #define CHIPREV_ID_5700_A1 0x7001
445 #define CHIPREV_ID_5700_B0 0x7100
446 #define CHIPREV_ID_5700_B1 0x7101
447 #define CHIPREV_ID_5700_B3 0x7102
448 #define CHIPREV_ID_5700_ALTIMA 0x7104
449 #define CHIPREV_ID_5700_C0 0x7200
450 #define CHIPREV_ID_5701_A0 0x0000
451 #define CHIPREV_ID_5701_B0 0x0100
452 #define CHIPREV_ID_5701_B2 0x0102
453 #define CHIPREV_ID_5701_B5 0x0105
454 #define CHIPREV_ID_5703_A0 0x1000
455 #define CHIPREV_ID_5703_A1 0x1001
456 #define CHIPREV_ID_5703_A2 0x1002
457 #define CHIPREV_ID_5703_A3 0x1003
458 #define CHIPREV_ID_5704_A0 0x2000
459 #define CHIPREV_ID_5704_A1 0x2001
460 #define CHIPREV_ID_5704_A2 0x2002
461 #define CHIPREV_ID_5704_A3 0x2003
462 #define CHIPREV_ID_5705_A0 0x3000
463 #define CHIPREV_ID_5705_A1 0x3001
464 #define CHIPREV_ID_5705_A2 0x3002
465 #define CHIPREV_ID_5705_A3 0x3003
466 #define CHIPREV_ID_5750_A0 0x4000
467 #define CHIPREV_ID_5750_A1 0x4001
468 #define CHIPREV_ID_5750_A3 0x4003
469 #define CHIPREV_ID_5750_C2 0x4202
470 #define CHIPREV_ID_5752_A0_HW 0x5000
471 #define CHIPREV_ID_5752_A0 0x6000
472 #define CHIPREV_ID_5752_A1 0x6001
473 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
474 #define ASIC_REV_5700 0x07
475 #define ASIC_REV_5701 0x00
476 #define ASIC_REV_5703 0x01
477 #define ASIC_REV_5704 0x02
478 #define ASIC_REV_5705 0x03
479 #define ASIC_REV_5750 0x04
480 #define ASIC_REV_5752 0x06
481 #define ASIC_REV_5780 0x08
482 #define ASIC_REV_5714 0x09
483 #define ASIC_REV_5755 0x0a
484 #define ASIC_REV_5787 0x0b
485 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
486 #define CHIPREV_5700_AX 0x70
487 #define CHIPREV_5700_BX 0x71
488 #define CHIPREV_5700_CX 0x72
489 #define CHIPREV_5701_AX 0x00
490 #define CHIPREV_5703_AX 0x10
491 #define CHIPREV_5704_AX 0x20
492 #define CHIPREV_5704_BX 0x21
493 #define CHIPREV_5750_AX 0x40
494 #define CHIPREV_5750_BX 0x41
495 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
496 #define METAL_REV_A0 0x00
497 #define METAL_REV_A1 0x01
498 #define METAL_REV_B0 0x00
499 #define METAL_REV_B1 0x01
500 #define METAL_REV_B2 0x02
501 #define TG3PCI_DMA_RW_CTRL 0x0000006c
502 #define DMA_RWCTRL_MIN_DMA 0x000000ff
503 #define DMA_RWCTRL_MIN_DMA_SHIFT 0
504 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
505 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
506 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
507 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
508 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
509 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
510 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
511 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
512 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
513 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
514 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
515 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
516 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
517 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
518 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
519 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
520 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
521 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
522 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
523 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
524 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
525 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
526 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
527 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
528 #define DMA_RWCTRL_ONE_DMA 0x00004000
529 #define DMA_RWCTRL_READ_WATER 0x00070000
530 #define DMA_RWCTRL_READ_WATER_SHIFT 16
531 #define DMA_RWCTRL_WRITE_WATER 0x00380000
532 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
533 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
534 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
535 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
536 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
537 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
538 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
539 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
540 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
541 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
542 #define TG3PCI_PCISTATE 0x00000070
543 #define PCISTATE_FORCE_RESET 0x00000001
544 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
545 #define PCISTATE_CONV_PCI_MODE 0x00000004
546 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
547 #define PCISTATE_BUS_32BIT 0x00000010
548 #define PCISTATE_ROM_ENABLE 0x00000020
549 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
550 #define PCISTATE_FLAT_VIEW 0x00000100
551 #define PCISTATE_RETRY_SAME_DMA 0x00002000
552 #define TG3PCI_CLOCK_CTRL 0x00000074
553 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
554 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
555 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
556 #define CLOCK_CTRL_ALTCLK 0x00001000
557 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
558 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
559 #define CLOCK_CTRL_625_CORE 0x00100000
560 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
561 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
562 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
563 #define TG3PCI_REG_BASE_ADDR 0x00000078
564 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
565 #define TG3PCI_REG_DATA 0x00000080
566 #define TG3PCI_MEM_WIN_DATA 0x00000084
567 #define TG3PCI_MODE_CTRL 0x00000088
568 #define TG3PCI_MISC_CFG 0x0000008c
569 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
570 /* 0x94 --> 0x98 unused */
571 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
572 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
573 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
574 /* 0xb0 --> 0xb8 unused */
575 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
576 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
577 #define DUAL_MAC_CTRL_ID 0x00000004
578 /* 0xbc --> 0x100 unused */
580 /* 0x100 --> 0x200 unused */
582 /* Mailbox registers */
583 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
584 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
585 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
586 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
587 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
588 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
589 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
590 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
591 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
592 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
593 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
594 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
595 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
596 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
597 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
598 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
599 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
600 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
601 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
602 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
603 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
604 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
605 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
606 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
607 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
608 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
609 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
610 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
611 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
612 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
613 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
614 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
615 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
616 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
617 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
618 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
619 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
620 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
621 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
622 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
623 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
624 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
625 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
626 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
627 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
628 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
629 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
630 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
631 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
632 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
633 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
634 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
635 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
636 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
637 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
638 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
639 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
640 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
641 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
642 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
643 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
644 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
645 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
646 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
648 /* MAC control registers */
649 #define MAC_MODE 0x00000400
650 #define MAC_MODE_RESET 0x00000001
651 #define MAC_MODE_HALF_DUPLEX 0x00000002
652 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
653 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
654 #define MAC_MODE_PORT_MODE_GMII 0x00000008
655 #define MAC_MODE_PORT_MODE_MII 0x00000004
656 #define MAC_MODE_PORT_MODE_NONE 0x00000000
657 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
658 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
659 #define MAC_MODE_TX_BURSTING 0x00000100
660 #define MAC_MODE_MAX_DEFER 0x00000200
661 #define MAC_MODE_LINK_POLARITY 0x00000400
662 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
663 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
664 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
665 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
666 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
667 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
668 #define MAC_MODE_SEND_CONFIGS 0x00020000
669 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
670 #define MAC_MODE_ACPI_ENABLE 0x00080000
671 #define MAC_MODE_MIP_ENABLE 0x00100000
672 #define MAC_MODE_TDE_ENABLE 0x00200000
673 #define MAC_MODE_RDE_ENABLE 0x00400000
674 #define MAC_MODE_FHDE_ENABLE 0x00800000
675 #define MAC_STATUS 0x00000404
676 #define MAC_STATUS_PCS_SYNCED 0x00000001
677 #define MAC_STATUS_SIGNAL_DET 0x00000002
678 #define MAC_STATUS_RCVD_CFG 0x00000004
679 #define MAC_STATUS_CFG_CHANGED 0x00000008
680 #define MAC_STATUS_SYNC_CHANGED 0x00000010
681 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
682 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
683 #define MAC_STATUS_MI_COMPLETION 0x00400000
684 #define MAC_STATUS_MI_INTERRUPT 0x00800000
685 #define MAC_STATUS_AP_ERROR 0x01000000
686 #define MAC_STATUS_ODI_ERROR 0x02000000
687 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
688 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
689 #define MAC_EVENT 0x00000408
690 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
691 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
692 #define MAC_EVENT_MI_COMPLETION 0x00400000
693 #define MAC_EVENT_MI_INTERRUPT 0x00800000
694 #define MAC_EVENT_AP_ERROR 0x01000000
695 #define MAC_EVENT_ODI_ERROR 0x02000000
696 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
697 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
698 #define MAC_LED_CTRL 0x0000040c
699 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
700 #define LED_CTRL_1000MBPS_ON 0x00000002
701 #define LED_CTRL_100MBPS_ON 0x00000004
702 #define LED_CTRL_10MBPS_ON 0x00000008
703 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
704 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
705 #define LED_CTRL_TRAFFIC_LED 0x00000040
706 #define LED_CTRL_1000MBPS_STATUS 0x00000080
707 #define LED_CTRL_100MBPS_STATUS 0x00000100
708 #define LED_CTRL_10MBPS_STATUS 0x00000200
709 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
710 #define LED_CTRL_MODE_MAC 0x00000000
711 #define LED_CTRL_MODE_PHY_1 0x00000800
712 #define LED_CTRL_MODE_PHY_2 0x00001000
713 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
714 #define LED_CTRL_MODE_SHARED 0x00004000
715 #define LED_CTRL_MODE_COMBO 0x00008000
716 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
717 #define LED_CTRL_BLINK_RATE_SHIFT 19
718 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
719 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
720 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
721 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
722 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
723 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
724 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
725 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
726 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
727 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
728 #define MAC_ACPI_MBUF_PTR 0x00000430
729 #define MAC_ACPI_LEN_OFFSET 0x00000434
730 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
731 #define ACPI_LENOFF_LEN_SHIFT 0
732 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
733 #define ACPI_LENOFF_OFF_SHIFT 16
734 #define MAC_TX_BACKOFF_SEED 0x00000438
735 #define TX_BACKOFF_SEED_MASK 0x000003ff
736 #define MAC_RX_MTU_SIZE 0x0000043c
737 #define RX_MTU_SIZE_MASK 0x0000ffff
738 #define MAC_PCS_TEST 0x00000440
739 #define PCS_TEST_PATTERN_MASK 0x000fffff
740 #define PCS_TEST_PATTERN_SHIFT 0
741 #define PCS_TEST_ENABLE 0x00100000
742 #define MAC_TX_AUTO_NEG 0x00000444
743 #define TX_AUTO_NEG_MASK 0x0000ffff
744 #define TX_AUTO_NEG_SHIFT 0
745 #define MAC_RX_AUTO_NEG 0x00000448
746 #define RX_AUTO_NEG_MASK 0x0000ffff
747 #define RX_AUTO_NEG_SHIFT 0
748 #define MAC_MI_COM 0x0000044c
749 #define MI_COM_CMD_MASK 0x0c000000
750 #define MI_COM_CMD_WRITE 0x04000000
751 #define MI_COM_CMD_READ 0x08000000
752 #define MI_COM_READ_FAILED 0x10000000
753 #define MI_COM_START 0x20000000
754 #define MI_COM_BUSY 0x20000000
755 #define MI_COM_PHY_ADDR_MASK 0x03e00000
756 #define MI_COM_PHY_ADDR_SHIFT 21
757 #define MI_COM_REG_ADDR_MASK 0x001f0000
758 #define MI_COM_REG_ADDR_SHIFT 16
759 #define MI_COM_DATA_MASK 0x0000ffff
760 #define MAC_MI_STAT 0x00000450
761 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
762 #define MAC_MI_MODE 0x00000454
763 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
764 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
765 #define MAC_MI_MODE_AUTO_POLL 0x00000010
766 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
767 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
768 #define MAC_AUTO_POLL_STATUS 0x00000458
769 #define MAC_AUTO_POLL_ERROR 0x00000001
770 #define MAC_TX_MODE 0x0000045c
771 #define TX_MODE_RESET 0x00000001
772 #define TX_MODE_ENABLE 0x00000002
773 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
774 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
775 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
776 #define MAC_TX_STATUS 0x00000460
777 #define TX_STATUS_XOFFED 0x00000001
778 #define TX_STATUS_SENT_XOFF 0x00000002
779 #define TX_STATUS_SENT_XON 0x00000004
780 #define TX_STATUS_LINK_UP 0x00000008
781 #define TX_STATUS_ODI_UNDERRUN 0x00000010
782 #define TX_STATUS_ODI_OVERRUN 0x00000020
783 #define MAC_TX_LENGTHS 0x00000464
784 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
785 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
786 #define TX_LENGTHS_IPG_MASK 0x00000f00
787 #define TX_LENGTHS_IPG_SHIFT 8
788 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
789 #define TX_LENGTHS_IPG_CRS_SHIFT 12
790 #define MAC_RX_MODE 0x00000468
791 #define RX_MODE_RESET 0x00000001
792 #define RX_MODE_ENABLE 0x00000002
793 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
794 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
795 #define RX_MODE_KEEP_PAUSE 0x00000010
796 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
797 #define RX_MODE_ACCEPT_RUNTS 0x00000040
798 #define RX_MODE_LEN_CHECK 0x00000080
799 #define RX_MODE_PROMISC 0x00000100
800 #define RX_MODE_NO_CRC_CHECK 0x00000200
801 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
802 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
803 #define MAC_RX_STATUS 0x0000046c
804 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
805 #define RX_STATUS_XOFF_RCVD 0x00000002
806 #define RX_STATUS_XON_RCVD 0x00000004
807 #define MAC_HASH_REG_0 0x00000470
808 #define MAC_HASH_REG_1 0x00000474
809 #define MAC_HASH_REG_2 0x00000478
810 #define MAC_HASH_REG_3 0x0000047c
811 #define MAC_RCV_RULE_0 0x00000480
812 #define MAC_RCV_VALUE_0 0x00000484
813 #define MAC_RCV_RULE_1 0x00000488
814 #define MAC_RCV_VALUE_1 0x0000048c
815 #define MAC_RCV_RULE_2 0x00000490
816 #define MAC_RCV_VALUE_2 0x00000494
817 #define MAC_RCV_RULE_3 0x00000498
818 #define MAC_RCV_VALUE_3 0x0000049c
819 #define MAC_RCV_RULE_4 0x000004a0
820 #define MAC_RCV_VALUE_4 0x000004a4
821 #define MAC_RCV_RULE_5 0x000004a8
822 #define MAC_RCV_VALUE_5 0x000004ac
823 #define MAC_RCV_RULE_6 0x000004b0
824 #define MAC_RCV_VALUE_6 0x000004b4
825 #define MAC_RCV_RULE_7 0x000004b8
826 #define MAC_RCV_VALUE_7 0x000004bc
827 #define MAC_RCV_RULE_8 0x000004c0
828 #define MAC_RCV_VALUE_8 0x000004c4
829 #define MAC_RCV_RULE_9 0x000004c8
830 #define MAC_RCV_VALUE_9 0x000004cc
831 #define MAC_RCV_RULE_10 0x000004d0
832 #define MAC_RCV_VALUE_10 0x000004d4
833 #define MAC_RCV_RULE_11 0x000004d8
834 #define MAC_RCV_VALUE_11 0x000004dc
835 #define MAC_RCV_RULE_12 0x000004e0
836 #define MAC_RCV_VALUE_12 0x000004e4
837 #define MAC_RCV_RULE_13 0x000004e8
838 #define MAC_RCV_VALUE_13 0x000004ec
839 #define MAC_RCV_RULE_14 0x000004f0
840 #define MAC_RCV_VALUE_14 0x000004f4
841 #define MAC_RCV_RULE_15 0x000004f8
842 #define MAC_RCV_VALUE_15 0x000004fc
843 #define RCV_RULE_DISABLE_MASK 0x7fffffff
844 #define MAC_RCV_RULE_CFG 0x00000500
845 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
846 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
847 /* 0x508 --> 0x520 unused */
848 #define MAC_HASHREGU_0 0x00000520
849 #define MAC_HASHREGU_1 0x00000524
850 #define MAC_HASHREGU_2 0x00000528
851 #define MAC_HASHREGU_3 0x0000052c
852 #define MAC_EXTADDR_0_HIGH 0x00000530
853 #define MAC_EXTADDR_0_LOW 0x00000534
854 #define MAC_EXTADDR_1_HIGH 0x00000538
855 #define MAC_EXTADDR_1_LOW 0x0000053c
856 #define MAC_EXTADDR_2_HIGH 0x00000540
857 #define MAC_EXTADDR_2_LOW 0x00000544
858 #define MAC_EXTADDR_3_HIGH 0x00000548
859 #define MAC_EXTADDR_3_LOW 0x0000054c
860 #define MAC_EXTADDR_4_HIGH 0x00000550
861 #define MAC_EXTADDR_4_LOW 0x00000554
862 #define MAC_EXTADDR_5_HIGH 0x00000558
863 #define MAC_EXTADDR_5_LOW 0x0000055c
864 #define MAC_EXTADDR_6_HIGH 0x00000560
865 #define MAC_EXTADDR_6_LOW 0x00000564
866 #define MAC_EXTADDR_7_HIGH 0x00000568
867 #define MAC_EXTADDR_7_LOW 0x0000056c
868 #define MAC_EXTADDR_8_HIGH 0x00000570
869 #define MAC_EXTADDR_8_LOW 0x00000574
870 #define MAC_EXTADDR_9_HIGH 0x00000578
871 #define MAC_EXTADDR_9_LOW 0x0000057c
872 #define MAC_EXTADDR_10_HIGH 0x00000580
873 #define MAC_EXTADDR_10_LOW 0x00000584
874 #define MAC_EXTADDR_11_HIGH 0x00000588
875 #define MAC_EXTADDR_11_LOW 0x0000058c
876 #define MAC_SERDES_CFG 0x00000590
877 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
878 #define MAC_SERDES_STAT 0x00000594
879 /* 0x598 --> 0x5b0 unused */
880 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
881 #define SERDES_RX_SIG_DETECT 0x00000400
882 #define SG_DIG_CTRL 0x000005b0
883 #define SG_DIG_USING_HW_AUTONEG 0x80000000
884 #define SG_DIG_SOFT_RESET 0x40000000
885 #define SG_DIG_DISABLE_LINKRDY 0x20000000
886 #define SG_DIG_CRC16_CLEAR_N 0x01000000
887 #define SG_DIG_EN10B 0x00800000
888 #define SG_DIG_CLEAR_STATUS 0x00400000
889 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
890 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
891 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
892 #define SG_DIG_SPEED_STATUS_SHIFT 18
893 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
894 #define SG_DIG_RESTART_AUTONEG 0x00010000
895 #define SG_DIG_FIBER_MODE 0x00008000
896 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
897 #define SG_DIG_PAUSE_MASK 0x00001800
898 #define SG_DIG_GBIC_ENABLE 0x00000400
899 #define SG_DIG_CHECK_END_ENABLE 0x00000200
900 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
901 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
902 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
903 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
904 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
905 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
906 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
907 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
908 #define SG_DIG_LOOPBACK 0x00000001
909 #define SG_DIG_STATUS 0x000005b4
910 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
911 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
912 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
913 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
914 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
915 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
916 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
917 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
918 #define SG_DIG_COMMA_DETECTOR 0x00000008
919 #define SG_DIG_MAC_ACK_STATUS 0x00000004
920 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
921 #define SG_DIG_AUTONEG_ERROR 0x00000001
922 /* 0x5b8 --> 0x600 unused */
923 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
924 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
925 /* 0x624 --> 0x800 unused */
926 #define MAC_TX_STATS_OCTETS 0x00000800
927 #define MAC_TX_STATS_RESV1 0x00000804
928 #define MAC_TX_STATS_COLLISIONS 0x00000808
929 #define MAC_TX_STATS_XON_SENT 0x0000080c
930 #define MAC_TX_STATS_XOFF_SENT 0x00000810
931 #define MAC_TX_STATS_RESV2 0x00000814
932 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
933 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
934 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
935 #define MAC_TX_STATS_DEFERRED 0x00000824
936 #define MAC_TX_STATS_RESV3 0x00000828
937 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
938 #define MAC_TX_STATS_LATE_COL 0x00000830
939 #define MAC_TX_STATS_RESV4_1 0x00000834
940 #define MAC_TX_STATS_RESV4_2 0x00000838
941 #define MAC_TX_STATS_RESV4_3 0x0000083c
942 #define MAC_TX_STATS_RESV4_4 0x00000840
943 #define MAC_TX_STATS_RESV4_5 0x00000844
944 #define MAC_TX_STATS_RESV4_6 0x00000848
945 #define MAC_TX_STATS_RESV4_7 0x0000084c
946 #define MAC_TX_STATS_RESV4_8 0x00000850
947 #define MAC_TX_STATS_RESV4_9 0x00000854
948 #define MAC_TX_STATS_RESV4_10 0x00000858
949 #define MAC_TX_STATS_RESV4_11 0x0000085c
950 #define MAC_TX_STATS_RESV4_12 0x00000860
951 #define MAC_TX_STATS_RESV4_13 0x00000864
952 #define MAC_TX_STATS_RESV4_14 0x00000868
953 #define MAC_TX_STATS_UCAST 0x0000086c
954 #define MAC_TX_STATS_MCAST 0x00000870
955 #define MAC_TX_STATS_BCAST 0x00000874
956 #define MAC_TX_STATS_RESV5_1 0x00000878
957 #define MAC_TX_STATS_RESV5_2 0x0000087c
958 #define MAC_RX_STATS_OCTETS 0x00000880
959 #define MAC_RX_STATS_RESV1 0x00000884
960 #define MAC_RX_STATS_FRAGMENTS 0x00000888
961 #define MAC_RX_STATS_UCAST 0x0000088c
962 #define MAC_RX_STATS_MCAST 0x00000890
963 #define MAC_RX_STATS_BCAST 0x00000894
964 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
965 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
966 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
967 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
968 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
969 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
970 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
971 #define MAC_RX_STATS_JABBERS 0x000008b4
972 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
973 /* 0x8bc --> 0xc00 unused */
975 /* Send data initiator control registers */
976 #define SNDDATAI_MODE 0x00000c00
977 #define SNDDATAI_MODE_RESET 0x00000001
978 #define SNDDATAI_MODE_ENABLE 0x00000002
979 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
980 #define SNDDATAI_STATUS 0x00000c04
981 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
982 #define SNDDATAI_STATSCTRL 0x00000c08
983 #define SNDDATAI_SCTRL_ENABLE 0x00000001
984 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
985 #define SNDDATAI_SCTRL_CLEAR 0x00000004
986 #define SNDDATAI_SCTRL_FLUSH 0x00000008
987 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
988 #define SNDDATAI_STATSENAB 0x00000c0c
989 #define SNDDATAI_STATSINCMASK 0x00000c10
990 /* 0xc14 --> 0xc80 unused */
991 #define SNDDATAI_COS_CNT_0 0x00000c80
992 #define SNDDATAI_COS_CNT_1 0x00000c84
993 #define SNDDATAI_COS_CNT_2 0x00000c88
994 #define SNDDATAI_COS_CNT_3 0x00000c8c
995 #define SNDDATAI_COS_CNT_4 0x00000c90
996 #define SNDDATAI_COS_CNT_5 0x00000c94
997 #define SNDDATAI_COS_CNT_6 0x00000c98
998 #define SNDDATAI_COS_CNT_7 0x00000c9c
999 #define SNDDATAI_COS_CNT_8 0x00000ca0
1000 #define SNDDATAI_COS_CNT_9 0x00000ca4
1001 #define SNDDATAI_COS_CNT_10 0x00000ca8
1002 #define SNDDATAI_COS_CNT_11 0x00000cac
1003 #define SNDDATAI_COS_CNT_12 0x00000cb0
1004 #define SNDDATAI_COS_CNT_13 0x00000cb4
1005 #define SNDDATAI_COS_CNT_14 0x00000cb8
1006 #define SNDDATAI_COS_CNT_15 0x00000cbc
1007 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
1008 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
1009 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
1010 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
1011 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
1012 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
1013 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
1014 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
1015 /* 0xce0 --> 0x1000 unused */
1017 /* Send data completion control registers */
1018 #define SNDDATAC_MODE 0x00001000
1019 #define SNDDATAC_MODE_RESET 0x00000001
1020 #define SNDDATAC_MODE_ENABLE 0x00000002
1021 /* 0x1004 --> 0x1400 unused */
1023 /* Send BD ring selector */
1024 #define SNDBDS_MODE 0x00001400
1025 #define SNDBDS_MODE_RESET 0x00000001
1026 #define SNDBDS_MODE_ENABLE 0x00000002
1027 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
1028 #define SNDBDS_STATUS 0x00001404
1029 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
1030 #define SNDBDS_HWDIAG 0x00001408
1031 /* 0x140c --> 0x1440 */
1032 #define SNDBDS_SEL_CON_IDX_0 0x00001440
1033 #define SNDBDS_SEL_CON_IDX_1 0x00001444
1034 #define SNDBDS_SEL_CON_IDX_2 0x00001448
1035 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
1036 #define SNDBDS_SEL_CON_IDX_4 0x00001450
1037 #define SNDBDS_SEL_CON_IDX_5 0x00001454
1038 #define SNDBDS_SEL_CON_IDX_6 0x00001458
1039 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
1040 #define SNDBDS_SEL_CON_IDX_8 0x00001460
1041 #define SNDBDS_SEL_CON_IDX_9 0x00001464
1042 #define SNDBDS_SEL_CON_IDX_10 0x00001468
1043 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
1044 #define SNDBDS_SEL_CON_IDX_12 0x00001470
1045 #define SNDBDS_SEL_CON_IDX_13 0x00001474
1046 #define SNDBDS_SEL_CON_IDX_14 0x00001478
1047 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
1048 /* 0x1480 --> 0x1800 unused */
1050 /* Send BD initiator control registers */
1051 #define SNDBDI_MODE 0x00001800
1052 #define SNDBDI_MODE_RESET 0x00000001
1053 #define SNDBDI_MODE_ENABLE 0x00000002
1054 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
1055 #define SNDBDI_STATUS 0x00001804
1056 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
1057 #define SNDBDI_IN_PROD_IDX_0 0x00001808
1058 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
1059 #define SNDBDI_IN_PROD_IDX_2 0x00001810
1060 #define SNDBDI_IN_PROD_IDX_3 0x00001814
1061 #define SNDBDI_IN_PROD_IDX_4 0x00001818
1062 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
1063 #define SNDBDI_IN_PROD_IDX_6 0x00001820
1064 #define SNDBDI_IN_PROD_IDX_7 0x00001824
1065 #define SNDBDI_IN_PROD_IDX_8 0x00001828
1066 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
1067 #define SNDBDI_IN_PROD_IDX_10 0x00001830
1068 #define SNDBDI_IN_PROD_IDX_11 0x00001834
1069 #define SNDBDI_IN_PROD_IDX_12 0x00001838
1070 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
1071 #define SNDBDI_IN_PROD_IDX_14 0x00001840
1072 #define SNDBDI_IN_PROD_IDX_15 0x00001844
1073 /* 0x1848 --> 0x1c00 unused */
1075 /* Send BD completion control registers */
1076 #define SNDBDC_MODE 0x00001c00
1077 #define SNDBDC_MODE_RESET 0x00000001
1078 #define SNDBDC_MODE_ENABLE 0x00000002
1079 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
1080 /* 0x1c04 --> 0x2000 unused */
1082 /* Receive list placement control registers */
1083 #define RCVLPC_MODE 0x00002000
1084 #define RCVLPC_MODE_RESET 0x00000001
1085 #define RCVLPC_MODE_ENABLE 0x00000002
1086 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
1087 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
1088 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
1089 #define RCVLPC_STATUS 0x00002004
1090 #define RCVLPC_STATUS_CLASS0 0x00000004
1091 #define RCVLPC_STATUS_MAPOOR 0x00000008
1092 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
1093 #define RCVLPC_LOCK 0x00002008
1094 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
1095 #define RCVLPC_LOCK_REQ_SHIFT 0
1096 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1097 #define RCVLPC_LOCK_GRANT_SHIFT 16
1098 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
1099 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1100 #define RCVLPC_CONFIG 0x00002010
1101 #define RCVLPC_STATSCTRL 0x00002014
1102 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
1103 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1104 #define RCVLPC_STATS_ENABLE 0x00002018
1105 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1106 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1107 #define RCVLPC_STATS_INCMASK 0x0000201c
1108 /* 0x2020 --> 0x2100 unused */
1109 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
1110 #define SELLST_TAIL 0x00000004
1111 #define SELLST_CONT 0x00000008
1112 #define SELLST_UNUSED 0x0000000c
1113 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
1114 #define RCVLPC_DROP_FILTER_CNT 0x00002240
1115 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1116 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1117 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1118 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
1119 #define RCVLPC_IN_ERRORS_CNT 0x00002254
1120 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1121 /* 0x225c --> 0x2400 unused */
1123 /* Receive Data and Receive BD Initiator Control */
1124 #define RCVDBDI_MODE 0x00002400
1125 #define RCVDBDI_MODE_RESET 0x00000001
1126 #define RCVDBDI_MODE_ENABLE 0x00000002
1127 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1128 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1129 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1130 #define RCVDBDI_STATUS 0x00002404
1131 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1132 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1133 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1134 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1135 /* 0x240c --> 0x2440 unused */
1136 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
1137 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
1138 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
1139 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
1140 #define RCVDBDI_STD_CON_IDX 0x00002474
1141 #define RCVDBDI_MINI_CON_IDX 0x00002478
1142 /* 0x247c --> 0x2480 unused */
1143 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
1144 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
1145 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
1146 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1147 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
1148 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
1149 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
1150 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1151 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1152 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1153 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1154 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1155 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1156 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1157 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1158 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1159 #define RCVDBDI_HWDIAG 0x000024c0
1160 /* 0x24c4 --> 0x2800 unused */
1162 /* Receive Data Completion Control */
1163 #define RCVDCC_MODE 0x00002800
1164 #define RCVDCC_MODE_RESET 0x00000001
1165 #define RCVDCC_MODE_ENABLE 0x00000002
1166 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1167 /* 0x2804 --> 0x2c00 unused */
1169 /* Receive BD Initiator Control Registers */
1170 #define RCVBDI_MODE 0x00002c00
1171 #define RCVBDI_MODE_RESET 0x00000001
1172 #define RCVBDI_MODE_ENABLE 0x00000002
1173 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1174 #define RCVBDI_STATUS 0x00002c04
1175 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
1176 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1177 #define RCVBDI_STD_PROD_IDX 0x00002c0c
1178 #define RCVBDI_MINI_PROD_IDX 0x00002c10
1179 #define RCVBDI_MINI_THRESH 0x00002c14
1180 #define RCVBDI_STD_THRESH 0x00002c18
1181 #define RCVBDI_JUMBO_THRESH 0x00002c1c
1182 /* 0x2c20 --> 0x3000 unused */
1184 /* Receive BD Completion Control Registers */
1185 #define RCVCC_MODE 0x00003000
1186 #define RCVCC_MODE_RESET 0x00000001
1187 #define RCVCC_MODE_ENABLE 0x00000002
1188 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
1189 #define RCVCC_STATUS 0x00003004
1190 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
1191 #define RCVCC_JUMP_PROD_IDX 0x00003008
1192 #define RCVCC_STD_PROD_IDX 0x0000300c
1193 #define RCVCC_MINI_PROD_IDX 0x00003010
1194 /* 0x3014 --> 0x3400 unused */
1196 /* Receive list selector control registers */
1197 #define RCVLSC_MODE 0x00003400
1198 #define RCVLSC_MODE_RESET 0x00000001
1199 #define RCVLSC_MODE_ENABLE 0x00000002
1200 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1201 #define RCVLSC_STATUS 0x00003404
1202 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1203 /* 0x3408 --> 0x3800 unused */
1205 /* Mbuf cluster free registers */
1206 #define MBFREE_MODE 0x00003800
1207 #define MBFREE_MODE_RESET 0x00000001
1208 #define MBFREE_MODE_ENABLE 0x00000002
1209 #define MBFREE_STATUS 0x00003804
1210 /* 0x3808 --> 0x3c00 unused */
1212 /* Host coalescing control registers */
1213 #define HOSTCC_MODE 0x00003c00
1214 #define HOSTCC_MODE_RESET 0x00000001
1215 #define HOSTCC_MODE_ENABLE 0x00000002
1216 #define HOSTCC_MODE_ATTN 0x00000004
1217 #define HOSTCC_MODE_NOW 0x00000008
1218 #define HOSTCC_MODE_FULL_STATUS 0x00000000
1219 #define HOSTCC_MODE_64BYTE 0x00000080
1220 #define HOSTCC_MODE_32BYTE 0x00000100
1221 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1222 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1223 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1224 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1225 #define HOSTCC_STATUS 0x00003c04
1226 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1227 #define HOSTCC_RXCOL_TICKS 0x00003c08
1228 #define LOW_RXCOL_TICKS 0x00000032
1229 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1230 #define DEFAULT_RXCOL_TICKS 0x00000048
1231 #define HIGH_RXCOL_TICKS 0x00000096
1232 #define MAX_RXCOL_TICKS 0x000003ff
1233 #define HOSTCC_TXCOL_TICKS 0x00003c0c
1234 #define LOW_TXCOL_TICKS 0x00000096
1235 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1236 #define DEFAULT_TXCOL_TICKS 0x0000012c
1237 #define HIGH_TXCOL_TICKS 0x00000145
1238 #define MAX_TXCOL_TICKS 0x000003ff
1239 #define HOSTCC_RXMAX_FRAMES 0x00003c10
1240 #define LOW_RXMAX_FRAMES 0x00000005
1241 #define DEFAULT_RXMAX_FRAMES 0x00000008
1242 #define HIGH_RXMAX_FRAMES 0x00000012
1243 #define MAX_RXMAX_FRAMES 0x000000ff
1244 #define HOSTCC_TXMAX_FRAMES 0x00003c14
1245 #define LOW_TXMAX_FRAMES 0x00000035
1246 #define DEFAULT_TXMAX_FRAMES 0x0000004b
1247 #define HIGH_TXMAX_FRAMES 0x00000052
1248 #define MAX_TXMAX_FRAMES 0x000000ff
1249 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1250 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
1251 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1252 #define MAX_RXCOAL_TICK_INT 0x000003ff
1253 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1254 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
1255 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1256 #define MAX_TXCOAL_TICK_INT 0x000003ff
1257 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1258 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1259 #define MAX_RXCOAL_MAXF_INT 0x000000ff
1260 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1261 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1262 #define MAX_TXCOAL_MAXF_INT 0x000000ff
1263 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
1264 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
1265 #define MAX_STAT_COAL_TICKS 0xd693d400
1266 #define MIN_STAT_COAL_TICKS 0x00000064
1267 /* 0x3c2c --> 0x3c30 unused */
1268 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1269 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1270 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1271 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1272 #define HOSTCC_FLOW_ATTN 0x00003c48
1273 /* 0x3c4c --> 0x3c50 unused */
1274 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
1275 #define HOSTCC_STD_CON_IDX 0x00003c54
1276 #define HOSTCC_MINI_CON_IDX 0x00003c58
1277 /* 0x3c5c --> 0x3c80 unused */
1278 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
1279 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
1280 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
1281 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1282 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
1283 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
1284 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
1285 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1286 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1287 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1288 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1289 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
1290 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1291 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1292 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1293 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1294 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
1295 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
1296 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
1297 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
1298 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
1299 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
1300 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
1301 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
1302 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
1303 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
1304 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
1305 #define HOSTCC_SND_CON_IDX_11 0x00003cec
1306 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
1307 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
1308 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
1309 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
1310 /* 0x3d00 --> 0x4000 unused */
1312 /* Memory arbiter control registers */
1313 #define MEMARB_MODE 0x00004000
1314 #define MEMARB_MODE_RESET 0x00000001
1315 #define MEMARB_MODE_ENABLE 0x00000002
1316 #define MEMARB_STATUS 0x00004004
1317 #define MEMARB_TRAP_ADDR_LOW 0x00004008
1318 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1319 /* 0x4010 --> 0x4400 unused */
1321 /* Buffer manager control registers */
1322 #define BUFMGR_MODE 0x00004400
1323 #define BUFMGR_MODE_RESET 0x00000001
1324 #define BUFMGR_MODE_ENABLE 0x00000002
1325 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1326 #define BUFMGR_MODE_BM_TEST 0x00000008
1327 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1328 #define BUFMGR_STATUS 0x00004404
1329 #define BUFMGR_STATUS_ERROR 0x00000004
1330 #define BUFMGR_STATUS_MBLOW 0x00000010
1331 #define BUFMGR_MB_POOL_ADDR 0x00004408
1332 #define BUFMGR_MB_POOL_SIZE 0x0000440c
1333 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1334 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1335 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1336 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1337 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1338 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1339 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1340 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1341 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1342 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1343 #define BUFMGR_MB_HIGH_WATER 0x00004418
1344 #define DEFAULT_MB_HIGH_WATER 0x00000060
1345 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1346 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1347 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1348 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1349 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1350 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1351 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1352 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1353 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1354 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1355 #define BUFMGR_DMA_LOW_WATER 0x00004434
1356 #define DEFAULT_DMA_LOW_WATER 0x00000005
1357 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1358 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1359 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1360 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1361 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1362 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1363 #define BUFMGR_HWDIAG_0 0x0000444c
1364 #define BUFMGR_HWDIAG_1 0x00004450
1365 #define BUFMGR_HWDIAG_2 0x00004454
1366 /* 0x4458 --> 0x4800 unused */
1368 /* Read DMA control registers */
1369 #define RDMAC_MODE 0x00004800
1370 #define RDMAC_MODE_RESET 0x00000001
1371 #define RDMAC_MODE_ENABLE 0x00000002
1372 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1373 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1374 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1375 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1376 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1377 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1378 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1379 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1380 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1381 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1382 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1383 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1384 #define RDMAC_STATUS 0x00004804
1385 #define RDMAC_STATUS_TGTABORT 0x00000004
1386 #define RDMAC_STATUS_MSTABORT 0x00000008
1387 #define RDMAC_STATUS_PARITYERR 0x00000010
1388 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1389 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1390 #define RDMAC_STATUS_FIFOURUN 0x00000080
1391 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1392 #define RDMAC_STATUS_LNGREAD 0x00000200
1393 /* 0x4808 --> 0x4c00 unused */
1395 /* Write DMA control registers */
1396 #define WDMAC_MODE 0x00004c00
1397 #define WDMAC_MODE_RESET 0x00000001
1398 #define WDMAC_MODE_ENABLE 0x00000002
1399 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1400 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1401 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1402 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1403 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1404 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1405 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1406 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1407 #define WDMAC_MODE_RX_ACCEL 0x00000400
1408 #define WDMAC_STATUS 0x00004c04
1409 #define WDMAC_STATUS_TGTABORT 0x00000004
1410 #define WDMAC_STATUS_MSTABORT 0x00000008
1411 #define WDMAC_STATUS_PARITYERR 0x00000010
1412 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1413 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1414 #define WDMAC_STATUS_FIFOURUN 0x00000080
1415 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1416 #define WDMAC_STATUS_LNGREAD 0x00000200
1417 /* 0x4c08 --> 0x5000 unused */
1419 /* Per-cpu register offsets (arm9) */
1420 #define CPU_MODE 0x00000000
1421 #define CPU_MODE_RESET 0x00000001
1422 #define CPU_MODE_HALT 0x00000400
1423 #define CPU_STATE 0x00000004
1424 #define CPU_EVTMASK 0x00000008
1425 /* 0xc --> 0x1c reserved */
1426 #define CPU_PC 0x0000001c
1427 #define CPU_INSN 0x00000020
1428 #define CPU_SPAD_UFLOW 0x00000024
1429 #define CPU_WDOG_CLEAR 0x00000028
1430 #define CPU_WDOG_VECTOR 0x0000002c
1431 #define CPU_WDOG_PC 0x00000030
1432 #define CPU_HW_BP 0x00000034
1433 /* 0x38 --> 0x44 unused */
1434 #define CPU_WDOG_SAVED_STATE 0x00000044
1435 #define CPU_LAST_BRANCH_ADDR 0x00000048
1436 #define CPU_SPAD_UFLOW_SET 0x0000004c
1437 /* 0x50 --> 0x200 unused */
1438 #define CPU_R0 0x00000200
1439 #define CPU_R1 0x00000204
1440 #define CPU_R2 0x00000208
1441 #define CPU_R3 0x0000020c
1442 #define CPU_R4 0x00000210
1443 #define CPU_R5 0x00000214
1444 #define CPU_R6 0x00000218
1445 #define CPU_R7 0x0000021c
1446 #define CPU_R8 0x00000220
1447 #define CPU_R9 0x00000224
1448 #define CPU_R10 0x00000228
1449 #define CPU_R11 0x0000022c
1450 #define CPU_R12 0x00000230
1451 #define CPU_R13 0x00000234
1452 #define CPU_R14 0x00000238
1453 #define CPU_R15 0x0000023c
1454 #define CPU_R16 0x00000240
1455 #define CPU_R17 0x00000244
1456 #define CPU_R18 0x00000248
1457 #define CPU_R19 0x0000024c
1458 #define CPU_R20 0x00000250
1459 #define CPU_R21 0x00000254
1460 #define CPU_R22 0x00000258
1461 #define CPU_R23 0x0000025c
1462 #define CPU_R24 0x00000260
1463 #define CPU_R25 0x00000264
1464 #define CPU_R26 0x00000268
1465 #define CPU_R27 0x0000026c
1466 #define CPU_R28 0x00000270
1467 #define CPU_R29 0x00000274
1468 #define CPU_R30 0x00000278
1469 #define CPU_R31 0x0000027c
1470 /* 0x280 --> 0x400 unused */
1472 #define RX_CPU_BASE 0x00005000
1473 #define RX_CPU_MODE 0x00005000
1474 #define RX_CPU_STATE 0x00005004
1475 #define RX_CPU_PGMCTR 0x0000501c
1476 #define RX_CPU_HWBKPT 0x00005034
1477 #define TX_CPU_BASE 0x00005400
1478 #define TX_CPU_MODE 0x00005400
1479 #define TX_CPU_STATE 0x00005404
1480 #define TX_CPU_PGMCTR 0x0000541c
1483 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1484 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1485 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1486 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1487 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1488 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1489 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1490 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1491 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1492 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1493 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1494 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1495 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1496 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1497 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1498 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1499 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1500 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1501 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1502 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1503 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1504 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1505 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1506 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1507 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1508 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1509 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1510 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1511 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1512 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1513 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1514 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1515 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1516 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1517 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1518 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1519 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1520 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1521 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1522 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1523 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1524 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1525 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1526 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1527 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1528 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1529 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1530 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1531 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1532 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1533 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1534 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1535 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1536 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1537 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1538 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1539 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1540 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1541 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1542 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1543 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1544 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1545 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1546 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1547 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1548 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1549 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1550 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1551 /* 0x5a10 --> 0x5c00 */
1553 /* Flow Through queues */
1554 #define FTQ_RESET 0x00005c00
1555 /* 0x5c04 --> 0x5c10 unused */
1556 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1557 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1558 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1559 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1560 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1561 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1562 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1563 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1564 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1565 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1566 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1567 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1568 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1569 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1570 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1571 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1572 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1573 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1574 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1575 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1576 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1577 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1578 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1579 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1580 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1581 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1582 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1583 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1584 #define FTQ_SWTYPE1_CTL 0x00005c80
1585 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1586 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1587 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1588 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1589 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1590 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1591 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1592 #define FTQ_HOST_COAL_CTL 0x00005ca0
1593 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1594 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1595 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1596 #define FTQ_MAC_TX_CTL 0x00005cb0
1597 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1598 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1599 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1600 #define FTQ_MB_FREE_CTL 0x00005cc0
1601 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1602 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1603 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1604 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1605 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1606 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1607 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1608 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1609 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1610 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1611 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1612 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1613 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1614 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1615 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1616 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1617 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1618 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1619 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1620 #define FTQ_SWTYPE2_CTL 0x00005d10
1621 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1622 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1623 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1624 /* 0x5d20 --> 0x6000 unused */
1626 /* Message signaled interrupt registers */
1627 #define MSGINT_MODE 0x00006000
1628 #define MSGINT_MODE_RESET 0x00000001
1629 #define MSGINT_MODE_ENABLE 0x00000002
1630 #define MSGINT_STATUS 0x00006004
1631 #define MSGINT_FIFO 0x00006008
1632 /* 0x600c --> 0x6400 unused */
1634 /* DMA completion registers */
1635 #define DMAC_MODE 0x00006400
1636 #define DMAC_MODE_RESET 0x00000001
1637 #define DMAC_MODE_ENABLE 0x00000002
1638 /* 0x6404 --> 0x6800 unused */
1641 #define GRC_MODE 0x00006800
1642 #define GRC_MODE_UPD_ON_COAL 0x00000001
1643 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1644 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1645 #define GRC_MODE_BSWAP_DATA 0x00000010
1646 #define GRC_MODE_WSWAP_DATA 0x00000020
1647 #define GRC_MODE_SPLITHDR 0x00000100
1648 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1649 #define GRC_MODE_INCL_CRC 0x00000400
1650 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1651 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1652 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1653 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1654 #define GRC_MODE_HOST_STACKUP 0x00010000
1655 #define GRC_MODE_HOST_SENDBDS 0x00020000
1656 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1657 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1658 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1659 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1660 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1661 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1662 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1663 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1664 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1665 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1666 #define GRC_MISC_CFG 0x00006804
1667 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1668 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1669 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1670 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1671 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1672 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1673 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1674 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1675 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1676 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1677 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1678 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1679 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1680 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1681 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1682 #define GRC_MISC_CFG_BOARD_ID_5754 0x00008000
1683 #define GRC_MISC_CFG_BOARD_ID_5754M 0x0000c000
1684 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1685 #define GRC_LOCAL_CTRL 0x00006808
1686 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1687 #define GRC_LCLCTRL_CLEARINT 0x00000002
1688 #define GRC_LCLCTRL_SETINT 0x00000004
1689 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1690 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1691 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1692 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1693 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1694 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1695 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1696 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1697 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1698 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1699 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1700 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1701 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1702 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1703 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1704 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1705 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1706 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1707 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1708 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1709 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1710 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1711 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1712 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1713 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1714 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1715 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1716 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1717 #define GRC_TIMER 0x0000680c
1718 #define GRC_RX_CPU_EVENT 0x00006810
1719 #define GRC_RX_TIMER_REF 0x00006814
1720 #define GRC_RX_CPU_SEM 0x00006818
1721 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1722 #define GRC_TX_CPU_EVENT 0x00006820
1723 #define GRC_TX_TIMER_REF 0x00006824
1724 #define GRC_TX_CPU_SEM 0x00006828
1725 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1726 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1727 #define GRC_EEPROM_ADDR 0x00006838
1728 #define EEPROM_ADDR_WRITE 0x00000000
1729 #define EEPROM_ADDR_READ 0x80000000
1730 #define EEPROM_ADDR_COMPLETE 0x40000000
1731 #define EEPROM_ADDR_FSM_RESET 0x20000000
1732 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1733 #define EEPROM_ADDR_DEVID_SHIFT 26
1734 #define EEPROM_ADDR_START 0x02000000
1735 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1736 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1737 #define EEPROM_ADDR_ADDR_SHIFT 0
1738 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1739 #define EEPROM_CHIP_SIZE (64 * 1024)
1740 #define GRC_EEPROM_DATA 0x0000683c
1741 #define GRC_EEPROM_CTRL 0x00006840
1742 #define GRC_MDI_CTRL 0x00006844
1743 #define GRC_SEEPROM_DELAY 0x00006848
1744 /* 0x684c --> 0x6c00 unused */
1745 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1747 /* 0x6c00 --> 0x7000 unused */
1749 /* NVRAM Control registers */
1750 #define NVRAM_CMD 0x00007000
1751 #define NVRAM_CMD_RESET 0x00000001
1752 #define NVRAM_CMD_DONE 0x00000008
1753 #define NVRAM_CMD_GO 0x00000010
1754 #define NVRAM_CMD_WR 0x00000020
1755 #define NVRAM_CMD_RD 0x00000000
1756 #define NVRAM_CMD_ERASE 0x00000040
1757 #define NVRAM_CMD_FIRST 0x00000080
1758 #define NVRAM_CMD_LAST 0x00000100
1759 #define NVRAM_CMD_WREN 0x00010000
1760 #define NVRAM_CMD_WRDI 0x00020000
1761 #define NVRAM_STAT 0x00007004
1762 #define NVRAM_WRDATA 0x00007008
1763 #define NVRAM_ADDR 0x0000700c
1764 #define NVRAM_ADDR_MSK 0x00ffffff
1765 #define NVRAM_RDDATA 0x00007010
1766 #define NVRAM_CFG1 0x00007014
1767 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1768 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1769 #define NVRAM_CFG1_PASS_THRU 0x00000004
1770 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1771 #define NVRAM_CFG1_BIT_BANG 0x00000008
1772 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1773 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1774 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1775 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1776 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1777 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1778 #define FLASH_VENDOR_ST 0x03000001
1779 #define FLASH_VENDOR_SAIFUN 0x01000003
1780 #define FLASH_VENDOR_SST_SMALL 0x00000001
1781 #define FLASH_VENDOR_SST_LARGE 0x02000001
1782 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1783 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1784 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1785 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1786 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1787 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1788 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1789 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1790 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1791 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1792 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1793 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1794 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1795 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1796 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1797 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1798 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1799 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1800 #define FLASH_5752PAGE_SIZE_256 0x00000000
1801 #define FLASH_5752PAGE_SIZE_512 0x10000000
1802 #define FLASH_5752PAGE_SIZE_1K 0x20000000
1803 #define FLASH_5752PAGE_SIZE_2K 0x30000000
1804 #define FLASH_5752PAGE_SIZE_4K 0x40000000
1805 #define FLASH_5752PAGE_SIZE_264 0x50000000
1806 #define NVRAM_CFG2 0x00007018
1807 #define NVRAM_CFG3 0x0000701c
1808 #define NVRAM_SWARB 0x00007020
1809 #define SWARB_REQ_SET0 0x00000001
1810 #define SWARB_REQ_SET1 0x00000002
1811 #define SWARB_REQ_SET2 0x00000004
1812 #define SWARB_REQ_SET3 0x00000008
1813 #define SWARB_REQ_CLR0 0x00000010
1814 #define SWARB_REQ_CLR1 0x00000020
1815 #define SWARB_REQ_CLR2 0x00000040
1816 #define SWARB_REQ_CLR3 0x00000080
1817 #define SWARB_GNT0 0x00000100
1818 #define SWARB_GNT1 0x00000200
1819 #define SWARB_GNT2 0x00000400
1820 #define SWARB_GNT3 0x00000800
1821 #define SWARB_REQ0 0x00001000
1822 #define SWARB_REQ1 0x00002000
1823 #define SWARB_REQ2 0x00004000
1824 #define SWARB_REQ3 0x00008000
1825 #define NVRAM_ACCESS 0x00007024
1826 #define ACCESS_ENABLE 0x00000001
1827 #define ACCESS_WR_ENABLE 0x00000002
1828 #define NVRAM_WRITE1 0x00007028
1829 /* 0x702c --> 0x7400 unused */
1831 /* 0x7400 --> 0x8000 unused */
1833 #define TG3_EEPROM_MAGIC 0x669955aa
1835 /* 32K Window into NIC internal memory */
1836 #define NIC_SRAM_WIN_BASE 0x00008000
1838 /* Offsets into first 32k of NIC internal memory. */
1839 #define NIC_SRAM_PAGE_ZERO 0x00000000
1840 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1841 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1842 #define NIC_SRAM_STATS_BLK 0x00000300
1843 #define NIC_SRAM_STATUS_BLK 0x00000b00
1845 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1846 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1847 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1849 #define NIC_SRAM_DATA_SIG 0x00000b54
1850 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1852 #define NIC_SRAM_DATA_CFG 0x00000b58
1853 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1854 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1855 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1856 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1857 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1858 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1859 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1860 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1861 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1862 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1863 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1864 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1865 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1866 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
1868 #define NIC_SRAM_DATA_VER 0x00000b5c
1869 #define NIC_SRAM_DATA_VER_SHIFT 16
1871 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1872 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1873 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1875 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1876 #define FWCMD_NICDRV_ALIVE 0x00000001
1877 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1878 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1879 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1880 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1881 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1882 #define FWCMD_NICDRV_ALIVE2 0x0000000d
1883 #define FWCMD_NICDRV_ALIVE_DETECT 0x0000000e
1884 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1885 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1886 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1887 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1888 #define DRV_STATE_START 0x00000001
1889 #define DRV_STATE_START_DONE 0x80000001
1890 #define DRV_STATE_UNLOAD 0x00000002
1891 #define DRV_STATE_UNLOAD_DONE 0x80000002
1892 #define DRV_STATE_WOL 0x00000003
1893 #define DRV_STATE_SUSPEND 0x00000004
1895 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1897 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1898 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1900 #define NIC_SRAM_WOL_MBOX 0x00000d30
1901 #define WOL_SIGNATURE 0x474c0000
1902 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
1903 #define WOL_DRV_WOL 0x00000002
1904 #define WOL_SET_MAGIC_PKT 0x00000004
1906 #define NIC_SRAM_DATA_CFG_2 0x00000d38
1908 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
1909 #define SHASTA_EXT_LED_LEGACY 0x00000000
1910 #define SHASTA_EXT_LED_SHARED 0x00008000
1911 #define SHASTA_EXT_LED_MAC 0x00010000
1912 #define SHASTA_EXT_LED_COMBO 0x00018000
1914 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1916 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1917 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1918 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1919 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1920 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1921 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1922 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1923 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1924 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1925 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1927 /* Currently this is fixed. */
1928 #define PHY_ADDR 0x01
1930 /* Tigon3 specific PHY MII registers. */
1931 #define TG3_BMCR_SPEED1000 0x0040
1933 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1934 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1935 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1936 #define MII_TG3_CTRL_AS_MASTER 0x0800
1937 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1939 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1940 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1941 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1942 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1943 #define MII_TG3_EXT_CTRL_TBI 0x8000
1945 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1946 #define MII_TG3_EXT_STAT_LPASS 0x0100
1948 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1950 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1952 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1954 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1955 #define MII_TG3_AUX_STAT_LPASS 0x0004
1956 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1957 #define MII_TG3_AUX_STAT_10HALF 0x0100
1958 #define MII_TG3_AUX_STAT_10FULL 0x0200
1959 #define MII_TG3_AUX_STAT_100HALF 0x0300
1960 #define MII_TG3_AUX_STAT_100_4 0x0400
1961 #define MII_TG3_AUX_STAT_100FULL 0x0500
1962 #define MII_TG3_AUX_STAT_1000HALF 0x0600
1963 #define MII_TG3_AUX_STAT_1000FULL 0x0700
1964 #define MII_TG3_AUX_STAT_100 0x0008
1965 #define MII_TG3_AUX_STAT_FULL 0x0001
1967 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1968 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1970 /* ISTAT/IMASK event bits */
1971 #define MII_TG3_INT_LINKCHG 0x0002
1972 #define MII_TG3_INT_SPEEDCHG 0x0004
1973 #define MII_TG3_INT_DUPLEXCHG 0x0008
1974 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1976 /* There are two ways to manage the TX descriptors on the tigon3.
1977 * Either the descriptors are in host DMA'able memory, or they
1978 * exist only in the cards on-chip SRAM. All 16 send bds are under
1979 * the same mode, they may not be configured individually.
1981 * This driver always uses host memory TX descriptors.
1983 * To use host memory TX descriptors:
1984 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1985 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1986 * 2) Allocate DMA'able memory.
1987 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1988 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1989 * obtained in step 2
1990 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1991 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1992 * of TX descriptors. Leave flags field clear.
1993 * 4) Access TX descriptors via host memory. The chip
1994 * will refetch into local SRAM as needed when producer
1995 * index mailboxes are updated.
1997 * To use on-chip TX descriptors:
1998 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1999 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2000 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2001 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2002 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2003 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2004 * 3) Access TX descriptors directly in on-chip SRAM
2005 * using normal {read,write}l(). (and not using
2006 * pointer dereferencing of ioremap()'d memory like
2007 * the broken Broadcom driver does)
2009 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2010 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2012 struct tg3_tx_buffer_desc {
2017 #define TXD_FLAG_TCPUDP_CSUM 0x0001
2018 #define TXD_FLAG_IP_CSUM 0x0002
2019 #define TXD_FLAG_END 0x0004
2020 #define TXD_FLAG_IP_FRAG 0x0008
2021 #define TXD_FLAG_IP_FRAG_END 0x0010
2022 #define TXD_FLAG_VLAN 0x0040
2023 #define TXD_FLAG_COAL_NOW 0x0080
2024 #define TXD_FLAG_CPU_PRE_DMA 0x0100
2025 #define TXD_FLAG_CPU_POST_DMA 0x0200
2026 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
2027 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2028 #define TXD_FLAG_NO_CRC 0x8000
2029 #define TXD_LEN_SHIFT 16
2032 #define TXD_VLAN_TAG_SHIFT 0
2033 #define TXD_MSS_SHIFT 16
2036 #define TXD_ADDR 0x00UL /* 64-bit */
2037 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2038 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2039 #define TXD_SIZE 0x10UL
2041 struct tg3_rx_buffer_desc {
2046 #define RXD_IDX_MASK 0xffff0000
2047 #define RXD_IDX_SHIFT 16
2048 #define RXD_LEN_MASK 0x0000ffff
2049 #define RXD_LEN_SHIFT 0
2052 #define RXD_TYPE_SHIFT 16
2053 #define RXD_FLAGS_SHIFT 0
2055 #define RXD_FLAG_END 0x0004
2056 #define RXD_FLAG_MINI 0x0800
2057 #define RXD_FLAG_JUMBO 0x0020
2058 #define RXD_FLAG_VLAN 0x0040
2059 #define RXD_FLAG_ERROR 0x0400
2060 #define RXD_FLAG_IP_CSUM 0x1000
2061 #define RXD_FLAG_TCPUDP_CSUM 0x2000
2062 #define RXD_FLAG_IS_TCP 0x4000
2065 #define RXD_IPCSUM_MASK 0xffff0000
2066 #define RXD_IPCSUM_SHIFT 16
2067 #define RXD_TCPCSUM_MASK 0x0000ffff
2068 #define RXD_TCPCSUM_SHIFT 0
2072 #define RXD_VLAN_MASK 0x0000ffff
2074 #define RXD_ERR_BAD_CRC 0x00010000
2075 #define RXD_ERR_COLLISION 0x00020000
2076 #define RXD_ERR_LINK_LOST 0x00040000
2077 #define RXD_ERR_PHY_DECODE 0x00080000
2078 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2079 #define RXD_ERR_MAC_ABRT 0x00200000
2080 #define RXD_ERR_TOO_SMALL 0x00400000
2081 #define RXD_ERR_NO_RESOURCES 0x00800000
2082 #define RXD_ERR_HUGE_FRAME 0x01000000
2083 #define RXD_ERR_MASK 0xffff0000
2087 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2088 #define RXD_OPAQUE_INDEX_SHIFT 0
2089 #define RXD_OPAQUE_RING_STD 0x00010000
2090 #define RXD_OPAQUE_RING_JUMBO 0x00020000
2091 #define RXD_OPAQUE_RING_MINI 0x00040000
2092 #define RXD_OPAQUE_RING_MASK 0x00070000
2095 struct tg3_ext_rx_buffer_desc {
2102 struct tg3_rx_buffer_desc std;
2105 /* We only use this when testing out the DMA engine
2106 * at probe time. This is the internal format of buffer
2107 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2109 struct tg3_internal_buffer_desc {
2127 #define TG3_HW_STATUS_SIZE 0x50
2128 struct tg3_hw_status {
2129 volatile u32 status;
2130 #define SD_STATUS_UPDATED 0x00000001
2131 #define SD_STATUS_LINK_CHG 0x00000002
2132 #define SD_STATUS_ERROR 0x00000004
2134 volatile u32 status_tag;
2137 volatile u16 rx_consumer;
2138 volatile u16 rx_jumbo_consumer;
2140 volatile u16 rx_jumbo_consumer;
2141 volatile u16 rx_consumer;
2145 volatile u16 reserved;
2146 volatile u16 rx_mini_consumer;
2148 volatile u16 rx_mini_consumer;
2149 volatile u16 reserved;
2153 volatile u16 tx_consumer;
2154 volatile u16 rx_producer;
2156 volatile u16 rx_producer;
2157 volatile u16 tx_consumer;
2166 struct tg3_hw_stats {
2167 u8 __reserved0[0x400-0x300];
2169 /* Statistics maintained by Receive MAC. */
2170 tg3_stat64_t rx_octets;
2172 tg3_stat64_t rx_fragments;
2173 tg3_stat64_t rx_ucast_packets;
2174 tg3_stat64_t rx_mcast_packets;
2175 tg3_stat64_t rx_bcast_packets;
2176 tg3_stat64_t rx_fcs_errors;
2177 tg3_stat64_t rx_align_errors;
2178 tg3_stat64_t rx_xon_pause_rcvd;
2179 tg3_stat64_t rx_xoff_pause_rcvd;
2180 tg3_stat64_t rx_mac_ctrl_rcvd;
2181 tg3_stat64_t rx_xoff_entered;
2182 tg3_stat64_t rx_frame_too_long_errors;
2183 tg3_stat64_t rx_jabbers;
2184 tg3_stat64_t rx_undersize_packets;
2185 tg3_stat64_t rx_in_length_errors;
2186 tg3_stat64_t rx_out_length_errors;
2187 tg3_stat64_t rx_64_or_less_octet_packets;
2188 tg3_stat64_t rx_65_to_127_octet_packets;
2189 tg3_stat64_t rx_128_to_255_octet_packets;
2190 tg3_stat64_t rx_256_to_511_octet_packets;
2191 tg3_stat64_t rx_512_to_1023_octet_packets;
2192 tg3_stat64_t rx_1024_to_1522_octet_packets;
2193 tg3_stat64_t rx_1523_to_2047_octet_packets;
2194 tg3_stat64_t rx_2048_to_4095_octet_packets;
2195 tg3_stat64_t rx_4096_to_8191_octet_packets;
2196 tg3_stat64_t rx_8192_to_9022_octet_packets;
2200 /* Statistics maintained by Transmit MAC. */
2201 tg3_stat64_t tx_octets;
2203 tg3_stat64_t tx_collisions;
2204 tg3_stat64_t tx_xon_sent;
2205 tg3_stat64_t tx_xoff_sent;
2206 tg3_stat64_t tx_flow_control;
2207 tg3_stat64_t tx_mac_errors;
2208 tg3_stat64_t tx_single_collisions;
2209 tg3_stat64_t tx_mult_collisions;
2210 tg3_stat64_t tx_deferred;
2212 tg3_stat64_t tx_excessive_collisions;
2213 tg3_stat64_t tx_late_collisions;
2214 tg3_stat64_t tx_collide_2times;
2215 tg3_stat64_t tx_collide_3times;
2216 tg3_stat64_t tx_collide_4times;
2217 tg3_stat64_t tx_collide_5times;
2218 tg3_stat64_t tx_collide_6times;
2219 tg3_stat64_t tx_collide_7times;
2220 tg3_stat64_t tx_collide_8times;
2221 tg3_stat64_t tx_collide_9times;
2222 tg3_stat64_t tx_collide_10times;
2223 tg3_stat64_t tx_collide_11times;
2224 tg3_stat64_t tx_collide_12times;
2225 tg3_stat64_t tx_collide_13times;
2226 tg3_stat64_t tx_collide_14times;
2227 tg3_stat64_t tx_collide_15times;
2228 tg3_stat64_t tx_ucast_packets;
2229 tg3_stat64_t tx_mcast_packets;
2230 tg3_stat64_t tx_bcast_packets;
2231 tg3_stat64_t tx_carrier_sense_errors;
2232 tg3_stat64_t tx_discards;
2233 tg3_stat64_t tx_errors;
2237 /* Statistics maintained by Receive List Placement. */
2238 tg3_stat64_t COS_rx_packets[16];
2239 tg3_stat64_t COS_rx_filter_dropped;
2240 tg3_stat64_t dma_writeq_full;
2241 tg3_stat64_t dma_write_prioq_full;
2242 tg3_stat64_t rxbds_empty;
2243 tg3_stat64_t rx_discards;
2244 tg3_stat64_t rx_errors;
2245 tg3_stat64_t rx_threshold_hit;
2249 /* Statistics maintained by Send Data Initiator. */
2250 tg3_stat64_t COS_out_packets[16];
2251 tg3_stat64_t dma_readq_full;
2252 tg3_stat64_t dma_read_prioq_full;
2253 tg3_stat64_t tx_comp_queue_full;
2255 /* Statistics maintained by Host Coalescing. */
2256 tg3_stat64_t ring_set_send_prod_index;
2257 tg3_stat64_t ring_status_update;
2258 tg3_stat64_t nic_irqs;
2259 tg3_stat64_t nic_avoided_irqs;
2260 tg3_stat64_t nic_tx_threshold_hit;
2262 u8 __reserved4[0xb00-0x9c0];
2265 /* 'mapping' is superfluous as the chip does not write into
2266 * the tx/rx post rings so we could just fetch it from there.
2267 * But the cache behavior is better how we are doing it now.
2270 struct sk_buff *skb;
2271 DECLARE_PCI_UNMAP_ADDR(mapping)
2274 struct tx_ring_info {
2275 struct sk_buff *skb;
2276 DECLARE_PCI_UNMAP_ADDR(mapping)
2280 struct tg3_config_info {
2284 struct tg3_link_config {
2285 /* Describes what we're trying to get. */
2291 /* Describes what we actually have. */
2294 #define SPEED_INVALID 0xffff
2295 #define DUPLEX_INVALID 0xff
2296 #define AUTONEG_INVALID 0xff
2298 /* When we go in and out of low power mode we need
2299 * to swap with this state.
2301 int phy_is_low_power;
2307 struct tg3_bufmgr_config {
2308 u32 mbuf_read_dma_low_water;
2309 u32 mbuf_mac_rx_low_water;
2310 u32 mbuf_high_water;
2312 u32 mbuf_read_dma_low_water_jumbo;
2313 u32 mbuf_mac_rx_low_water_jumbo;
2314 u32 mbuf_high_water_jumbo;
2320 struct tg3_ethtool_stats {
2321 /* Statistics maintained by Receive MAC. */
2324 u64 rx_ucast_packets;
2325 u64 rx_mcast_packets;
2326 u64 rx_bcast_packets;
2328 u64 rx_align_errors;
2329 u64 rx_xon_pause_rcvd;
2330 u64 rx_xoff_pause_rcvd;
2331 u64 rx_mac_ctrl_rcvd;
2332 u64 rx_xoff_entered;
2333 u64 rx_frame_too_long_errors;
2335 u64 rx_undersize_packets;
2336 u64 rx_in_length_errors;
2337 u64 rx_out_length_errors;
2338 u64 rx_64_or_less_octet_packets;
2339 u64 rx_65_to_127_octet_packets;
2340 u64 rx_128_to_255_octet_packets;
2341 u64 rx_256_to_511_octet_packets;
2342 u64 rx_512_to_1023_octet_packets;
2343 u64 rx_1024_to_1522_octet_packets;
2344 u64 rx_1523_to_2047_octet_packets;
2345 u64 rx_2048_to_4095_octet_packets;
2346 u64 rx_4096_to_8191_octet_packets;
2347 u64 rx_8192_to_9022_octet_packets;
2349 /* Statistics maintained by Transmit MAC. */
2354 u64 tx_flow_control;
2356 u64 tx_single_collisions;
2357 u64 tx_mult_collisions;
2359 u64 tx_excessive_collisions;
2360 u64 tx_late_collisions;
2361 u64 tx_collide_2times;
2362 u64 tx_collide_3times;
2363 u64 tx_collide_4times;
2364 u64 tx_collide_5times;
2365 u64 tx_collide_6times;
2366 u64 tx_collide_7times;
2367 u64 tx_collide_8times;
2368 u64 tx_collide_9times;
2369 u64 tx_collide_10times;
2370 u64 tx_collide_11times;
2371 u64 tx_collide_12times;
2372 u64 tx_collide_13times;
2373 u64 tx_collide_14times;
2374 u64 tx_collide_15times;
2375 u64 tx_ucast_packets;
2376 u64 tx_mcast_packets;
2377 u64 tx_bcast_packets;
2378 u64 tx_carrier_sense_errors;
2382 /* Statistics maintained by Receive List Placement. */
2383 u64 dma_writeq_full;
2384 u64 dma_write_prioq_full;
2388 u64 rx_threshold_hit;
2390 /* Statistics maintained by Send Data Initiator. */
2392 u64 dma_read_prioq_full;
2393 u64 tx_comp_queue_full;
2395 /* Statistics maintained by Host Coalescing. */
2396 u64 ring_set_send_prod_index;
2397 u64 ring_status_update;
2399 u64 nic_avoided_irqs;
2400 u64 nic_tx_threshold_hit;
2404 /* begin "general, frequently-used members" cacheline section */
2406 /* If the IRQ handler (which runs lockless) needs to be
2407 * quiesced, the following bitmask state is used. The
2408 * SYNC flag is set by non-IRQ context code to initiate
2411 * When the IRQ handler notices that SYNC is set, it
2412 * disables interrupts and returns.
2414 * When all outstanding IRQ handlers have returned after
2415 * the SYNC flag has been set, the setter can be assured
2416 * that interrupts will no longer get run.
2418 * In this way all SMP driver locks are never acquired
2419 * in hw IRQ context, only sw IRQ context or lower.
2421 unsigned int irq_sync;
2423 /* SMP locking strategy:
2425 * lock: Held during reset, PHY access, timer, and when
2426 * updating tg3_flags and tg3_flags2.
2428 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2429 * netif_tx_lock when it needs to call
2432 * Both of these locks are to be held with BH safety.
2434 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2435 * are running lockless, it is necessary to completely
2436 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2437 * before reconfiguring the device.
2439 * indirect_lock: Held when accessing registers indirectly
2440 * with IRQ disabling.
2443 spinlock_t indirect_lock;
2445 u32 (*read32) (struct tg3 *, u32);
2446 void (*write32) (struct tg3 *, u32, u32);
2447 u32 (*read32_mbox) (struct tg3 *, u32);
2448 void (*write32_mbox) (struct tg3 *, u32,
2451 struct net_device *dev;
2452 struct pci_dev *pdev;
2454 struct tg3_hw_status *hw_status;
2455 dma_addr_t status_mapping;
2460 /* begin "tx thread" cacheline section */
2461 void (*write32_tx_mbox) (struct tg3 *, u32,
2467 struct tg3_tx_buffer_desc *tx_ring;
2468 struct tx_ring_info *tx_buffers;
2469 dma_addr_t tx_desc_mapping;
2471 /* begin "rx thread" cacheline section */
2472 void (*write32_rx_mbox) (struct tg3 *, u32,
2478 u32 rx_jumbo_pending;
2479 #if TG3_VLAN_TAG_USED
2480 struct vlan_group *vlgrp;
2483 struct tg3_rx_buffer_desc *rx_std;
2484 struct ring_info *rx_std_buffers;
2485 dma_addr_t rx_std_mapping;
2486 u32 rx_std_max_post;
2488 struct tg3_rx_buffer_desc *rx_jumbo;
2489 struct ring_info *rx_jumbo_buffers;
2490 dma_addr_t rx_jumbo_mapping;
2492 struct tg3_rx_buffer_desc *rx_rcb;
2493 dma_addr_t rx_rcb_mapping;
2497 /* begin "everything else" cacheline(s) section */
2498 struct net_device_stats net_stats;
2499 struct net_device_stats net_stats_prev;
2500 struct tg3_ethtool_stats estats;
2501 struct tg3_ethtool_stats estats_prev;
2503 unsigned long phy_crc_errors;
2507 #define TG3_FLAG_TAGGED_STATUS 0x00000001
2508 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2509 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
2510 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2511 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2512 #define TG3_FLAG_ENABLE_ASF 0x00000020
2513 #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
2514 #define TG3_FLAG_POLL_SERDES 0x00000080
2515 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2516 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2517 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2518 #define TG3_FLAG_WOL_ENABLE 0x00000800
2519 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2520 #define TG3_FLAG_NVRAM 0x00002000
2521 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2522 #define TG3_FLAG_RX_PAUSE 0x00008000
2523 #define TG3_FLAG_TX_PAUSE 0x00010000
2524 #define TG3_FLAG_PCIX_MODE 0x00020000
2525 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2526 #define TG3_FLAG_PCI_32BIT 0x00080000
2527 #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2528 #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2529 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2530 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2531 #define TG3_FLAG_10_100_ONLY 0x01000000
2532 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2533 #define TG3_FLAG_IN_RESET_TASK 0x04000000
2534 #define TG3_FLAG_40BIT_DMA_BUG 0x08000000
2535 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
2536 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
2537 #define TG3_FLAG_SPLIT_MODE 0x40000000
2538 #define TG3_FLAG_INIT_COMPLETE 0x80000000
2540 #define TG3_FLG2_RESTART_TIMER 0x00000001
2541 #define TG3_FLG2_HW_TSO_1_BUG 0x00000002
2542 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2543 #define TG3_FLG2_IS_5788 0x00000008
2544 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
2545 #define TG3_FLG2_TSO_CAPABLE 0x00000020
2546 #define TG3_FLG2_PHY_ADC_BUG 0x00000040
2547 #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2548 #define TG3_FLG2_PHY_BER_BUG 0x00000100
2549 #define TG3_FLG2_PCI_EXPRESS 0x00000200
2550 #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2551 #define TG3_FLG2_HW_AUTONEG 0x00000800
2552 #define TG3_FLG2_PHY_JUST_INITTED 0x00001000
2553 #define TG3_FLG2_PHY_SERDES 0x00002000
2554 #define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2555 #define TG3_FLG2_FLASH 0x00008000
2556 #define TG3_FLG2_HW_TSO_1 0x00010000
2557 #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2558 #define TG3_FLG2_5705_PLUS 0x00040000
2559 #define TG3_FLG2_5750_PLUS 0x00080000
2560 #define TG3_FLG2_PROTECTED_NVRAM 0x00100000
2561 #define TG3_FLG2_USING_MSI 0x00200000
2562 #define TG3_FLG2_JUMBO_CAPABLE 0x00400000
2563 #define TG3_FLG2_MII_SERDES 0x00800000
2564 #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2565 TG3_FLG2_MII_SERDES)
2566 #define TG3_FLG2_PARALLEL_DETECT 0x01000000
2567 #define TG3_FLG2_ICH_WORKAROUND 0x02000000
2568 #define TG3_FLG2_5780_CLASS 0x04000000
2569 #define TG3_FLG2_HW_TSO_2 0x08000000
2570 #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2571 #define TG3_FLG2_1SHOT_MSI 0x10000000
2572 #define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2573 #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2575 u32 split_mode_max_reqs;
2576 #define SPLIT_MODE_5704_MAX_REQ 3
2578 struct timer_list timer;
2580 u16 timer_multiplier;
2585 struct tg3_link_config link_config;
2586 struct tg3_bufmgr_config bufmgr_config;
2588 /* cache h/w values, often passed straight to h/w */
2600 u16 pci_chip_rev_id;
2601 u8 pci_cacheline_sz;
2605 u32 pci_cfg_state[64 / sizeof(u32)];
2612 #define PHY_ID_MASK 0xfffffff0
2613 #define PHY_ID_BCM5400 0x60008040
2614 #define PHY_ID_BCM5401 0x60008050
2615 #define PHY_ID_BCM5411 0x60008070
2616 #define PHY_ID_BCM5701 0x60008110
2617 #define PHY_ID_BCM5703 0x60008160
2618 #define PHY_ID_BCM5704 0x60008190
2619 #define PHY_ID_BCM5705 0x600081a0
2620 #define PHY_ID_BCM5750 0x60008180
2621 #define PHY_ID_BCM5752 0x60008100
2622 #define PHY_ID_BCM5714 0x60008340
2623 #define PHY_ID_BCM5780 0x60008350
2624 #define PHY_ID_BCM5755 0xbc050cc0
2625 #define PHY_ID_BCM5787 0xbc050ce0
2626 #define PHY_ID_BCM8002 0x60010140
2627 #define PHY_ID_INVALID 0xffffffff
2628 #define PHY_ID_REV_MASK 0x0000000f
2629 #define PHY_REV_BCM5401_B0 0x1
2630 #define PHY_REV_BCM5401_B2 0x3
2631 #define PHY_REV_BCM5401_C0 0x6
2632 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2636 char board_part_number[24];
2638 u32 nic_sram_data_cfg;
2640 struct pci_dev *pdev_peer;
2642 /* This macro assumes the passed PHY ID is already masked
2645 #define KNOWN_PHY_ID(X) \
2646 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2647 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2648 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2649 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2650 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2651 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2652 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)
2654 struct tg3_hw_stats *hw_stats;
2655 dma_addr_t stats_mapping;
2656 struct work_struct reset_task;
2663 #define JEDEC_ATMEL 0x1f
2664 #define JEDEC_ST 0x20
2665 #define JEDEC_SAIFUN 0x4f
2666 #define JEDEC_SST 0xbf
2668 #define ATMEL_AT24C64_CHIP_SIZE (64 * 1024)
2669 #define ATMEL_AT24C64_PAGE_SIZE (32)
2671 #define ATMEL_AT24C512_CHIP_SIZE (512 * 1024)
2672 #define ATMEL_AT24C512_PAGE_SIZE (128)
2674 #define ATMEL_AT45DB0X1B_PAGE_POS 9
2675 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2677 #define ATMEL_AT25F512_PAGE_SIZE 256
2679 #define ST_M45PEX0_PAGE_SIZE 256
2681 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
2683 #define SST_25VF0X0_PAGE_SIZE 4098
2685 struct ethtool_coalesce coal;
2688 #endif /* !(_T3_H) */