2 * Hitachi SCA HD64570 and HD64572 common driver for Linux
4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * Sources of information:
11 * Hitachi HD64570 SCA User's Manual
12 * Hitachi HD64572 SCA-II User's Manual
14 * We use the following SCA memory map:
16 * Packet buffer descriptor rings - starting from winbase or win0base:
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
19 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
20 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
22 * Packet data buffers - starting from winbase + buff_offset:
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
25 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
26 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/jiffies.h>
33 #include <linux/types.h>
34 #include <linux/fcntl.h>
35 #include <linux/interrupt.h>
37 #include <linux/string.h>
38 #include <linux/errno.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
42 #include <asm/system.h>
43 #include <asm/bitops.h>
44 #include <asm/uaccess.h>
47 #include <linux/netdevice.h>
48 #include <linux/skbuff.h>
50 #include <linux/hdlc.h>
52 #if (!defined (__HD64570_H) && !defined (__HD64572_H)) || \
53 (defined (__HD64570_H) && defined (__HD64572_H))
54 #error Either hd64570.h or hd64572.h must be included
57 #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
58 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
59 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
61 #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
62 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
63 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
65 #ifdef __HD64570_H /* HD64570 */
66 #define sca_outa(value, reg, card) sca_outw(value, reg, card)
67 #define sca_ina(reg, card) sca_inw(reg, card)
68 #define writea(value, ptr) writew(value, ptr)
71 #define sca_outa(value, reg, card) sca_outl(value, reg, card)
72 #define sca_ina(reg, card) sca_inl(reg, card)
73 #define writea(value, ptr) writel(value, ptr)
76 static inline struct net_device *port_to_dev(port_t *port)
81 static inline int sca_intr_status(card_t *card)
85 #ifdef __HD64570_H /* HD64570 */
86 u8 isr0 = sca_in(ISR0, card);
87 u8 isr1 = sca_in(ISR1, card);
89 if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
90 if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
91 if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
92 if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
93 if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
94 if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
97 u32 isr0 = sca_inl(ISR0, card);
99 if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0);
100 if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0);
101 if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1);
102 if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1);
103 if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0);
104 if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1);
106 #endif /* HD64570 vs HD64572 */
108 if (!(result & SCA_INTR_DMAC_TX(0)))
109 if (sca_in(DSR_TX(0), card) & DSR_EOM)
110 result |= SCA_INTR_DMAC_TX(0);
111 if (!(result & SCA_INTR_DMAC_TX(1)))
112 if (sca_in(DSR_TX(1), card) & DSR_EOM)
113 result |= SCA_INTR_DMAC_TX(1);
118 static inline port_t* dev_to_port(struct net_device *dev)
120 return dev_to_hdlc(dev)->priv;
123 static inline u16 next_desc(port_t *port, u16 desc, int transmit)
125 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
126 : port_to_card(port)->rx_ring_buffers);
131 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
133 u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
134 u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
136 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
137 return log_node(port) * (rx_buffs + tx_buffs) +
138 transmit * rx_buffs + desc;
143 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
145 /* Descriptor offset always fits in 16 bytes */
146 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
151 static inline pkt_desc* desc_address(port_t *port, u16 desc, int transmit)
153 #ifdef PAGE0_ALWAYS_MAPPED
154 return (pkt_desc*)(win0base(port_to_card(port))
155 + desc_offset(port, desc, transmit));
157 return (pkt_desc*)(winbase(port_to_card(port))
158 + desc_offset(port, desc, transmit));
164 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
166 return port_to_card(port)->buff_offset +
167 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
172 static void sca_init_sync_port(port_t *port)
174 card_t *card = port_to_card(port);
181 #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
185 for (transmit = 0; transmit < 2; transmit++) {
186 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
187 u16 buffs = transmit ? card->tx_ring_buffers
188 : card->rx_ring_buffers;
190 for (i = 0; i < buffs; i++) {
191 pkt_desc* desc = desc_address(port, i, transmit);
192 u16 chain_off = desc_offset(port, i + 1, transmit);
193 u32 buff_off = buffer_offset(port, i, transmit);
195 writea(chain_off, &desc->cp);
196 writel(buff_off, &desc->bp);
197 writew(0, &desc->len);
198 writeb(0, &desc->stat);
201 /* DMA disable - to halt state */
202 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
203 DSR_RX(phy_node(port)), card);
204 /* software ABORT - to initial state */
205 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
206 DCR_RX(phy_node(port)), card);
209 sca_out(0, dmac + CPB, card); /* pointer base */
211 /* current desc addr */
212 sca_outa(desc_offset(port, 0, transmit), dmac + CDAL, card);
214 sca_outa(desc_offset(port, buffs - 1, transmit),
217 sca_outa(desc_offset(port, 0, transmit), dmac + EDAL,
220 /* clear frame end interrupt counter */
221 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
222 DCR_RX(phy_node(port)), card);
224 if (!transmit) { /* Receive */
225 /* set buffer length */
226 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
227 /* Chain mode, Multi-frame */
228 sca_out(0x14, DMR_RX(phy_node(port)), card);
229 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
232 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
233 } else { /* Transmit */
234 /* Chain mode, Multi-frame */
235 sca_out(0x14, DMR_TX(phy_node(port)), card);
236 /* enable underflow interrupts */
237 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
241 hdlc_set_carrier(!(sca_in(get_msci(port) + ST3, card) & ST3_DCD),
247 #ifdef NEED_SCA_MSCI_INTR
248 /* MSCI interrupt service */
249 static inline void sca_msci_intr(port_t *port)
251 u16 msci = get_msci(port);
252 card_t* card = port_to_card(port);
253 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
255 /* Reset MSCI TX underrun and CDCD status bit */
256 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
258 if (stat & ST1_UDRN) {
259 struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
260 stats->tx_errors++; /* TX Underrun error detected */
261 stats->tx_fifo_errors++;
265 hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD),
272 static inline void sca_rx(card_t *card, port_t *port, pkt_desc *desc, u16 rxin)
274 struct net_device *dev = port_to_dev(port);
275 struct net_device_stats *stats = hdlc_stats(dev);
279 #ifndef ALL_PAGES_ALWAYS_MAPPED
284 len = readw(&desc->len);
285 skb = dev_alloc_skb(len);
291 buff = buffer_offset(port, rxin, 0);
292 #ifndef ALL_PAGES_ALWAYS_MAPPED
293 page = buff / winsize(card);
294 buff = buff % winsize(card);
295 maxlen = winsize(card) - buff;
300 memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
301 openwin(card, page + 1);
302 memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
305 memcpy_fromio(skb->data, winbase(card) + buff, len);
307 #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
308 /* select pkt_desc table page back */
313 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
317 stats->rx_bytes += skb->len;
318 skb->mac.raw = skb->data;
320 skb->dev->last_rx = jiffies;
321 skb->protocol = hdlc_type_trans(skb, dev);
327 /* Receive DMA interrupt service */
328 static inline void sca_rx_intr(port_t *port)
330 u16 dmac = get_dmac_rx(port);
331 card_t *card = port_to_card(port);
332 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
333 struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
335 /* Reset DSR status bits */
336 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
337 DSR_RX(phy_node(port)), card);
340 stats->rx_over_errors++; /* Dropped one or more frames */
343 u32 desc_off = desc_offset(port, port->rxin, 0);
345 u32 cda = sca_ina(dmac + CDAL, card);
347 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
348 break; /* No frame received */
350 desc = desc_address(port, port->rxin, 0);
351 stat = readb(&desc->stat);
352 if (!(stat & ST_RX_EOM))
353 port->rxpart = 1; /* partial frame received */
354 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
356 if (stat & ST_RX_OVERRUN) stats->rx_fifo_errors++;
357 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
358 ST_RX_RESBIT)) || port->rxpart)
359 stats->rx_frame_errors++;
360 else if (stat & ST_RX_CRC) stats->rx_crc_errors++;
361 if (stat & ST_RX_EOM)
362 port->rxpart = 0; /* received last fragment */
364 sca_rx(card, port, desc, port->rxin);
366 /* Set new error descriptor address */
367 sca_outa(desc_off, dmac + EDAL, card);
368 port->rxin = next_desc(port, port->rxin, 0);
371 /* make sure RX DMA is enabled */
372 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
377 /* Transmit DMA interrupt service */
378 static inline void sca_tx_intr(port_t *port)
380 struct net_device *dev = port_to_dev(port);
381 struct net_device_stats *stats = hdlc_stats(dev);
382 u16 dmac = get_dmac_tx(port);
383 card_t* card = port_to_card(port);
386 spin_lock(&port->lock);
388 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
390 /* Reset DSR status bits */
391 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
392 DSR_TX(phy_node(port)), card);
397 u32 desc_off = desc_offset(port, port->txlast, 1);
398 u32 cda = sca_ina(dmac + CDAL, card);
399 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
400 break; /* Transmitter is/will_be sending this frame */
402 desc = desc_address(port, port->txlast, 1);
404 stats->tx_bytes += readw(&desc->len);
405 writeb(0, &desc->stat); /* Free descriptor */
406 port->txlast = next_desc(port, port->txlast, 1);
409 netif_wake_queue(dev);
410 spin_unlock(&port->lock);
415 static irqreturn_t sca_intr(int irq, void* dev_id, struct pt_regs *regs)
417 card_t *card = dev_id;
422 #ifndef ALL_PAGES_ALWAYS_MAPPED
423 u8 page = sca_get_page(card);
426 while((stat = sca_intr_status(card)) != 0) {
428 for (i = 0; i < 2; i++) {
429 port_t *port = get_port(card, i);
431 if (stat & SCA_INTR_MSCI(i))
434 if (stat & SCA_INTR_DMAC_RX(i))
437 if (stat & SCA_INTR_DMAC_TX(i))
443 #ifndef ALL_PAGES_ALWAYS_MAPPED
444 openwin(card, page); /* Restore original page */
446 return IRQ_RETVAL(handled);
451 static void sca_set_port(port_t *port)
453 card_t* card = port_to_card(port);
454 u16 msci = get_msci(port);
455 u8 md2 = sca_in(msci + MD2, card);
456 unsigned int tmc, br = 10, brv = 1024;
459 if (port->settings.clock_rate > 0) {
460 /* Try lower br for better accuracy*/
463 brv >>= 1; /* brv = 2^9 = 512 max in specs */
465 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
466 tmc = CLOCK_BASE / (brv * port->settings.clock_rate);
467 }while(br > 1 && tmc <= 128);
471 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
473 } else if (tmc > 255)
474 tmc = 256; /* tmc=0 means 256 - low baud rates */
476 port->settings.clock_rate = CLOCK_BASE / (brv * tmc);
478 br = 9; /* Minimum clock rate */
479 tmc = 256; /* 8bit = 0 */
480 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
483 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
484 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
487 /* baud divisor - time constant*/
489 sca_out(port->tmc, msci + TMC, card);
491 sca_out(port->tmc, msci + TMCR, card);
492 sca_out(port->tmc, msci + TMCT, card);
496 sca_out(port->rxs, msci + RXS, card);
497 sca_out(port->txs, msci + TXS, card);
499 if (port->settings.loopback)
502 md2 &= ~MD2_LOOPBACK;
504 sca_out(md2, msci + MD2, card);
510 static void sca_open(struct net_device *dev)
512 port_t *port = dev_to_port(dev);
513 card_t* card = port_to_card(port);
514 u16 msci = get_msci(port);
517 switch(port->encoding) {
518 case ENCODING_NRZ: md2 = MD2_NRZ; break;
519 case ENCODING_NRZI: md2 = MD2_NRZI; break;
520 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
521 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
522 default: md2 = MD2_MANCHESTER;
525 if (port->settings.loopback)
528 switch(port->parity) {
529 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
530 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
532 case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
534 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
536 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
537 default: md0 = MD0_HDLC | MD0_CRC_NONE;
540 sca_out(CMD_RESET, msci + CMD, card);
541 sca_out(md0, msci + MD0, card);
542 sca_out(0x00, msci + MD1, card); /* no address field check */
543 sca_out(md2, msci + MD2, card);
544 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
546 sca_out(CTL_IDLE, msci + CTL, card);
548 /* Skip the rest of underrun frame */
549 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
553 /* Allow at least 8 bytes before requesting RX DMA operation */
554 /* TX with higher priority and possibly with shorter transfers */
555 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
556 sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
557 sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
559 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
560 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
561 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
562 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
563 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
566 /* We're using the following interrupts:
567 - TXINT (DMAC completed all transmisions, underrun or DCD change)
571 hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), dev);
574 /* MSCI TX INT and RX INT A IRQ enable */
575 sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
576 sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
577 sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
578 IER0, card); /* TXINT and RXINT */
580 sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
583 /* MSCI TXINT and RXINTA interrupt enable */
584 sca_outl(IE0_TXINT | IE0_RXINTA | IE0_UDRN | IE0_CDCD, msci + IE0,
586 /* DMA & MSCI IRQ enable */
587 sca_outl(sca_inl(IER0, card) |
588 (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, card);
592 sca_out(port->tmc, msci + TMC, card); /* Restore registers */
594 sca_out(port->tmc, msci + TMCR, card);
595 sca_out(port->tmc, msci + TMCT, card);
597 sca_out(port->rxs, msci + RXS, card);
598 sca_out(port->txs, msci + TXS, card);
599 sca_out(CMD_TX_ENABLE, msci + CMD, card);
600 sca_out(CMD_RX_ENABLE, msci + CMD, card);
602 netif_start_queue(dev);
607 static void sca_close(struct net_device *dev)
609 port_t *port = dev_to_port(dev);
610 card_t* card = port_to_card(port);
613 netif_stop_queue(dev);
614 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
616 /* disable MSCI interrupts */
617 sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
619 /* disable DMA interrupts */
620 sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
623 /* disable DMA & MSCI IRQ */
624 sca_outl(sca_inl(IER0, card) &
625 (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, card);
631 static int sca_attach(struct net_device *dev, unsigned short encoding,
632 unsigned short parity)
634 if (encoding != ENCODING_NRZ &&
635 encoding != ENCODING_NRZI &&
636 encoding != ENCODING_FM_MARK &&
637 encoding != ENCODING_FM_SPACE &&
638 encoding != ENCODING_MANCHESTER)
641 if (parity != PARITY_NONE &&
642 parity != PARITY_CRC16_PR0 &&
643 parity != PARITY_CRC16_PR1 &&
645 parity != PARITY_CRC16_PR0_CCITT &&
647 parity != PARITY_CRC32_PR1_CCITT &&
649 parity != PARITY_CRC16_PR1_CCITT)
652 dev_to_port(dev)->encoding = encoding;
653 dev_to_port(dev)->parity = parity;
660 static void sca_dump_rings(struct net_device *dev)
662 port_t *port = dev_to_port(dev);
663 card_t *card = port_to_card(port);
665 #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
669 #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
670 page = sca_get_page(card);
674 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
675 sca_ina(get_dmac_rx(port) + CDAL, card),
676 sca_ina(get_dmac_rx(port) + EDAL, card),
677 sca_in(DSR_RX(phy_node(port)), card), port->rxin,
678 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE?"":"in");
679 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
680 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
682 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
684 sca_ina(get_dmac_tx(port) + CDAL, card),
685 sca_ina(get_dmac_tx(port) + EDAL, card),
686 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
687 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
689 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
690 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
693 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, "
694 "ST: %02x %02x %02x %02x"
698 ", FST: %02x CST: %02x %02x\n",
699 sca_in(get_msci(port) + MD0, card),
700 sca_in(get_msci(port) + MD1, card),
701 sca_in(get_msci(port) + MD2, card),
702 sca_in(get_msci(port) + ST0, card),
703 sca_in(get_msci(port) + ST1, card),
704 sca_in(get_msci(port) + ST2, card),
705 sca_in(get_msci(port) + ST3, card),
707 sca_in(get_msci(port) + ST4, card),
709 sca_in(get_msci(port) + FST, card),
710 sca_in(get_msci(port) + CST0, card),
711 sca_in(get_msci(port) + CST1, card));
714 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
715 sca_inl(ISR0, card), sca_inl(ISR1, card));
717 printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
718 sca_in(ISR1, card), sca_in(ISR2, card));
721 #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
722 openwin(card, page); /* Restore original page */
725 #endif /* DEBUG_RINGS */
729 static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
731 port_t *port = dev_to_port(dev);
732 card_t *card = port_to_card(port);
735 #ifndef ALL_PAGES_ALWAYS_MAPPED
740 spin_lock_irq(&port->lock);
742 desc = desc_address(port, port->txin + 1, 1);
743 if (readb(&desc->stat)) { /* allow 1 packet gap */
744 /* should never happen - previous xmit should stop queue */
746 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
748 netif_stop_queue(dev);
749 spin_unlock_irq(&port->lock);
750 return 1; /* request packet to be queued */
754 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
758 desc = desc_address(port, port->txin, 1);
759 buff = buffer_offset(port, port->txin, 1);
761 #ifndef ALL_PAGES_ALWAYS_MAPPED
762 page = buff / winsize(card);
763 buff = buff % winsize(card);
764 maxlen = winsize(card) - buff;
768 memcpy_toio(winbase(card) + buff, skb->data, maxlen);
769 openwin(card, page + 1);
770 memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
774 memcpy_toio(winbase(card) + buff, skb->data, len);
776 #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
777 openwin(card, 0); /* select pkt_desc table page back */
779 writew(len, &desc->len);
780 writeb(ST_TX_EOM, &desc->stat);
781 dev->trans_start = jiffies;
783 port->txin = next_desc(port, port->txin, 1);
784 sca_outa(desc_offset(port, port->txin, 1),
785 get_dmac_tx(port) + EDAL, card);
787 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
789 desc = desc_address(port, port->txin + 1, 1);
790 if (readb(&desc->stat)) /* allow 1 packet gap */
791 netif_stop_queue(dev);
793 spin_unlock_irq(&port->lock);
801 #ifdef NEED_DETECT_RAM
802 static u32 __devinit sca_detect_ram(card_t *card, u8 *rambase, u32 ramsize)
804 /* Round RAM size to 32 bits, fill from end to start */
805 u32 i = ramsize &= ~3;
807 #ifndef ALL_PAGES_ALWAYS_MAPPED
808 u32 size = winsize(card);
810 openwin(card, (i - 4) / size); /* select last window */
814 #ifndef ALL_PAGES_ALWAYS_MAPPED
815 if ((i + 4) % size == 0)
816 openwin(card, i / size);
817 writel(i ^ 0x12345678, rambase + i % size);
819 writel(i ^ 0x12345678, rambase + i);
823 for (i = 0; i < ramsize ; i += 4) {
824 #ifndef ALL_PAGES_ALWAYS_MAPPED
826 openwin(card, i / size);
828 if (readl(rambase + i % size) != (i ^ 0x12345678))
831 if (readl(rambase + i) != (i ^ 0x12345678))
838 #endif /* NEED_DETECT_RAM */
842 static void __devinit sca_init(card_t *card, int wait_states)
844 sca_out(wait_states, WCRL, card); /* Wait Control */
845 sca_out(wait_states, WCRM, card);
846 sca_out(wait_states, WCRH, card);
848 sca_out(0, DMER, card); /* DMA Master disable */
849 sca_out(0x03, PCR, card); /* DMA priority */
850 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
851 sca_out(0, DSR_TX(0), card);
852 sca_out(0, DSR_RX(1), card);
853 sca_out(0, DSR_TX(1), card);
854 sca_out(DMER_DME, DMER, card); /* DMA Master enable */