3 ** PCI Lower Bus Adapter (LBA) manager
5 ** (c) Copyright 1999,2000 Grant Grundler
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
8 ** This program is free software; you can redistribute it and/or modify
9 ** it under the terms of the GNU General Public License as published by
10 ** the Free Software Foundation; either version 2 of the License, or
11 ** (at your option) any later version.
14 ** This module primarily provides access to PCI bus (config/IOport
15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
16 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
18 ** LBA driver isn't as simple as the Dino driver because:
19 ** (a) this chip has substantial bug fixes between revisions
20 ** (Only one Dino bug has a software workaround :^( )
21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
24 ** (dino only deals with "Legacy" PDC)
26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
27 ** (I/O SAPIC is integratd in the LBA chip).
29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
30 ** FIXME: Add support for PCI card hot-plug (OLARD).
33 #include <linux/delay.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/spinlock.h>
37 #include <linux/init.h> /* for __init and __devinit */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/smp_lock.h>
43 #include <asm/byteorder.h>
44 #include <asm/irq.h> /* for struct irq_region support */
46 #include <asm/pdcpat.h>
48 #include <asm/segment.h>
49 #include <asm/system.h>
51 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
52 #include <asm/parisc-device.h>
53 #include <asm/iosapic.h> /* for iosapic_register() */
54 #include <asm/io.h> /* read/write stuff */
58 #define FALSE (1 == 0)
61 #undef DEBUG_LBA /* general stuff */
62 #undef DEBUG_LBA_PORT /* debug I/O Port access */
63 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
64 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
66 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
70 #define DBG(x...) printk(x)
76 #define DBG_PORT(x...) printk(x)
78 #define DBG_PORT(x...)
82 #define DBG_CFG(x...) printk(x)
88 #define DBG_PAT(x...) printk(x)
95 #define ASSERT(expr) \
97 printk("\n%s:%d: Assertion " #expr " failed!\n", \
98 __FILE__, __LINE__); \
107 ** Config accessor functions only pass in the 8-bit bus number and not
108 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
109 ** number based on what firmware wrote into the scratch register.
111 ** The "secondary" bus number is set to this before calling
112 ** pci_register_ops(). If any PPB's are present, the scan will
113 ** discover them and update the "secondary" and "subordinate"
114 ** fields in the pci_bus structure.
116 ** Changes in the configuration *may* result in a different
117 ** bus number for each LBA depending on what firmware does.
120 #define MODULE_NAME "LBA"
122 #define LBA_FUNC_ID 0x0000 /* function id */
123 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
124 #define LBA_CAPABLE 0x0030 /* capabilities register */
126 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
127 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
129 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
130 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
131 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
133 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
134 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
135 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
136 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
138 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
140 #define LBA_STAT_CTL 0x0108 /* Status & Control */
141 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
142 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
143 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
144 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
146 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
147 #define LBA_LMMIO_MASK 0x0208
149 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
150 #define LBA_GMMIO_MASK 0x0218
152 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
153 #define LBA_WLMMIO_MASK 0x0228
155 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
156 #define LBA_WGMMIO_MASK 0x0238
158 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
159 #define LBA_IOS_MASK 0x0248
161 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
162 #define LBA_ELMMIO_MASK 0x0258
164 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
165 #define LBA_EIOS_MASK 0x0268
167 #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
168 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
170 #define LBA_IBASE 0x0300 /* SBA DMA support */
171 #define LBA_IMASK 0x0308
173 /* FIXME: ignore DMA Hint stuff until we can measure performance */
174 #define LBA_HINT_CFG 0x0310
175 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
177 #define LBA_BUS_MODE 0x0620
179 /* ERROR regs are needed for config cycle kluges */
180 #define LBA_ERROR_CONFIG 0x0680
181 #define LBA_SMART_MODE 0x20
182 #define LBA_ERROR_STATUS 0x0688
183 #define LBA_ROPE_CTL 0x06A0
185 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
187 /* non-postable I/O port space, densely packed */
188 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
190 #define ELROY_HVERS 0x782
191 #define MERCURY_HVERS 0x783
192 #define QUICKSILVER_HVERS 0x784
194 static inline int IS_ELROY(struct parisc_device *d)
196 return (d->id.hversion == ELROY_HVERS);
199 static inline int IS_MERCURY(struct parisc_device *d)
201 return (d->id.hversion == MERCURY_HVERS);
204 static inline int IS_QUICKSILVER(struct parisc_device *d)
206 return (d->id.hversion == QUICKSILVER_HVERS);
211 ** lba_device: Per instance Elroy data structure
214 struct pci_hba_data hba;
219 #ifdef CONFIG_PARISC64
220 unsigned long iop_base; /* PA_VIEW - for IO port accessor funcs */
223 int flags; /* state/functionality enabled */
224 int hw_rev; /* HW revision of chip */
233 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
234 #define LBA_FLAG_SKIP_PROBE 0x10
236 /* Tape Release 4 == hw_rev 5 */
237 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
238 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
239 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
242 /* Looks nice and keeps the compiler happy */
243 #define LBA_DEV(d) ((struct lba_device *) (d))
247 ** Only allow 8 subsidiary busses per LBA
248 ** Problem is the PCI bus numbering is globally shared.
250 #define LBA_MAX_NUM_BUSES 8
252 /************************************
253 * LBA register read and write support
255 * BE WARNED: register writes are posted.
256 * (ie follow writes which must reach HW with a read)
258 #define READ_U8(addr) __raw_readb(addr)
259 #define READ_U16(addr) __raw_readw(addr)
260 #define READ_U32(addr) __raw_readl(addr)
261 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
262 #define WRITE_U16(value, addr) __raw_writew(value, addr)
263 #define WRITE_U32(value, addr) __raw_writel(value, addr)
265 #define READ_REG8(addr) readb(addr)
266 #define READ_REG16(addr) readw(addr)
267 #define READ_REG32(addr) readl(addr)
268 #define READ_REG64(addr) readq(addr)
269 #define WRITE_REG8(value, addr) writeb(value, addr)
270 #define WRITE_REG16(value, addr) writew(value, addr)
271 #define WRITE_REG32(value, addr) writel(value, addr)
274 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
275 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
276 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
277 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
281 ** Extract LBA (Rope) number from HPA
282 ** REVISIT: 16 ropes for Stretch/Ike?
284 #define ROPES_PER_IOC 8
285 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
289 lba_dump_res(struct resource *r, int d)
296 printk(KERN_DEBUG "(%p)", r->parent);
297 for (i = d; i ; --i) printk(" ");
298 printk(KERN_DEBUG "%p [%lx,%lx]/%x\n", r, r->start, r->end, (int) r->flags);
299 lba_dump_res(r->child, d+2);
300 lba_dump_res(r->sibling, d);
305 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
306 ** workaround for cfg cycles:
307 ** -- preserve LBA state
308 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
309 ** -- turn on smart mode
310 ** -- probe with config writes before doing config reads
311 ** -- check ERROR_STATUS
312 ** -- clear ERROR_STATUS
313 ** -- restore LBA state
315 ** The workaround is only used for device discovery.
319 lba_device_present( u8 bus, u8 dfn, struct lba_device *d)
321 u8 first_bus = d->hba.hba_bus->secondary;
322 u8 last_sub_bus = d->hba.hba_bus->subordinate;
324 ASSERT(bus >= first_bus);
325 ASSERT(bus <= last_sub_bus);
326 ASSERT((bus - first_bus) < LBA_MAX_NUM_BUSES);
328 if ((bus < first_bus) ||
329 (bus > last_sub_bus) ||
330 ((bus - first_bus) >= LBA_MAX_NUM_BUSES))
332 /* devices that fall into any of these cases won't get claimed */
341 #define LBA_CFG_SETUP(d, tok) { \
342 /* Save contents of error config register. */ \
343 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
345 /* Save contents of status control register. */ \
346 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
348 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
349 ** arbitration for full bus walks. \
351 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
352 /* Save contents of arb mask register. */ \
353 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
356 * Turn off all device arbitration bits (i.e. everything \
357 * except arbitration enable bit). \
359 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
363 * Set the smart mode bit so that master aborts don't cause \
364 * LBA to go into PCI fatal mode (required). \
366 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
370 #define LBA_CFG_PROBE(d, tok) { \
372 * Setup Vendor ID write and read back the address register \
373 * to make sure that LBA is the bus master. \
375 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
377 * Read address register to ensure that LBA is the bus master, \
378 * which implies that DMA traffic has stopped when DMA arb is off. \
380 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
382 * Generate a cfg write cycle (will have no affect on \
383 * Vendor ID register since read-only). \
385 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
387 * Make sure write has completed before proceeding further, \
388 * i.e. before setting clear enable. \
390 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
396 * -- Can't tell if config cycle got the error.
398 * OV bit is broken until rev 4.0, so can't use OV bit and
399 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
401 * As of rev 4.0, no longer need the error check.
403 * -- Even if we could tell, we still want to return -1
404 * for **ANY** error (not just master abort).
406 * -- Only clear non-fatal errors (we don't want to bring
407 * LBA out of pci-fatal mode).
409 * Actually, there is still a race in which
410 * we could be clearing a fatal error. We will
411 * live with this during our initial bus walk
412 * until rev 4.0 (no driver activity during
413 * initial bus walk). The initial bus walk
414 * has race conditions concerning the use of
415 * smart mode as well.
418 #define LBA_MASTER_ABORT_ERROR 0xc
419 #define LBA_FATAL_ERROR 0x10
421 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
422 u32 error_status = 0; \
424 * Set clear enable (CE) bit. Unset by HW when new \
425 * errors are logged -- LBA HW ERS section 14.3.3). \
427 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
428 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
429 if ((error_status & 0x1f) != 0) { \
431 * Fail the config read request. \
434 if ((error_status & LBA_FATAL_ERROR) == 0) { \
436 * Clear error status (if fatal bit not set) by setting \
437 * clear error log bit (CL). \
439 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
444 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
445 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
446 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR)
448 #define LBA_CFG_ADDR_SETUP(d, addr) { \
449 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
452 * -- Potentially could skip this once DMA bug fixed. \
454 * Read address register to ensure that LBA is the bus master, \
455 * which implies that DMA traffic has stopped when DMA arb is off. \
457 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
461 #define LBA_CFG_RESTORE(d, base) { \
463 * Restore status control register (turn off clear enable). \
465 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
467 * Restore error config register (turn off smart mode). \
469 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
470 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
472 * Restore arb mask register (reenables DMA arbitration). \
474 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
481 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
485 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
486 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
487 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
489 ASSERT((size == sizeof(u8)) ||
490 (size == sizeof(u16)) ||
491 (size == sizeof(u32)));
493 if ((size != sizeof(u8)) &&
494 (size != sizeof(u16)) &&
495 (size != sizeof(u32))) {
499 LBA_CFG_SETUP(d, tok);
500 LBA_CFG_PROBE(d, tok);
501 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
503 LBA_CFG_ADDR_SETUP(d, tok | reg);
506 data = (u32) READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 3));
509 data = (u32) READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 2));
512 data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
515 break; /* leave data as -1 */
518 LBA_CFG_RESTORE(d, d->hba.base_addr);
525 /* PAT PDC needs to be relocated in order to perform properly.
526 * tg3 driver does about 1600 PCI Cfg writes to initialize the card.
527 * On 440Mhz A500, PDC takes ~20ms/write, or ~30 seconds per card.
528 * On PA8800, that takes about 5ms/write (8 seconds).
529 * But relocating PDC will burn at least 4MB of RAM.
530 * Easier/Cheaper to just maintain our own mercury cfg ops.
532 #define pat_cfg_addr(bus, devfn, addr) (((bus) << 16) | ((devfn) << 8) | (addr))
534 static int pat_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
536 int tok = pat_cfg_addr(bus->number, devfn, pos);
538 int ret = pdc_pat_io_pci_cfg_read(tok, size, &tmp);
540 DBG_CFG("%s(%d:%d.%d+0x%02x) -> 0x%x %d\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, tmp, ret);
543 case 1: *data = (u8) tmp; return (tmp == (u8) ~0);
544 case 2: *data = (u16) tmp; return (tmp == (u16) ~0);
545 case 4: *data = (u32) tmp; return (tmp == (u32) ~0);
551 static int pat_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
553 int tok = pat_cfg_addr(bus->number, devfn, pos);
554 int ret = pdc_pat_io_pci_cfg_write(tok, size, data);
556 DBG_CFG("%s(%d:%d.%d+0x%02x, 0x%lx/%d)\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, data, size);
560 static struct pci_ops pat_cfg_ops = {
561 .read = pat_cfg_read,
562 .write = pat_cfg_write,
567 #ifdef CONFIG_PARISC64
568 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
570 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
571 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
572 u32 tok = LBA_CFG_TOK(local_bus, devfn);
575 ** Should only get here on fully working LBA rev.
576 ** This is how simple the original LBA code should have been.
578 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
580 case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA
582 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos,
584 return(*(u8 *)data == (u8) ~0U);
585 case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA
587 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos,
589 return(*(u16 *)data == (u16) ~0U);
590 case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
591 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
592 return(*data == ~0U);
594 DBG_CFG("%s(%x+%2x) -> bad size (%d)\n", __FUNCTION__, tok, pos, size);
596 return(!PCIBIOS_SUCCESSFUL); /* failed */
600 * LBA 4.0 config write code implements non-postable semantics
601 * by doing a read of CONFIG ADDR after the write.
604 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
606 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
607 unsigned long data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
608 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
609 u32 tok = LBA_CFG_TOK(local_bus,devfn);
611 ASSERT((tok & 0xff) == 0);
614 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data);
616 /* Basic Algorithm */
617 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
619 case 1: WRITE_REG8 (data, data_reg + (pos & 3)); break;
620 case 2: WRITE_REG16(data, data_reg + (pos & 2)); break;
621 case 4: WRITE_REG32(data, data_reg); break;
623 DBG_CFG("%s(%x+%2x) WTF! size %d\n", __FUNCTION__, tok, pos,
627 /* flush posted write */
628 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
629 return PCIBIOS_SUCCESSFUL;
633 static struct pci_ops mercury_cfg_ops = {
634 .read = mercury_cfg_read,
635 .write = mercury_cfg_write,
638 #define mercury_cfg_ops lba_cfg_ops
639 #endif /* CONFIG_PARISC64 */
642 static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
644 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
645 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
646 u32 tok = LBA_CFG_TOK(local_bus, devfn);
648 /* FIXME: B2K/C3600 workaround is always use old method... */
649 /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ {
650 /* original - Generate config cycle on broken elroy
651 with risk we will miss PCI bus errors. */
652 *data = lba_rd_cfg(d, tok, pos, size);
653 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
654 return(*data == ~0U);
657 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d)))
659 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
660 /* either don't want to look or know device isn't present. */
666 ** Should only get here on fully working LBA rev.
667 ** This is how simple the code should have been.
669 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
671 case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
673 case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
675 case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
678 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
679 return(*data == ~0U);
684 lba_wr_cfg( struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
688 u32 error_config = 0;
689 u32 status_control = 0;
691 ASSERT((size == sizeof(u8)) ||
692 (size == sizeof(u16)) ||
693 (size == sizeof(u32)));
695 if ((size != sizeof(u8)) &&
696 (size != sizeof(u16)) &&
697 (size != sizeof(u32))) {
701 LBA_CFG_SETUP(d, tok);
702 LBA_CFG_ADDR_SETUP(d, tok | reg);
705 WRITE_REG8((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA + (reg&3));
708 WRITE_REG16((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA +(reg&2));
711 WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
716 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
717 LBA_CFG_RESTORE(d, d->hba.base_addr);
722 * LBA 4.0 config write code implements non-postable semantics
723 * by doing a read of CONFIG ADDR after the write.
726 static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
728 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
729 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
730 u32 tok = LBA_CFG_TOK(local_bus,devfn);
732 ASSERT((tok & 0xff) == 0);
735 if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) {
736 /* Original Workaround */
737 lba_wr_cfg(d, tok, pos, (u32) data, size);
738 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
742 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
743 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
744 return 1; /* New Workaround */
747 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
749 /* Basic Algorithm */
750 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
752 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
754 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
756 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
759 /* flush posted write */
760 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
765 static struct pci_ops lba_cfg_ops = {
766 .read = lba_cfg_read,
767 .write = lba_cfg_write,
774 DBG(MODULE_NAME ": lba_bios_init\n");
778 #ifdef CONFIG_PARISC64
781 ** Determine if a device is already configured.
782 ** If so, reserve it resources.
784 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
785 ** PAT has to enable the devices it's using.
787 ** Note: resources are fixed up before we try to claim them.
790 lba_claim_dev_resources(struct pci_dev *dev)
795 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
797 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
798 if (cmd & PCI_COMMAND_MEMORY)
799 srch_flags |= IORESOURCE_MEM;
804 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
805 if (dev->resource[i].flags & srch_flags) {
806 pci_claim_resource(dev, i);
807 DBG(" claimed %s %d [%lx,%lx]/%x\n",
809 dev->resource[i].start,
810 dev->resource[i].end,
811 (int) dev->resource[i].flags
817 #define lba_claim_dev_resources(dev)
822 ** The algorithm is generic code.
823 ** But it needs to access local data structures to get the IRQ base.
824 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
827 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
828 ** Resources aren't allocated until recursive buswalk below HBA is completed.
831 lba_fixup_bus(struct pci_bus *bus)
833 struct list_head *ln;
837 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
838 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
840 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
841 bus, bus->secondary, bus->bridge->platform_data);
844 ** Properly Setup MMIO resources for this bus.
845 ** pci_alloc_primary_bus() mangles this.
849 pci_read_bridge_bases(bus);
851 /* Host-PCI Bridge */
854 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
855 ldev->hba.io_space.name,
856 ldev->hba.io_space.start, ldev->hba.io_space.end,
857 (int) ldev->hba.io_space.flags);
858 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
859 ldev->hba.lmmio_space.name,
860 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
861 (int) ldev->hba.lmmio_space.flags);
863 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
865 lba_dump_res(&ioport_resource, 2);
869 if (ldev->hba.elmmio_space.start) {
870 err = request_resource(&iomem_resource,
871 &(ldev->hba.elmmio_space));
874 printk("FAILED: lba_fixup_bus() request for "
875 "elmmio_space [%lx/%lx]\n",
876 ldev->hba.elmmio_space.start,
877 ldev->hba.elmmio_space.end);
879 /* lba_dump_res(&iomem_resource, 2); */
884 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
886 /* FIXME overlaps with elmmio will fail here.
887 * Need to prune (or disable) the distributed range.
889 * BEWARE: conflicts with this lmmio range may be
890 * elmmio range which is pointing down another rope.
893 printk("FAILED: lba_fixup_bus() request for "
894 "lmmio_space [%lx/%lx]\n",
895 ldev->hba.lmmio_space.start,
896 ldev->hba.lmmio_space.end);
897 /* lba_dump_res(&iomem_resource, 2); */
900 #ifdef CONFIG_PARISC64
901 /* GMMIO is distributed range. Every LBA/Rope gets part it. */
902 if (ldev->hba.gmmio_space.flags) {
903 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
905 printk("FAILED: lba_fixup_bus() request for "
906 "gmmio_space [%lx/%lx]\n",
907 ldev->hba.gmmio_space.start,
908 ldev->hba.gmmio_space.end);
909 lba_dump_res(&iomem_resource, 2);
915 /* advertize Host bridge resources to PCI bus */
916 bus->resource[0] = &(ldev->hba.io_space);
917 bus->resource[1] = &(ldev->hba.lmmio_space);
919 if (ldev->hba.elmmio_space.start)
920 bus->resource[i++] = &(ldev->hba.elmmio_space);
921 if (ldev->hba.gmmio_space.start)
922 bus->resource[i++] = &(ldev->hba.gmmio_space);
926 list_for_each(ln, &bus->devices) {
928 struct pci_dev *dev = pci_dev_b(ln);
930 DBG("lba_fixup_bus() %s\n", pci_name(dev));
932 /* Virtualize Device/Bridge Resources. */
933 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
934 struct resource *res = &dev->resource[i];
936 /* If resource not allocated - skip it */
940 if (res->flags & IORESOURCE_IO) {
941 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
942 res->start, res->end);
943 res->start |= lba_portbase;
944 res->end |= lba_portbase;
945 DBG("[%lx/%lx]\n", res->start, res->end);
946 } else if (res->flags & IORESOURCE_MEM) {
948 ** Convert PCI (IO_VIEW) addresses to
949 ** processor (PA_VIEW) addresses
951 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
952 res->start, res->end);
953 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
954 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
955 DBG("[%lx/%lx]\n", res->start, res->end);
957 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX",
958 res->flags, res->start, res->end);
964 ** If one device does not support FBB transfers,
965 ** No one on the bus can be allowed to use them.
967 (void) pci_read_config_word(dev, PCI_STATUS, &status);
968 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
972 /* Claim resources for PDC's devices */
973 lba_claim_dev_resources(dev);
977 ** P2PB's have no IRQs. ignore them.
979 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
982 /* Adjust INTERRUPT_LINE for this dev */
983 iosapic_fixup_irq(ldev->iosapic_obj, dev);
987 /* FIXME/REVISIT - finish figuring out to set FBB on both
988 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
989 ** Can't fixup here anyway....garr...
995 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
996 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
1001 fbb_enable = PCI_COMMAND_FAST_BACK;
1004 /* Lastly enable FBB/PERR/SERR on all devices too */
1005 list_for_each(ln, &bus->devices) {
1006 (void) pci_read_config_word(dev, PCI_COMMAND, &status);
1007 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
1008 (void) pci_write_config_word(dev, PCI_COMMAND, status);
1014 struct pci_bios_ops lba_bios_ops = {
1015 .init = lba_bios_init,
1016 .fixup_bus = lba_fixup_bus,
1022 /*******************************************************
1024 ** LBA Sprockets "I/O Port" Space Accessor Functions
1026 ** This set of accessor functions is intended for use with
1027 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
1029 ** Many PCI devices don't require use of I/O port space (eg Tulip,
1030 ** NCR720) since they export the same registers to both MMIO and
1031 ** I/O port space. In general I/O port space is slower than
1032 ** MMIO since drivers are designed so PIO writes can be posted.
1034 ********************************************************/
1036 #define LBA_PORT_IN(size, mask) \
1037 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
1040 t = READ_REG##size(LBA_PORT_BASE + addr); \
1041 DBG_PORT(" 0x%x\n", t); \
1052 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
1054 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
1055 ** guarantee non-postable completion semantics - not avoid X4107.
1056 ** The READ_U32 only guarantees the write data gets to elroy but
1057 ** out to the PCI bus. We can't read stuff from I/O port space
1058 ** since we don't know what has side-effects. Attempting to read
1059 ** from configuration space would be suicidal given the number of
1060 ** bugs in that elroy functionality.
1063 ** DMA read results can improperly pass PIO writes (X4107). The
1064 ** result of this bug is that if a processor modifies a location in
1065 ** memory after having issued PIO writes, the PIO writes are not
1066 ** guaranteed to be completed before a PCI device is allowed to see
1067 ** the modified data in a DMA read.
1069 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
1073 ** The workaround for this bug is to always follow a PIO write with
1074 ** a PIO read to the same bus before starting DMA on that PCI bus.
1077 #define LBA_PORT_OUT(size, mask) \
1078 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
1080 ASSERT(d != NULL); \
1081 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
1082 WRITE_REG##size(val, LBA_PORT_BASE + addr); \
1083 if (LBA_DEV(d)->hw_rev < 3) \
1084 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
1092 static struct pci_port_ops lba_astro_port_ops = {
1093 .inb = lba_astro_in8,
1094 .inw = lba_astro_in16,
1095 .inl = lba_astro_in32,
1096 .outb = lba_astro_out8,
1097 .outw = lba_astro_out16,
1098 .outl = lba_astro_out32
1102 #ifdef CONFIG_PARISC64
1103 #define PIOP_TO_GMMIO(lba, addr) \
1104 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
1106 /*******************************************************
1108 ** LBA PAT "I/O Port" Space Accessor Functions
1110 ** This set of accessor functions is intended for use with
1111 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
1113 ** This uses the PIOP space located in the first 64MB of GMMIO.
1114 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
1115 ** bits 1:0 stay the same. bits 15:2 become 25:12.
1116 ** Then add the base and we can generate an I/O Port cycle.
1117 ********************************************************/
1119 #define LBA_PORT_IN(size, mask) \
1120 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
1123 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
1124 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
1125 DBG_PORT(" 0x%x\n", t); \
1135 #define LBA_PORT_OUT(size, mask) \
1136 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
1138 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
1139 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
1140 WRITE_REG##size(val, where); \
1141 /* flush the I/O down to the elroy at least */ \
1142 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1150 static struct pci_port_ops lba_pat_port_ops = {
1152 .inw = lba_pat_in16,
1153 .inl = lba_pat_in32,
1154 .outb = lba_pat_out8,
1155 .outw = lba_pat_out16,
1156 .outl = lba_pat_out32
1162 ** make range information from PDC available to PCI subsystem.
1163 ** We make the PDC call here in order to get the PCI bus range
1164 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
1165 ** We don't have a struct pci_bus assigned to us yet.
1168 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1170 unsigned long bytecnt;
1171 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */
1172 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */
1174 long status; /* PDC return status */
1178 /* return cell module (IO view) */
1179 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1180 PA_VIEW, & pa_pdc_cell);
1181 pa_count = pa_pdc_cell.mod[1];
1183 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1184 IO_VIEW, &io_pdc_cell);
1185 io_count = io_pdc_cell.mod[1];
1187 /* We've already done this once for device discovery...*/
1188 if (status != PDC_OK) {
1189 panic("pdc_pat_cell_module() call failed for LBA!\n");
1192 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
1193 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1197 ** Inspect the resources PAT tells us about
1199 for (i = 0; i < pa_count; i++) {
1202 unsigned long start;
1203 unsigned long end; /* aka finish */
1207 p = (void *) &(pa_pdc_cell.mod[2+i*3]);
1208 io = (void *) &(io_pdc_cell.mod[2+i*3]);
1210 /* Convert the PAT range data to PCI "struct resource" */
1211 switch(p->type & 0xff) {
1213 lba_dev->hba.bus_num.start = p->start;
1214 lba_dev->hba.bus_num.end = p->end;
1218 /* used to fix up pre-initialized MEM BARs */
1219 if (!lba_dev->hba.lmmio_space.start) {
1220 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1221 (int) lba_dev->hba.bus_num.start);
1222 lba_dev->hba.lmmio_space_offset = p->start - io->start;
1223 r = &(lba_dev->hba.lmmio_space);
1224 r->name = lba_dev->hba.lmmio_name;
1225 } else if (!lba_dev->hba.elmmio_space.start) {
1226 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1227 (int) lba_dev->hba.bus_num.start);
1228 r = &(lba_dev->hba.elmmio_space);
1229 r->name = lba_dev->hba.elmmio_name;
1231 printk(KERN_WARNING MODULE_NAME
1232 " only supports 2 LMMIO resources!\n");
1236 r->start = p->start;
1238 r->flags = IORESOURCE_MEM;
1239 r->parent = r->sibling = r->child = NULL;
1243 /* MMIO space > 4GB phys addr; for 64-bit BAR */
1244 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1245 (int) lba_dev->hba.bus_num.start);
1246 r = &(lba_dev->hba.gmmio_space);
1247 r->name = lba_dev->hba.gmmio_name;
1248 r->start = p->start;
1250 r->flags = IORESOURCE_MEM;
1251 r->parent = r->sibling = r->child = NULL;
1255 printk(KERN_WARNING MODULE_NAME
1256 " range[%d] : ignoring NPIOP (0x%lx)\n",
1262 ** Postable I/O port space is per PCI host adapter.
1263 ** base of 64MB PIOP region
1265 lba_dev->iop_base = p->start;
1267 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1268 (int) lba_dev->hba.bus_num.start);
1269 r = &(lba_dev->hba.io_space);
1270 r->name = lba_dev->hba.io_name;
1271 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1272 r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
1273 r->flags = IORESOURCE_IO;
1274 r->parent = r->sibling = r->child = NULL;
1278 printk(KERN_WARNING MODULE_NAME
1279 " range[%d] : unknown pat range type (0x%lx)\n",
1286 /* keep compiler from complaining about missing declarations */
1287 #define lba_pat_port_ops lba_astro_port_ops
1288 #define lba_pat_resources(pa_dev, lba_dev)
1289 #endif /* CONFIG_PARISC64 */
1292 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1293 extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1297 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1302 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1305 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1306 ** represents bus->secondary and the second byte represents
1307 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1308 ** PCI bus walk *should* end up with the same result.
1309 ** FIXME: But we don't have sanity checks in PCI or LBA.
1311 lba_num = READ_REG32(pa_dev->hpa + LBA_FW_SCRATCH);
1312 r = &(lba_dev->hba.bus_num);
1313 r->name = "LBA PCI Busses";
1314 r->start = lba_num & 0xff;
1315 r->end = (lba_num>>8) & 0xff;
1317 /* Set up local PCI Bus resources - we don't need them for
1318 ** Legacy boxes but it's nice to see in /proc/iomem.
1320 r = &(lba_dev->hba.lmmio_space);
1321 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1322 (int) lba_dev->hba.bus_num.start);
1323 r->name = lba_dev->hba.lmmio_name;
1326 /* We want the CPU -> IO routing of addresses.
1327 * The SBA BASE/MASK registers control CPU -> IO routing.
1328 * Ask SBA what is routed to this rope/LBA.
1330 sba_distributed_lmmio(pa_dev, r);
1333 * The LBA BASE/MASK registers control IO -> System routing.
1335 * The following code works but doesn't get us what we want.
1336 * Well, only because firmware (v5.0) on C3000 doesn't program
1337 * the LBA BASE/MASE registers to be the exact inverse of
1338 * the corresponding SBA registers. Other Astro/Pluto
1339 * based platform firmware may do it right.
1341 * Should someone want to mess with MSI, they may need to
1342 * reprogram LBA BASE/MASK registers. Thus preserve the code
1343 * below until MSI is known to work on C3000/A500/N4000/RP3440.
1345 * Using the code below, /proc/iomem shows:
1347 * f0000000-f0ffffff : PCI00 LMMIO
1348 * f05d0000-f05d0000 : lcd_data
1349 * f05d0008-f05d0008 : lcd_cmd
1350 * f1000000-f1ffffff : PCI01 LMMIO
1351 * f4000000-f4ffffff : PCI02 LMMIO
1352 * f4000000-f4001fff : sym53c8xx
1353 * f4002000-f4003fff : sym53c8xx
1354 * f4004000-f40043ff : sym53c8xx
1355 * f4005000-f40053ff : sym53c8xx
1356 * f4007000-f4007fff : ohci_hcd
1357 * f4008000-f40083ff : tulip
1358 * f6000000-f6ffffff : PCI03 LMMIO
1359 * f8000000-fbffffff : PCI00 ELMMIO
1360 * fa100000-fa4fffff : stifb mmio
1361 * fb000000-fb1fffff : stifb fb
1363 * But everything listed under PCI02 actually lives under PCI00.
1364 * This is clearly wrong.
1366 * Asking SBA how things are routed tells the correct story:
1367 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1368 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1369 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1370 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1371 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1373 * Which looks like this in /proc/iomem:
1374 * f4000000-f47fffff : PCI00 LMMIO
1375 * f4000000-f4001fff : sym53c8xx
1376 * ...[deteled core devices - same as above]...
1377 * f4008000-f40083ff : tulip
1378 * f4800000-f4ffffff : PCI01 LMMIO
1379 * f6000000-f67fffff : PCI02 LMMIO
1380 * f7000000-f77fffff : PCI03 LMMIO
1381 * f9000000-f9ffffff : PCI02 ELMMIO
1382 * fa000000-fbffffff : PCI03 ELMMIO
1383 * fa100000-fa4fffff : stifb mmio
1384 * fb000000-fb1fffff : stifb fb
1386 * ie all Built-in core are under now correctly under PCI00.
1387 * The "PCI02 ELMMIO" directed range is for:
1388 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
1392 r->start = (long) READ_REG32(pa_dev->hpa + LBA_LMMIO_BASE);
1394 unsigned long rsize;
1396 r->flags = IORESOURCE_MEM;
1397 /* mmio_mask also clears Enable bit */
1398 r->start &= mmio_mask;
1399 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1400 rsize = ~ READ_REG32(pa_dev->hpa + LBA_LMMIO_MASK);
1403 ** Each rope only gets part of the distributed range.
1404 ** Adjust "window" for this rope.
1406 rsize /= ROPES_PER_IOC;
1407 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa);
1408 r->end = r->start + rsize;
1410 r->end = r->start = 0; /* Not enabled. */
1415 ** "Directed" ranges are used when the "distributed range" isn't
1416 ** sufficient for all devices below a given LBA. Typically devices
1417 ** like graphics cards or X25 may need a directed range when the
1418 ** bus has multiple slots (ie multiple devices) or the device
1419 ** needs more than the typical 4 or 8MB a distributed range offers.
1421 ** The main reason for ignoring it now frigging complications.
1422 ** Directed ranges may overlap (and have precedence) over
1423 ** distributed ranges. Or a distributed range assigned to a unused
1424 ** rope may be used by a directed range on a different rope.
1425 ** Support for graphics devices may require fixing this
1426 ** since they may be assigned a directed range which overlaps
1427 ** an existing (but unused portion of) distributed range.
1429 r = &(lba_dev->hba.elmmio_space);
1430 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1431 (int) lba_dev->hba.bus_num.start);
1432 r->name = lba_dev->hba.elmmio_name;
1435 /* See comment which precedes call to sba_directed_lmmio() */
1436 sba_directed_lmmio(pa_dev, r);
1438 r->start = READ_REG32(pa_dev->hpa + LBA_ELMMIO_BASE);
1441 unsigned long rsize;
1442 r->flags = IORESOURCE_MEM;
1443 /* mmio_mask also clears Enable bit */
1444 r->start &= mmio_mask;
1445 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1446 rsize = READ_REG32(pa_dev->hpa + LBA_ELMMIO_MASK);
1447 r->end = r->start + ~rsize;
1451 r = &(lba_dev->hba.io_space);
1452 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1453 (int) lba_dev->hba.bus_num.start);
1454 r->name = lba_dev->hba.io_name;
1455 r->flags = IORESOURCE_IO;
1456 r->start = READ_REG32(pa_dev->hpa + LBA_IOS_BASE) & ~1L;
1457 r->end = r->start + (READ_REG32(pa_dev->hpa + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1459 /* Virtualize the I/O Port space ranges */
1460 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1461 r->start |= lba_num;
1466 /**************************************************************************
1468 ** LBA initialization code (HW and SW)
1470 ** o identify LBA chip itself
1471 ** o initialize LBA chip modes (HardFail)
1472 ** o FIXME: initialize DMA hints for reasonable defaults
1473 ** o enable configuration functions
1474 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1476 **************************************************************************/
1479 lba_hw_init(struct lba_device *d)
1482 u32 bus_reset; /* PDC_PAT_BUG */
1485 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1487 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1488 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1489 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1490 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1491 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1492 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1493 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1494 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1495 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1496 printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1497 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1498 printk(KERN_DEBUG " HINT reg ");
1500 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1501 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1504 #endif /* DEBUG_LBA_PAT */
1506 #ifdef CONFIG_PARISC64
1508 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1509 * Only N-Class and up can really make use of Get slot status.
1510 * maybe L-class too but I've never played with it there.
1514 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1515 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1517 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1520 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1521 if (stat & LBA_SMART_MODE) {
1522 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1523 stat &= ~LBA_SMART_MODE;
1524 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1527 /* Set HF mode as the default (vs. -1 mode). */
1528 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1529 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1532 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1533 ** if it's not already set. If we just cleared the PCI Bus Reset
1534 ** signal, wait a bit for the PCI devices to recover and setup.
1537 mdelay(pci_post_reset_delay);
1539 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1541 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1542 ** B2000/C3600/J6000 also have this problem?
1544 ** Elroys with hot pluggable slots don't get configured
1545 ** correctly if the slot is empty. ARB_MASK is set to 0
1546 ** and we can't master transactions on the bus if it's
1547 ** not at least one. 0x3 enables elroy and first slot.
1549 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1550 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1554 ** FIXME: Hint registers are programmed with default hint
1555 ** values by firmware. Hints should be sane even if we
1556 ** can't reprogram them the way drivers want.
1564 lba_common_init(struct lba_device *lba_dev)
1566 pci_bios = &lba_bios_ops;
1567 pcibios_register_hba(HBA_DATA(lba_dev));
1568 lba_dev->lba_lock = SPIN_LOCK_UNLOCKED;
1571 ** Set flags which depend on hw_rev
1573 if (!LBA_TR4PLUS(lba_dev)) {
1574 lba_dev->flags |= LBA_FLAG_NO_DMA_DURING_CFG;
1581 ** Determine if lba should claim this chip (return 0) or not (return 1).
1582 ** If so, initialize the chip and tell other partners in crime they
1586 lba_driver_probe(struct parisc_device *dev)
1588 struct lba_device *lba_dev;
1589 struct pci_bus *lba_bus;
1594 /* Read HW Rev First */
1595 func_class = READ_REG32(dev->hpa + LBA_FCLASS);
1597 if (IS_ELROY(dev)) {
1599 switch (func_class) {
1600 case 0: version = "TR1.0"; break;
1601 case 1: version = "TR2.0"; break;
1602 case 2: version = "TR2.1"; break;
1603 case 3: version = "TR2.2"; break;
1604 case 4: version = "TR3.0"; break;
1605 case 5: version = "TR4.0"; break;
1606 default: version = "TR4+";
1608 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1609 MODULE_NAME, version, func_class & 0xf, dev->hpa);
1611 /* Just in case we find some prototypes... */
1612 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1614 version = kmalloc(6, GFP_KERNEL);
1615 sprintf(version,"TR%d.%d",(func_class >> 4),(func_class & 0xf));
1616 /* We could use one printk for both and have it outside,
1617 * but for the mask for func_class.
1619 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1620 MODULE_NAME, version, func_class & 0xff, dev->hpa);
1623 if (func_class < 2) {
1624 printk(KERN_WARNING "Can't support LBA older than TR2.1"
1625 " - continuing under adversity.\n");
1629 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1631 tmp_obj = iosapic_register(dev->hpa + LBA_IOSAPIC_BASE);
1633 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1634 ** have an IRT entry will get NULL back from iosapic code.
1637 lba_dev = kmalloc(sizeof(struct lba_device), GFP_KERNEL);
1638 if (NULL == lba_dev)
1640 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1644 memset(lba_dev, 0, sizeof(struct lba_device));
1647 /* ---------- First : initialize data we already have --------- */
1650 ** Need hw_rev to adjust configuration space behavior.
1651 ** LBA_TR4PLUS macro uses hw_rev field.
1653 lba_dev->hw_rev = func_class;
1655 lba_dev->hba.base_addr = dev->hpa; /* faster access */
1656 lba_dev->hba.dev = dev;
1657 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
1658 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
1660 /* ------------ Second : initialize common stuff ---------- */
1661 lba_common_init(lba_dev);
1663 if (lba_hw_init(lba_dev))
1666 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1669 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1670 pci_port = &lba_pat_port_ops;
1671 /* Go ask PDC PAT what resources this LBA has */
1672 lba_pat_resources(dev, lba_dev);
1674 /* Sprockets PDC uses NPIOP region */
1675 pci_port = &lba_astro_port_ops;
1677 /* Poke the chip a bit for /proc output */
1678 lba_legacy_resources(dev, lba_dev);
1682 ** Tell PCI support another PCI bus was found.
1683 ** Walks PCI bus for us too.
1685 dev->dev.platform_data = lba_dev;
1686 lba_bus = lba_dev->hba.hba_bus =
1687 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1688 IS_ELROY(dev) ? &lba_cfg_ops : &mercury_cfg_ops,
1691 /* This is in lieu of calling pci_assign_unassigned_resources() */
1693 /* assign resources to un-initialized devices */
1695 DBG_PAT("LBA pci_bus_size_bridges()\n");
1696 pci_bus_size_bridges(lba_bus);
1698 DBG_PAT("LBA pci_bus_assign_resources()\n");
1699 pci_bus_assign_resources(lba_bus);
1701 #ifdef DEBUG_LBA_PAT
1702 DBG_PAT("\nLBA PIOP resource tree\n");
1703 lba_dump_res(&lba_dev->hba.io_space, 2);
1704 DBG_PAT("\nLBA LMMIO resource tree\n");
1705 lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1708 pci_enable_bridges(lba_bus);
1712 ** Once PCI register ops has walked the bus, access to config
1713 ** space is restricted. Avoids master aborts on config cycles.
1714 ** Early LBA revs go fatal on *any* master abort.
1716 if (!LBA_TR4PLUS(lba_dev)) {
1717 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1720 /* Whew! Finally done! Tell services we got this one covered. */
1724 static struct parisc_device_id lba_tbl[] = {
1725 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1726 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1727 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1731 static struct parisc_driver lba_driver = {
1732 .name = MODULE_NAME,
1733 .id_table = lba_tbl,
1734 .probe = lba_driver_probe,
1738 ** One time initialization to let the world know the LBA was found.
1739 ** Must be called exactly once before pci_init().
1741 void __init lba_init(void)
1743 register_parisc_driver(&lba_driver);
1747 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1748 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1749 ** sba_iommu is responsible for locking (none needed at init time).
1752 lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1754 unsigned long base_addr = lba->hpa;
1756 imask <<= 2; /* adjust for hints - 2 more bits */
1758 ASSERT((ibase & 0x003fffff) == 0);
1759 ASSERT((imask & 0x003fffff) == 0);
1761 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1762 WRITE_REG32( imask, base_addr + LBA_IMASK);
1763 WRITE_REG32( ibase, base_addr + LBA_IBASE);