5 * IBM Hot Plug Controller Driver
7 * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation
9 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
10 * Copyright (C) 2001-2003 IBM Corp.
12 * All rights reserved.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
22 * NON INFRINGEMENT. See the GNU General Public License for more
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Send feedback to <gregkh@us.ibm.com>
33 #include "pci_hotplug.h"
35 extern int ibmphp_debug;
37 #if !defined(CONFIG_HOTPLUG_PCI_IBM_MODULE)
38 #define MY_NAME "ibmphpd"
40 #define MY_NAME THIS_MODULE->name
42 #define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
43 #define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
44 #define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
45 #define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
46 #define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
51 /***********************************************************
53 ***********************************************************/
55 #define EBDA_SLOT_133_MAX 0x20
56 #define EBDA_SLOT_100_MAX 0x10
57 #define EBDA_SLOT_66_MAX 0x02
58 #define EBDA_SLOT_PCIX_CAP 0x08
61 /************************************************************
63 ************************************************************/
65 #define EBDA_RSRC_TYPE_MASK 0x03
66 #define EBDA_IO_RSRC_TYPE 0x00
67 #define EBDA_MEM_RSRC_TYPE 0x01
68 #define EBDA_PFM_RSRC_TYPE 0x03
69 #define EBDA_RES_RSRC_TYPE 0x02
72 /*************************************************************
73 * IO RESTRICTION TYPE *
74 *************************************************************/
76 #define EBDA_IO_RESTRI_MASK 0x0c
77 #define EBDA_NO_RESTRI 0x00
78 #define EBDA_AVO_VGA_ADDR 0x04
79 #define EBDA_AVO_VGA_ADDR_AND_ALIA 0x08
80 #define EBDA_AVO_ISA_ADDR 0x0c
83 /**************************************************************
85 **************************************************************/
87 #define EBDA_DEV_TYPE_MASK 0x10
88 #define EBDA_PCI_DEV 0x10
89 #define EBDA_NON_PCI_DEV 0x00
92 /***************************************************************
93 * PRIMARY DEF DEFINITION *
94 ***************************************************************/
96 #define EBDA_PRI_DEF_MASK 0x20
97 #define EBDA_PRI_PCI_BUS_INFO 0x20
98 #define EBDA_NORM_DEV_RSRC_INFO 0x00
101 //--------------------------------------------------------------
102 // RIO TABLE DATA STRUCTURE
103 //--------------------------------------------------------------
105 struct rio_table_hdr {
112 //-------------------------------------------------------------
113 // SCALABILITY DETAIL
114 //-------------------------------------------------------------
119 u8 port0_node_connect;
120 u8 port0_port_connect;
121 u8 port1_node_connect;
122 u8 port1_port_connect;
123 u8 port2_node_connect;
124 u8 port2_port_connect;
126 // struct list_head scal_detail_list;
129 //--------------------------------------------------------------
131 //--------------------------------------------------------------
138 u8 port0_node_connect;
139 u8 port0_port_connect;
140 u8 port1_node_connect;
141 u8 port1_port_connect;
146 struct list_head rio_detail_list;
154 struct list_head opt_rio_list;
163 struct list_head opt_rio_lo_list;
166 /****************************************************************
167 * HPC DESCRIPTOR NODE *
168 ****************************************************************/
170 struct ebda_hpc_list {
174 // struct list_head ebda_hpc_list;
176 /*****************************************************************
177 * IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS *
179 *****************************************************************/
181 struct ebda_hpc_slot {
188 struct ebda_hpc_bus {
193 u8 slots_at_100_pcix;
194 u8 slots_at_133_pcix;
198 /********************************************************************
199 * THREE TYPE OF HOT PLUG CONTROLER *
200 ********************************************************************/
202 struct isa_ctlr_access {
207 struct pci_ctlr_access {
212 struct wpeg_i2c_ctlr_access {
217 #define HPC_DEVICE_ID 0x0246
218 #define HPC_SUBSYSTEM_ID 0x0247
219 #define HPC_PCI_OFFSET 0x40
220 /*************************************************************************
221 * RSTC DESCRIPTOR NODE *
222 *************************************************************************/
224 struct ebda_rsrc_list {
228 struct ebda_rsrc_list *next;
232 /***************************************************************************
234 ***************************************************************************/
236 struct ebda_pci_rsrc {
242 u8 marked; /* for NVRAM */
243 struct list_head ebda_pci_rsrc_list;
247 /***********************************************************
248 * BUS_INFO DATE STRUCTURE *
249 ***********************************************************/
263 u8 slots_at_100_pcix;
264 u8 slots_at_133_pcix;
265 struct list_head bus_info_list;
269 /***********************************************************
271 ***********************************************************/
272 extern struct list_head ibmphp_ebda_pci_rsrc_head;
273 extern struct list_head ibmphp_slot_head;
274 extern struct list_head ibmphp_res_head;
275 /***********************************************************
276 * FUNCTION PROTOTYPES *
277 ***********************************************************/
279 extern void ibmphp_free_ebda_hpc_queue (void);
280 extern int ibmphp_access_ebda (void);
281 extern struct slot *ibmphp_get_slot_from_physical_num (u8);
282 extern int ibmphp_get_total_hp_slots (void);
283 extern void ibmphp_free_ibm_slot (struct slot *);
284 extern void ibmphp_free_bus_info_queue (void);
285 extern void ibmphp_free_ebda_pci_rsrc_queue (void);
286 extern struct bus_info *ibmphp_find_same_bus_num (u32);
287 extern int ibmphp_get_bus_index (u8);
288 extern u16 ibmphp_get_total_controllers (void);
289 extern int ibmphp_register_pci (void);
291 /* passed parameters */
298 #define IOMASK 0x00 /* will need to take its complement */
301 #define PCIDEVMASK 0x10 /* we should always have PCI devices */
302 #define PRIMARYBUSMASK 0x20
304 /* pci specific defines */
305 #define PCI_VENDOR_ID_NOTVALID 0xFFFF
306 #define PCI_HEADER_TYPE_MULTIDEVICE 0x80
307 #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81
311 #define DEVICEENABLE 0x015F /* CPQ has 0x0157 */
313 #define IOBRIDGE 0x1000 /* 4k */
314 #define MEMBRIDGE 0x100000 /* 1M */
317 #define SCSI_IRQ 0x09
319 #define OTHER_IRQ 0x0B
321 /* Data Structures */
323 /* type is of the form x x xx xx
324 * | | | |_ 00 - I/O, 01 - Memory, 11 - PFMemory
325 * | | - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid
326 * | | VGA and their aliases, 11 - Avoid ISA
327 * | - 1 - PCI device, 0 - non pci device
328 * - 1 - Primary PCI Bus Information (0 if Normal device)
329 * the IO restrictions [2:3] are only for primary buses
333 /* we need this struct because there could be several resource blocks
334 * allocated per primary bus in the EBDA
340 struct range_node *next;
346 struct range_node *rangeIO;
348 struct range_node *rangeMem;
350 struct range_node *rangePFMem;
354 struct resource_node *firstIO; /* first IO resource on the Bus */
355 struct resource_node *firstMem; /* first memory resource on the Bus */
356 struct resource_node *firstPFMem; /* first prefetchable memory resource on the Bus */
357 struct resource_node *firstPFMemFromMem; /* when run out of pfmem available, taking from Mem */
358 struct list_head bus_list;
361 struct resource_node {
368 int type; /* MEM, IO, PFMEM */
369 u8 fromMem; /* this is to indicate that the range is from
370 * from the Memory bucket rather than from PFMem */
371 struct resource_node *next;
372 struct resource_node *nextRange; /* for the other mem range on bus */
379 u8 not_correct; /* needed for return */
380 int devices[32]; /* for device numbers behind this bridge */
385 extern int ibmphp_rsrc_init (void);
386 extern int ibmphp_add_resource (struct resource_node *);
387 extern int ibmphp_remove_resource (struct resource_node *);
388 extern int ibmphp_find_resource (struct bus_node *, u32, struct resource_node **, int);
389 extern int ibmphp_check_resource (struct resource_node *, u8);
390 extern int ibmphp_remove_bus (struct bus_node *, u8);
391 extern void ibmphp_free_resources (void);
392 extern int ibmphp_add_pfmem_from_mem (struct resource_node *);
393 extern struct bus_node *ibmphp_find_res_bus (u8);
394 extern void ibmphp_print_test (void); /* for debugging purposes */
396 extern void ibmphp_hpc_initvars (void);
397 extern int ibmphp_hpc_readslot (struct slot *, u8, u8 *);
398 extern int ibmphp_hpc_writeslot (struct slot *, u8);
399 extern void ibmphp_lock_operations (void);
400 extern void ibmphp_unlock_operations (void);
401 extern int ibmphp_hpc_start_poll_thread (void);
402 extern void ibmphp_hpc_stop_poll_thread (void);
404 //----------------------------------------------------------------------------
407 //----------------------------------------------------------------------------
409 //----------------------------------------------------------------------------
412 #define HPC_ERROR 0xFF
414 //-----------------------------------------------------------------------------
416 //-----------------------------------------------------------------------------
417 #define BUS_SPEED 0x30
418 #define BUS_MODE 0x40
419 #define BUS_MODE_PCIX 0x01
420 #define BUS_MODE_PCI 0x00
421 #define BUS_SPEED_2 0x20
422 #define BUS_SPEED_1 0x10
423 #define BUS_SPEED_33 0x00
424 #define BUS_SPEED_66 0x01
425 #define BUS_SPEED_100 0x02
426 #define BUS_SPEED_133 0x03
427 #define BUS_SPEED_66PCIX 0x04
428 #define BUS_SPEED_66UNKNOWN 0x05
429 #define BUS_STATUS_AVAILABLE 0x01
430 #define BUS_CONTROL_AVAILABLE 0x02
431 #define SLOT_LATCH_REGS_SUPPORTED 0x10
433 #define PRGM_MODEL_REV_LEVEL 0xF0
434 #define MAX_ADAPTER_NONE 0x09
436 //----------------------------------------------------------------------------
437 // HPC 'write' operations/commands
438 //----------------------------------------------------------------------------
439 // Command Code State Write to reg
441 //------------------------- ---- ------- ------------
442 #define HPC_CTLR_ENABLEIRQ 0x00 // N 15
443 #define HPC_CTLR_DISABLEIRQ 0x01 // N 15
444 #define HPC_SLOT_OFF 0x02 // Y 0-14
445 #define HPC_SLOT_ON 0x03 // Y 0-14
446 #define HPC_SLOT_ATTNOFF 0x04 // N 0-14
447 #define HPC_SLOT_ATTNON 0x05 // N 0-14
448 #define HPC_CTLR_CLEARIRQ 0x06 // N 15
449 #define HPC_CTLR_RESET 0x07 // Y 15
450 #define HPC_CTLR_IRQSTEER 0x08 // N 15
451 #define HPC_BUS_33CONVMODE 0x09 // Y 31-34
452 #define HPC_BUS_66CONVMODE 0x0A // Y 31-34
453 #define HPC_BUS_66PCIXMODE 0x0B // Y 31-34
454 #define HPC_BUS_100PCIXMODE 0x0C // Y 31-34
455 #define HPC_BUS_133PCIXMODE 0x0D // Y 31-34
456 #define HPC_ALLSLOT_OFF 0x11 // Y 15
457 #define HPC_ALLSLOT_ON 0x12 // Y 15
458 #define HPC_SLOT_BLINKLED 0x13 // N 0-14
460 //----------------------------------------------------------------------------
462 //----------------------------------------------------------------------------
463 #define READ_SLOTSTATUS 0x01
464 #define READ_EXTSLOTSTATUS 0x02
465 #define READ_BUSSTATUS 0x03
466 #define READ_CTLRSTATUS 0x04
467 #define READ_ALLSTAT 0x05
468 #define READ_ALLSLOT 0x06
469 #define READ_SLOTLATCHLOWREG 0x07
470 #define READ_REVLEVEL 0x08
471 #define READ_HPCOPTIONS 0x09
472 //----------------------------------------------------------------------------
474 //----------------------------------------------------------------------------
475 #define HPC_SLOT_POWER 0x01
476 #define HPC_SLOT_CONNECT 0x02
477 #define HPC_SLOT_ATTN 0x04
478 #define HPC_SLOT_PRSNT2 0x08
479 #define HPC_SLOT_PRSNT1 0x10
480 #define HPC_SLOT_PWRGD 0x20
481 #define HPC_SLOT_BUS_SPEED 0x40
482 #define HPC_SLOT_LATCH 0x80
484 //----------------------------------------------------------------------------
485 // HPC_SLOT_POWER status return codes
486 //----------------------------------------------------------------------------
487 #define HPC_SLOT_POWER_OFF 0x00
488 #define HPC_SLOT_POWER_ON 0x01
490 //----------------------------------------------------------------------------
491 // HPC_SLOT_CONNECT status return codes
492 //----------------------------------------------------------------------------
493 #define HPC_SLOT_CONNECTED 0x00
494 #define HPC_SLOT_DISCONNECTED 0x01
496 //----------------------------------------------------------------------------
497 // HPC_SLOT_ATTN status return codes
498 //----------------------------------------------------------------------------
499 #define HPC_SLOT_ATTN_OFF 0x00
500 #define HPC_SLOT_ATTN_ON 0x01
501 #define HPC_SLOT_ATTN_BLINK 0x02
503 //----------------------------------------------------------------------------
504 // HPC_SLOT_PRSNT status return codes
505 //----------------------------------------------------------------------------
506 #define HPC_SLOT_EMPTY 0x00
507 #define HPC_SLOT_PRSNT_7 0x01
508 #define HPC_SLOT_PRSNT_15 0x02
509 #define HPC_SLOT_PRSNT_25 0x03
511 //----------------------------------------------------------------------------
512 // HPC_SLOT_PWRGD status return codes
513 //----------------------------------------------------------------------------
514 #define HPC_SLOT_PWRGD_FAULT_NONE 0x00
515 #define HPC_SLOT_PWRGD_GOOD 0x01
517 //----------------------------------------------------------------------------
518 // HPC_SLOT_BUS_SPEED status return codes
519 //----------------------------------------------------------------------------
520 #define HPC_SLOT_BUS_SPEED_OK 0x00
521 #define HPC_SLOT_BUS_SPEED_MISM 0x01
523 //----------------------------------------------------------------------------
524 // HPC_SLOT_LATCH status return codes
525 //----------------------------------------------------------------------------
526 #define HPC_SLOT_LATCH_OPEN 0x01 // NOTE : in PCI spec bit off = open
527 #define HPC_SLOT_LATCH_CLOSED 0x00 // NOTE : in PCI spec bit on = closed
530 //----------------------------------------------------------------------------
531 // extended slot status
532 //----------------------------------------------------------------------------
533 #define HPC_SLOT_PCIX 0x01
534 #define HPC_SLOT_SPEED1 0x02
535 #define HPC_SLOT_SPEED2 0x04
536 #define HPC_SLOT_BLINK_ATTN 0x08
537 #define HPC_SLOT_RSRVD1 0x10
538 #define HPC_SLOT_RSRVD2 0x20
539 #define HPC_SLOT_BUS_MODE 0x40
540 #define HPC_SLOT_RSRVD3 0x80
542 //----------------------------------------------------------------------------
543 // HPC_XSLOT_PCIX_CAP status return codes
544 //----------------------------------------------------------------------------
545 #define HPC_SLOT_PCIX_NO 0x00
546 #define HPC_SLOT_PCIX_YES 0x01
548 //----------------------------------------------------------------------------
549 // HPC_XSLOT_SPEED status return codes
550 //----------------------------------------------------------------------------
551 #define HPC_SLOT_SPEED_33 0x00
552 #define HPC_SLOT_SPEED_66 0x01
553 #define HPC_SLOT_SPEED_133 0x02
555 //----------------------------------------------------------------------------
556 // HPC_XSLOT_ATTN_BLINK status return codes
557 //----------------------------------------------------------------------------
558 #define HPC_SLOT_ATTN_BLINK_OFF 0x00
559 #define HPC_SLOT_ATTN_BLINK_ON 0x01
561 //----------------------------------------------------------------------------
562 // HPC_XSLOT_BUS_MODE status return codes
563 //----------------------------------------------------------------------------
564 #define HPC_SLOT_BUS_MODE_OK 0x00
565 #define HPC_SLOT_BUS_MODE_MISM 0x01
567 //----------------------------------------------------------------------------
569 //----------------------------------------------------------------------------
570 #define HPC_CTLR_WORKING 0x01
571 #define HPC_CTLR_FINISHED 0x02
572 #define HPC_CTLR_RESULT0 0x04
573 #define HPC_CTLR_RESULT1 0x08
574 #define HPC_CTLR_RESULE2 0x10
575 #define HPC_CTLR_RESULT3 0x20
576 #define HPC_CTLR_IRQ_ROUTG 0x40
577 #define HPC_CTLR_IRQ_PENDG 0x80
579 //----------------------------------------------------------------------------
580 // HPC_CTLR_WROKING status return codes
581 //----------------------------------------------------------------------------
582 #define HPC_CTLR_WORKING_NO 0x00
583 #define HPC_CTLR_WORKING_YES 0x01
585 //----------------------------------------------------------------------------
586 // HPC_CTLR_FINISHED status return codes
587 //----------------------------------------------------------------------------
588 #define HPC_CTLR_FINISHED_NO 0x00
589 #define HPC_CTLR_FINISHED_YES 0x01
591 //----------------------------------------------------------------------------
592 // HPC_CTLR_RESULT status return codes
593 //----------------------------------------------------------------------------
594 #define HPC_CTLR_RESULT_SUCCESS 0x00
595 #define HPC_CTLR_RESULT_FAILED 0x01
596 #define HPC_CTLR_RESULT_RSVD 0x02
597 #define HPC_CTLR_RESULT_NORESP 0x03
600 //----------------------------------------------------------------------------
601 // macro for slot info
602 //----------------------------------------------------------------------------
603 #define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \
604 ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))
606 #define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
607 ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
609 #define SLOT_ATTN(s,es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
610 ? HPC_SLOT_ATTN_BLINK \
611 : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
613 #define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \
614 ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \
615 : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))
617 #define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \
618 ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))
620 #define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \
621 ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))
623 #define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \
624 ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))
626 #define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \
627 ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))
629 #define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \
630 ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \
631 : HPC_SLOT_SPEED_66) \
632 : HPC_SLOT_SPEED_33))
634 #define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \
635 ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))
637 //--------------------------------------------------------------------------
638 // macro for bus info
639 //---------------------------------------------------------------------------
640 #define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \
641 ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \
642 : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))
644 #define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)
646 #define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE))
648 #define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)
650 #define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE))
652 #define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))
654 //----------------------------------------------------------------------------
655 // macro for controller info
656 //----------------------------------------------------------------------------
657 #define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \
658 ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))
659 #define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \
660 ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))
661 #define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \
662 ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \
663 : HPC_CTLR_RESULT_RSVD) \
664 : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \
665 : HPC_CTLR_RESULT_SUCCESS)))
667 // command that affect the state machine of HPC
668 #define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \
669 (c == HPC_SLOT_ON) || \
670 (c == HPC_CTLR_RESET) || \
671 (c == HPC_BUS_33CONVMODE) || \
672 (c == HPC_BUS_66CONVMODE) || \
673 (c == HPC_BUS_66PCIXMODE) || \
674 (c == HPC_BUS_100PCIXMODE) || \
675 (c == HPC_BUS_133PCIXMODE) || \
676 (c == HPC_ALLSLOT_OFF) || \
677 (c == HPC_ALLSLOT_ON))
680 /* Core part of the driver */
685 #define CARD_INFO 0x07
690 extern struct pci_bus *ibmphp_pci_bus;
695 struct pci_dev *dev; /* from the OS */
699 struct resource_node *io[6];
700 struct resource_node *mem[6];
701 struct resource_node *pfmem[6];
702 struct pci_func *next;
703 int devices[32]; /* for bridge config */
704 u8 irq[4]; /* for interrupt config */
705 u8 bus; /* flag for unconfiguring, to say if PPB */
712 u8 real_physical_slot_num;
716 u8 supported_bus_mode;
717 struct hotplug_slot *hotplug_slot;
718 struct controller *ctrl;
719 struct pci_func *func;
721 u8 flag; /* this is for disable slot and polling */
722 int bit_mode; /* 0 = 32, 1 = 64 */
724 struct bus_info *bus_on;
725 struct list_head ibm_slot_list;
732 struct ebda_hpc_slot *slots;
733 struct ebda_hpc_bus *buses;
734 struct pci_dev *ctrl_dev; /* in case where controller is PCI */
735 u8 starting_slot_num; /* starting and ending slot #'s this ctrl controls*/
738 u8 options; /* which options HPC supports */
746 struct isa_ctlr_access isa_ctlr;
747 struct pci_ctlr_access pci_ctlr;
748 struct wpeg_i2c_ctlr_access wpeg_ctlr;
751 struct list_head ebda_hpc_list;
756 extern int ibmphp_init_devno (struct slot **); /* This function is called from EBDA, so we need it not be static */
757 extern int ibmphp_disable_slot (struct hotplug_slot *); /* This function is called from HPC, so we need it to not be static */
758 extern int ibmphp_do_disable_slot (struct slot *slot_cur);
759 extern int ibmphp_update_slot_info (struct slot *); /* This function is called from HPC, so we need it to not be be static */
760 extern int ibmphp_configure_card (struct pci_func *, u8);
761 extern int ibmphp_unconfigure_card (struct slot **, int);
762 extern struct hotplug_slot_ops ibmphp_hotplug_slot_ops;
764 static inline void long_delay (int delay)
766 set_current_state (TASK_INTERRUPTIBLE);
767 schedule_timeout (delay);