2 * PCI Express Hot Plug Controller Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>, <dely.l.sy@intel.com>
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/types.h>
34 #include <linux/slab.h>
35 #include <linux/workqueue.h>
36 #include <linux/proc_fs.h>
37 #include <linux/pci.h>
41 #include "../../../arch/i386/pci/pci.h" /* horrible hack showing how processor dependant we are... */
45 int pciehp_configure_device (struct controller* ctrl, struct pci_func* func)
48 struct pci_bus *child;
51 if (func->pci_dev == NULL)
52 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
54 /* Still NULL ? Well then scan for it ! */
55 if (func->pci_dev == NULL) {
56 dbg("%s: pci_dev still null. do pci_scan_slot\n", __FUNCTION__);
58 num = pci_scan_slot(ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function));
61 pci_bus_add_devices(ctrl->pci_dev->subordinate);
63 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
64 if (func->pci_dev == NULL) {
65 dbg("ERROR: pci_dev still null\n");
70 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
71 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
72 child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
73 pci_do_scan_bus(child);
81 int pciehp_unconfigure_device(struct pci_func* func)
86 dbg("%s: bus/dev/func = %x/%x/%x\n", __FUNCTION__, func->bus, func->device, func->function);
88 for (j=0; j<8 ; j++) {
89 struct pci_dev* temp = pci_find_slot(func->bus, (func->device << 3) | j);
91 pci_remove_bus_device(temp);
100 * @bus_num: bus number of PCI device
101 * @dev_num: device number of PCI device
102 * @slot: pointer to u8 where slot number will be returned
104 int pciehp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
106 #if defined(CONFIG_X86) && !defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_64)
109 struct pci_dev fakedev;
110 struct pci_bus fakebus;
112 fakedev.devfn = dev_num << 3;
113 fakedev.bus = &fakebus;
114 fakebus.number = bus_num;
115 dbg("%s: dev %d, bus %d, pin %d, num %d\n",
116 __FUNCTION__, dev_num, bus_num, int_pin, irq_num);
117 rc = pcibios_set_irq_routing(&fakedev, int_pin - 0x0a, irq_num);
118 dbg("%s: rc %d\n", __FUNCTION__, rc);
122 /* set the Edge Level Control Register (ELCR) */
123 temp_word = inb(0x4d0);
124 temp_word |= inb(0x4d1) << 8;
126 temp_word |= 0x01 << irq_num;
128 /* This should only be for x86 as it sets the Edge Level Control Register */
129 outb((u8) (temp_word & 0xFF), 0x4d0);
130 outb((u8) ((temp_word & 0xFF00) >> 8), 0x4d1);
135 /* More PCI configuration routines; this time centered around hotplug controller */
141 * Reads configuration for all slots in a PCI bus and saves info.
143 * Note: For non-hot plug busses, the slot # saved is the device #
145 * returns 0 if success
147 int pciehp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num)
154 struct pci_func *new_slot;
163 int is_hot_plug = num_ctlr_slots || first_device_num;
164 struct pci_bus lpci_bus, *pci_bus;
165 int FirstSupported, LastSupported;
167 dbg("%s: Enter\n", __FUNCTION__);
169 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
172 dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__, num_ctlr_slots, first_device_num);
174 /* Decide which slots are supported */
176 /*********************************
177 * is_hot_plug is the slot mask
178 *********************************/
179 FirstSupported = first_device_num;
180 LastSupported = FirstSupported + num_ctlr_slots - 1;
183 LastSupported = 0x1F;
186 dbg("FirstSupported = %d, LastSupported = %d\n", FirstSupported, LastSupported);
188 /* Save PCI configuration space for all devices in supported slots */
189 dbg("%s: pci_bus->number = %x\n", __FUNCTION__, pci_bus->number);
190 pci_bus->number = busnumber;
191 dbg("%s: bus = %x, dev = %x\n", __FUNCTION__, busnumber, device);
192 for (device = FirstSupported; device <= LastSupported; device++) {
194 rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
196 if (ID != 0xFFFFFFFF) { /* device in slot */
197 dbg("%s: ID = %x\n", __FUNCTION__, ID);
198 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
202 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
206 dbg("class_code = %x, header_type = %x\n", class_code, header_type);
208 /* If multi-function device, set max_functions to 8 */
209 if (header_type & 0x80)
218 dbg("%s: In do loop\n", __FUNCTION__);
220 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* P-P Bridge */
221 /* Recurse the subordinate bus
222 * get the subordinate bus number
224 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, function),
225 PCI_SECONDARY_BUS, &secondary_bus);
229 sub_bus = (int) secondary_bus;
231 /* Save secondary bus cfg spc with this recursive call. */
232 rc = pciehp_save_config(ctrl, sub_bus, 0, 0);
239 new_slot = pciehp_slot_find(busnumber, device, index++);
241 dbg("%s: new_slot = %p bus %x dev %x fun %x\n",
242 __FUNCTION__, new_slot, busnumber, device, index-1);
244 while (new_slot && (new_slot->function != (u8) function)) {
245 new_slot = pciehp_slot_find(busnumber, device, index++);
246 dbg("%s: while loop, new_slot = %p bus %x dev %x fun %x\n",
247 __FUNCTION__, new_slot, busnumber, device, index-1);
250 /* Setup slot structure. */
251 new_slot = pciehp_slot_create(busnumber);
252 dbg("%s: if, new_slot = %p bus %x dev %x fun %x\n",
253 __FUNCTION__, new_slot, busnumber, device, function);
255 if (new_slot == NULL)
259 new_slot->bus = (u8) busnumber;
260 new_slot->device = (u8) device;
261 new_slot->function = (u8) function;
262 new_slot->is_a_board = 1;
263 new_slot->switch_save = 0x10;
264 /* In case of unsupported board */
265 new_slot->status = DevError;
266 new_slot->pci_dev = pci_find_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
267 dbg("new_slot->pci_dev = %p\n", new_slot->pci_dev);
269 for (cloop = 0; cloop < 0x20; cloop++) {
270 rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, function), cloop << 2,
271 (u32 *) & (new_slot->config_space [cloop]));
272 /* dbg("new_slot->config_space[%x] = %x\n", cloop, new_slot->config_space[cloop]); */
281 /* this loop skips to the next present function
282 * reading in Class Code and Header type.
285 while ((function < max_functions)&&(!stop_it)) {
286 dbg("%s: In while loop \n", __FUNCTION__);
287 rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
289 if (ID == 0xFFFFFFFF) { /* nothing there. */
291 dbg("Nothing there\n");
292 } else { /* Something there */
293 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, function), 0x0B,
298 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE,
303 dbg("class_code = %x, header_type = %x\n", class_code, header_type);
308 } while (function < max_functions);
309 } /* End of IF (device in slot?) */
310 else if (is_hot_plug) {
311 /* Setup slot structure with entry for empty slot */
312 new_slot = pciehp_slot_create(busnumber);
314 if (new_slot == NULL) {
317 dbg("new_slot = %p, bus = %x, dev = %x, fun = %x\n", new_slot,
318 new_slot->bus, new_slot->device, new_slot->function);
320 new_slot->bus = (u8) busnumber;
321 new_slot->device = (u8) device;
322 new_slot->function = 0;
323 new_slot->is_a_board = 0;
324 new_slot->presence_save = 0;
325 new_slot->switch_save = 0;
327 } /* End of FOR loop */
329 dbg("%s: Exit\n", __FUNCTION__);
335 * pciehp_save_slot_config
337 * Saves configuration info for all PCI devices in a given slot
338 * including subordinate busses.
340 * returns 0 if success
342 int pciehp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot)
354 struct pci_bus lpci_bus, *pci_bus;
355 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
357 pci_bus->number = new_slot->bus;
361 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
363 if (ID != 0xFFFFFFFF) { /* device in slot */
364 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
366 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
368 if (header_type & 0x80) /* Multi-function device */
376 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
377 /* Recurse the subordinate bus */
378 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, function),
379 PCI_SECONDARY_BUS, &secondary_bus);
381 sub_bus = (int) secondary_bus;
383 /* Save the config headers for the secondary bus. */
384 rc = pciehp_save_config(ctrl, sub_bus, 0, 0);
391 new_slot->status = 0;
393 for (cloop = 0; cloop < 0x20; cloop++) {
394 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, function),
395 cloop << 2, (u32 *) & (new_slot->config_space [cloop]));
402 /* this loop skips to the next present function
403 * reading in the Class Code and the Header type.
406 while ((function < max_functions) && (!stop_it)) {
407 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
409 if (ID == 0xFFFFFFFF) { /* nothing there. */
411 } else { /* Something there */
412 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
414 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE,
421 } while (function < max_functions);
422 } /* End of IF (device in slot?) */
432 * pciehp_save_used_resources
434 * Stores used resource information for existing boards. this is
435 * for boards that were in the system when this driver was loaded.
436 * this function is for hot plug ADD
438 * returns 0 if success
439 * if disable == 1(DISABLE_CARD),
440 * it loops for all functions of the slot and disables them.
441 * else, it just get resources of the function and return.
443 int pciehp_save_used_resources (struct controller *ctrl, struct pci_func *func, int disable)
451 u16 w_base, w_length;
458 struct pci_resource *mem_node = NULL;
459 struct pci_resource *p_mem_node = NULL;
460 struct pci_resource *t_mem_node;
461 struct pci_resource *io_node;
462 struct pci_resource *bus_node;
463 struct pci_bus lpci_bus, *pci_bus;
464 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
468 func = pciehp_slot_find(func->bus, func->device, index++);
470 while ((func != NULL) && func->is_a_board) {
471 pci_bus->number = func->bus;
472 devfn = PCI_DEVFN(func->device, func->function);
474 /* Save the command register */
475 pci_bus_read_config_word (pci_bus, devfn, PCI_COMMAND, &save_command);
480 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
483 /* Check for Bridge */
484 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
486 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
487 dbg("Save_used_res of PCI bridge b:d=0x%x:%x, sc=0x%x\n", func->bus, func->device, save_command);
489 /* Clear Bridge Control Register */
491 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
494 pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
495 pci_bus_read_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
497 bus_node =(struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
501 bus_node->base = (ulong)secondary_bus;
502 bus_node->length = (ulong)(temp_byte - secondary_bus + 1);
504 bus_node->next = func->bus_head;
505 func->bus_head = bus_node;
507 /* Save IO base and Limit registers */
508 pci_bus_read_config_byte (pci_bus, devfn, PCI_IO_BASE, &temp_byte);
510 pci_bus_read_config_byte (pci_bus, devfn, PCI_IO_LIMIT, &temp_byte);
513 if ((base <= length) && (!disable || (save_command & PCI_COMMAND_IO))) {
514 io_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
518 io_node->base = (ulong)(base & PCI_IO_RANGE_MASK) << 8;
519 io_node->length = (ulong)(length - base + 0x10) << 8;
521 io_node->next = func->io_head;
522 func->io_head = io_node;
525 /* Save memory base and Limit registers */
526 pci_bus_read_config_word (pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
527 pci_bus_read_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
529 if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
530 mem_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
534 mem_node->base = (ulong)w_base << 16;
535 mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
537 mem_node->next = func->mem_head;
538 func->mem_head = mem_node;
540 /* Save prefetchable memory base and Limit registers */
541 pci_bus_read_config_word (pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
542 pci_bus_read_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
544 if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
545 p_mem_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
549 p_mem_node->base = (ulong)w_base << 16;
550 p_mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
552 p_mem_node->next = func->p_mem_head;
553 func->p_mem_head = p_mem_node;
555 } else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
556 dbg("Save_used_res of PCI adapter b:d=0x%x:%x, sc=0x%x\n", func->bus, func->device, save_command);
558 /* Figure out IO and memory base lengths */
559 for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
560 pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base);
562 temp_register = 0xFFFFFFFF;
563 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
564 pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp_register);
567 pci_bus_write_config_dword (pci_bus, devfn, cloop, save_base);
573 base = temp_register;
575 if ((base & PCI_BASE_ADDRESS_SPACE_IO) && (!disable || (save_command & PCI_COMMAND_IO))) {
577 /* set temp_register = amount of IO space requested */
578 base = base & 0xFFFFFFFCL;
581 io_node = (struct pci_resource *) kmalloc(sizeof (struct pci_resource), GFP_KERNEL);
585 io_node->base = (ulong)save_base & PCI_BASE_ADDRESS_IO_MASK;
586 io_node->length = (ulong)base;
587 dbg("sur adapter: IO bar=0x%x(length=0x%x)\n", io_node->base, io_node->length);
589 io_node->next = func->io_head;
590 func->io_head = io_node;
591 } else { /* map Memory */
592 int prefetchable = 1;
593 /* struct pci_resources **res_node; */
594 char *res_type_str = "PMEM";
597 t_mem_node = (struct pci_resource *) kmalloc(sizeof (struct pci_resource), GFP_KERNEL);
601 if (!(base & PCI_BASE_ADDRESS_MEM_PREFETCH) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
603 mem_node = t_mem_node;
606 p_mem_node = t_mem_node;
608 base = base & 0xFFFFFFF0L;
611 switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
612 case PCI_BASE_ADDRESS_MEM_TYPE_32:
614 p_mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
615 p_mem_node->length = (ulong)base;
616 dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n", res_type_str,
617 p_mem_node->base, p_mem_node->length);
619 p_mem_node->next = func->p_mem_head;
620 func->p_mem_head = p_mem_node;
622 mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
623 mem_node->length = (ulong)base;
624 dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n", res_type_str,
625 mem_node->base, mem_node->length);
627 mem_node->next = func->mem_head;
628 func->mem_head = mem_node;
631 case PCI_BASE_ADDRESS_MEM_TYPE_64:
632 pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
633 base64 = temp_register2;
634 base64 = (base64 << 32) | save_base;
636 if (temp_register2) {
637 dbg("sur adapter: 64 %s high dword of base64(0x%x:%x) masked to 0\n",
638 res_type_str, temp_register2, (u32)base64);
639 base64 &= 0x00000000FFFFFFFFL;
643 p_mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
644 p_mem_node->length = base;
645 dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n", res_type_str,
646 p_mem_node->base, p_mem_node->length);
648 p_mem_node->next = func->p_mem_head;
649 func->p_mem_head = p_mem_node;
651 mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
652 mem_node->length = base;
653 dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n", res_type_str,
654 mem_node->base, mem_node->length);
656 mem_node->next = func->mem_head;
657 func->mem_head = mem_node;
662 dbg("asur: reserved BAR type=0x%x\n", temp_register);
666 } /* End of base register loop */
667 } else { /* Some other unknown header type */
668 dbg("Save_used_res of PCI unknown type b:d=0x%x:%x. skip.\n", func->bus, func->device);
671 /* find the next device in this slot */
674 func = pciehp_slot_find(func->bus, func->device, index++);
682 * pciehp_return_board_resources
684 * this routine returns all resources allocated to a board to
685 * the available pool.
687 * returns 0 if success
689 int pciehp_return_board_resources(struct pci_func * func, struct resource_lists * resources)
692 struct pci_resource *node;
693 struct pci_resource *t_node;
694 dbg("%s\n", __FUNCTION__);
699 node = func->io_head;
700 func->io_head = NULL;
703 return_resource(&(resources->io_head), node);
707 node = func->mem_head;
708 func->mem_head = NULL;
711 return_resource(&(resources->mem_head), node);
715 node = func->p_mem_head;
716 func->p_mem_head = NULL;
719 return_resource(&(resources->p_mem_head), node);
723 node = func->bus_head;
724 func->bus_head = NULL;
727 return_resource(&(resources->bus_head), node);
731 rc |= pciehp_resource_sort_and_combine(&(resources->mem_head));
732 rc |= pciehp_resource_sort_and_combine(&(resources->p_mem_head));
733 rc |= pciehp_resource_sort_and_combine(&(resources->io_head));
734 rc |= pciehp_resource_sort_and_combine(&(resources->bus_head));
741 * pciehp_destroy_resource_list
743 * Puts node back in the resource list pointed to by head
745 void pciehp_destroy_resource_list (struct resource_lists * resources)
747 struct pci_resource *res, *tres;
749 res = resources->io_head;
750 resources->io_head = NULL;
758 res = resources->mem_head;
759 resources->mem_head = NULL;
767 res = resources->p_mem_head;
768 resources->p_mem_head = NULL;
776 res = resources->bus_head;
777 resources->bus_head = NULL;
788 * pciehp_destroy_board_resources
790 * Puts node back in the resource list pointed to by head
792 void pciehp_destroy_board_resources (struct pci_func * func)
794 struct pci_resource *res, *tres;
797 func->io_head = NULL;
805 res = func->mem_head;
806 func->mem_head = NULL;
814 res = func->p_mem_head;
815 func->p_mem_head = NULL;
823 res = func->bus_head;
824 func->bus_head = NULL;