2 * drivers/pcmcia/m32r_cfc.c
4 * Device driver for the CFC functionality of M32R.
6 * Copyright (c) 2001, 2002, 2003, 2004
7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/config.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/timer.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <linux/ioport.h>
23 #include <linux/delay.h>
24 #include <linux/workqueue.h>
25 #include <linux/interrupt.h>
26 #include <linux/device.h>
29 #include <asm/bitops.h>
30 #include <asm/system.h>
32 #include <pcmcia/version.h>
33 #include <pcmcia/cs_types.h>
34 #include <pcmcia/ss.h>
35 #include <pcmcia/cs.h>
37 #undef MAX_IO_WIN /* FIXME */
39 #undef MAX_WIN /* FIXME */
45 static int m32r_cfc_debug;
46 module_param(m32r_cfc_debug, int, 0644);
47 #define debug(lvl, fmt, arg...) do { \
48 if (m32r_cfc_debug > (lvl)) \
49 printk(KERN_DEBUG "m32r_cfc: " fmt , ## arg); \
52 #define debug(n, args...) do { } while (0)
55 /* Poll status interval -- 0 means default to interrupt */
56 static int poll_interval = 0;
58 typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
60 typedef struct pcc_socket {
62 struct pcmcia_socket socket;
66 u_long base; /* PCC register base */
67 u_char cs_irq1, cs_irq2, intr;
68 pccard_io_map io_map[MAX_IO_WIN];
69 pccard_mem_map mem_map[MAX_WIN];
72 pcc_as_t current_space;
75 struct proc_dir_entry *proc;
79 static int pcc_sockets = 0;
80 static pcc_socket_t socket[M32R_MAX_PCC] = {
84 /*====================================================================*/
86 static unsigned int pcc_get(u_short, unsigned int);
87 static void pcc_set(u_short, unsigned int , unsigned int );
89 static spinlock_t pcc_lock = SPIN_LOCK_UNLOCKED;
91 #if !defined(CONFIG_PLAT_USRV)
92 static inline u_long pcc_port2addr(unsigned long port, int size) {
96 if (size == 1) { /* byte access */
99 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
100 } else if (size == 2)
101 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
105 #else /* CONFIG_PLAT_USRV */
106 static inline u_long pcc_port2addr(unsigned long port, int size) {
108 u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
110 if (size == 1) { /* byte access */
114 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
115 } else if (size == 2) /* word access */
116 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
120 #endif /* CONFIG_PLAT_USRV */
122 void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
123 size_t nmemb, int flag)
126 unsigned char *bp = (unsigned char *)buf;
129 debug(3, "m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
130 "size=%u, nmemb=%d, flag=%d\n",
131 sock, port, buf, size, nmemb, flag);
133 addr = pcc_port2addr(port, 1);
135 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
138 debug(3, "m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
140 spin_lock_irqsave(&pcc_lock, flags);
144 spin_unlock_irqrestore(&pcc_lock, flags);
147 void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
148 size_t nmemb, int flag)
151 unsigned short *bp = (unsigned short *)buf;
154 debug(3, "m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
155 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
156 sock, port, buf, size, nmemb, flag);
159 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
162 printk("m32r_cfc: ioread_word :insw \n");
164 addr = pcc_port2addr(port, 2);
166 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
169 debug(3, "m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
171 spin_lock_irqsave(&pcc_lock, flags);
175 spin_unlock_irqrestore(&pcc_lock, flags);
178 void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
179 size_t nmemb, int flag)
182 unsigned char *bp = (unsigned char *)buf;
185 debug(3, "m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
186 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
187 sock, port, buf, size, nmemb, flag);
190 addr = pcc_port2addr(port, 1);
192 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
195 debug(3, "m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
197 spin_lock_irqsave(&pcc_lock, flags);
200 spin_unlock_irqrestore(&pcc_lock, flags);
203 void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
204 size_t nmemb, int flag)
207 unsigned short *bp = (unsigned short *)buf;
210 debug(3, "m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
211 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
212 sock, port, buf, size, nmemb, flag);
215 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
218 printk("m32r_cfc: iowrite_word :outsw \n");
220 addr = pcc_port2addr(port, 2);
222 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
227 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
232 debug(3, "m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
234 spin_lock_irqsave(&pcc_lock, flags);
237 spin_unlock_irqrestore(&pcc_lock, flags);
240 /*====================================================================*/
242 #define IS_ALIVE 0x8000
244 typedef struct pcc_t {
249 static pcc_t pcc[] = {
250 #if !defined(CONFIG_PLAT_USRV)
251 { "m32r_cfc", 0 }, { "", 0 },
252 #else /* CONFIG_PLAT_USRV */
253 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
254 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
255 #endif /* CONFIG_PLAT_USRV */
258 static irqreturn_t pcc_interrupt(int, void *, struct pt_regs *);
260 /*====================================================================*/
262 static struct timer_list poll_timer;
264 static unsigned int pcc_get(u_short sock, unsigned int reg)
266 unsigned int val = inw(reg);
267 debug(3, "m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
272 static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
275 debug(3, "m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
278 /*======================================================================
280 See if a card is present, powered up, in IO mode, and already
281 bound to a (non PC Card) Linux driver. We leave these alone.
283 We make an exception for cards that seem to be serial devices.
285 ======================================================================*/
287 static int __init is_alive(u_short sock)
291 debug(3, "m32r_cfc: is_alive:\n");
294 stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
297 printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
298 debug(3, "m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
303 static void add_pcc_socket(ulong base, int irq, ulong mapaddr, ioaddr_t ioaddr)
305 pcc_socket_t *t = &socket[pcc_sockets];
307 debug(3, "m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
308 "mapaddr=%#lx, ioaddr=%08x\n",
309 base, irq, mapaddr, ioaddr);
313 t->mapaddr = mapaddr;
314 #if !defined(CONFIG_PLAT_USRV)
317 t->cs_irq1 = irq; // insert irq
318 t->cs_irq2 = irq + 1; // eject irq
319 #else /* CONFIG_PLAT_USRV */
322 t->cs_irq1 = 0; // insert irq
323 t->cs_irq2 = 0; // eject irq
324 #endif /* CONFIG_PLAT_USRV */
326 if (is_alive(pcc_sockets))
327 t->flags |= IS_ALIVE;
330 #if !defined(CONFIG_PLAT_USRV)
331 request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
332 #else /* CONFIG_PLAT_USRV */
334 unsigned int reg_base;
336 reg_base = (unsigned int)PLD_CFRSTCR;
337 reg_base |= pcc_sockets << 8;
338 request_region(reg_base, 0x20, "m32r_cfc");
340 #endif /* CONFIG_PLAT_USRV */
341 printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
342 printk("pcc at 0x%08lx\n", t->base);
344 /* Update socket interrupt information, capabilities */
345 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
346 t->socket.map_size = M32R_PCC_MAPSIZE;
347 t->socket.io_offset = ioaddr; /* use for io access offset */
348 t->socket.irq_mask = 0;
349 #if !defined(CONFIG_PLAT_USRV)
350 t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */
351 #else /* CONFIG_PLAT_USRV */
352 t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
353 #endif /* CONFIG_PLAT_USRV */
355 #ifndef CONFIG_PLAT_USRV
356 /* insert interrupt */
357 request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
358 /* eject interrupt */
359 request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
361 debug(3, "m32r_cfc: enable CFMSK, RDYSEL\n");
362 pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
363 #endif /* CONFIG_PLAT_USRV */
364 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
365 pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
373 /*====================================================================*/
375 static irqreturn_t pcc_interrupt(int irq, void *dev, struct pt_regs *regs)
381 debug(3, "m32r_cfc: pcc_interrupt: irq=%d, dev=%p, regs=%p\n",
383 for (i = 0; i < pcc_sockets; i++) {
384 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
388 debug(3, "m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
390 events |= SS_DETECT; /* insert or eject */
392 pcmcia_parse_events(&socket[i].socket, events);
394 debug(3, "m32r_cfc: pcc_interrupt: done\n");
396 return IRQ_RETVAL(handled);
397 } /* pcc_interrupt */
399 static void pcc_interrupt_wrapper(u_long data)
401 debug(3, "m32r_cfc: pcc_interrupt_wrapper:\n");
402 pcc_interrupt(0, NULL, NULL);
403 init_timer(&poll_timer);
404 poll_timer.expires = jiffies + poll_interval;
405 add_timer(&poll_timer);
408 /*====================================================================*/
410 static int _pcc_get_status(u_short sock, u_int *value)
414 debug(3, "m32r_cfc: _pcc_get_status:\n");
415 status = pcc_get(sock, (unsigned int)PLD_CFSTS);
416 *value = (status) ? SS_DETECT : 0;
417 debug(3, "m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
419 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
421 /* enable CF power */
422 status = inw((unsigned int)PLD_CPCR);
423 if (!(status & PLD_CPCR_CF)) {
424 debug(3, "m32r_cfc: _pcc_get_status: "
425 "power on (CPCR=0x%08x)\n", status);
426 status |= PLD_CPCR_CF;
427 outw(status, (unsigned int)PLD_CPCR);
430 *value |= SS_POWERON;
432 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
435 *value |= SS_READY; /* always ready */
438 /* disable CF power */
439 status = inw((unsigned int)PLD_CPCR);
440 status &= ~PLD_CPCR_CF;
441 outw(status, (unsigned int)PLD_CPCR);
443 debug(3, "m32r_cfc: _pcc_get_status: "
444 "power off (CPCR=0x%08x)\n", status);
446 #elif defined(CONFIG_PLAT_MAPPI2)
448 status = pcc_get(sock, (unsigned int)PLD_CPCR);
449 if (status == 0) { /* power off */
450 pcc_set(sock, (unsigned int)PLD_CPCR, 1);
451 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
454 status = pcc_get(sock, (unsigned int)PLD_CFBUFCR);
455 if (status != 0) { /* buffer off */
456 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
458 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
459 udelay(25); /* for IDE reset */
460 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
461 mdelay(2); /* for IDE reset */
463 *value |= SS_POWERON;
468 #error no platform configuration
470 debug(3, "m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
475 /*====================================================================*/
477 static int _pcc_get_socket(u_short sock, socket_state_t *state)
479 // pcc_socket_t *t = &socket[sock];
481 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
483 state->csc_mask = SS_DETECT;
484 state->csc_mask |= SS_READY;
486 state->Vcc = 33; /* 3.3V fixed */
489 debug(3, "m32r_cfc: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
490 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
491 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
495 /*====================================================================*/
497 static int _pcc_set_socket(u_short sock, socket_state_t *state)
499 #if defined(CONFIG_PLAT_MAPPI2)
502 debug(3, "m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
503 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
504 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
506 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
508 if ((state->Vcc != 50) && (state->Vcc != 33))
510 /* accept 5V and 3.3V */
512 #elif defined(CONFIG_PLAT_MAPPI2)
517 if (state->Vcc == 50) {
525 if (state->flags & SS_RESET) {
526 debug(3, ":RESET\n");
527 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
529 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
531 if (state->flags & SS_OUTPUT_ENA){
532 debug(3, ":OUTPUT_ENA\n");
534 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
536 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
540 if(state->flags & SS_IOCARD){
543 if (state->flags & SS_PWR_AUTO) {
544 debug(3, ":PWR_AUTO");
546 if (state->csc_mask & SS_DETECT)
547 debug(3, ":csc-SS_DETECT");
548 if (state->flags & SS_IOCARD) {
549 if (state->csc_mask & SS_STSCHG)
552 if (state->csc_mask & SS_BATDEAD)
553 debug(3, ":BATDEAD");
554 if (state->csc_mask & SS_BATWARN)
555 debug(3, ":BATWARN");
556 if (state->csc_mask & SS_READY)
564 /*====================================================================*/
566 static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
570 debug(3, "m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
571 "%#4.4x-%#4.4x)\n", sock, io->map, io->flags,
572 io->speed, io->start, io->stop);
578 /*====================================================================*/
580 static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
583 u_char map = mem->map;
585 pcc_socket_t *t = &socket[sock];
587 debug(3, "m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
588 "%#5.5lx, %#5.5x)\n", sock, map, mem->flags,
589 mem->speed, mem->static_start, mem->card_start);
594 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
601 if ((mem->flags & MAP_ACTIVE) == 0) {
602 t->current_space = as_none;
609 if (mem->flags & MAP_ATTRIB) {
610 t->current_space = as_attr;
612 t->current_space = as_comm;
618 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
619 mem->static_start = addr + mem->card_start;
625 #if 0 /* driver model ordering issue */
626 /*======================================================================
628 Routines for accessing socket information and register dumps via
631 ======================================================================*/
633 static ssize_t show_info(struct class_device *class_dev, char *buf)
635 pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
638 return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
639 pcc[s->type].name, s->base);
642 static ssize_t show_exca(struct class_device *class_dev, char *buf)
649 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
650 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
653 /*====================================================================*/
655 /* this is horribly ugly... proper locking needs to be done here at
657 #define LOCKED(x) do { \
659 unsigned long flags; \
660 spin_lock_irqsave(&pcc_lock, flags); \
662 spin_unlock_irqrestore(&pcc_lock, flags); \
667 static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
669 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
671 if (socket[sock].flags & IS_ALIVE) {
672 debug(3, "m32r_cfc: pcc_get_status: sock(%d) -EINVAL\n", sock);
676 debug(3, "m32r_cfc: pcc_get_status: sock(%d)\n", sock);
677 LOCKED(_pcc_get_status(sock, value));
680 static int pcc_get_socket(struct pcmcia_socket *s, socket_state_t *state)
682 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
684 if (socket[sock].flags & IS_ALIVE) {
685 debug(3, "m32r_cfc: pcc_get_socket: sock(%d) -EINVAL\n", sock);
688 debug(3, "m32r_cfc: pcc_get_socket: sock(%d)\n", sock);
689 LOCKED(_pcc_get_socket(sock, state));
692 static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
694 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
696 if (socket[sock].flags & IS_ALIVE) {
697 debug(3, "m32r_cfc: pcc_set_socket: sock(%d) -EINVAL\n", sock);
700 debug(3, "m32r_cfc: pcc_set_socket: sock(%d)\n", sock);
701 LOCKED(_pcc_set_socket(sock, state));
704 static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
706 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
708 if (socket[sock].flags & IS_ALIVE) {
709 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d) -EINVAL\n", sock);
712 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d)\n", sock);
713 LOCKED(_pcc_set_io_map(sock, io));
716 static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
718 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
720 if (socket[sock].flags & IS_ALIVE) {
721 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
724 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d)\n", sock);
725 LOCKED(_pcc_set_mem_map(sock, mem));
728 static int pcc_init(struct pcmcia_socket *s)
730 debug(3, "m32r_cfc: pcc_init()\n");
734 static int pcc_suspend(struct pcmcia_socket *sock)
736 debug(3, "m32r_cfc: pcc_suspend()\n");
737 return pcc_set_socket(sock, &dead_socket);
740 static struct pccard_operations pcc_operations = {
742 .suspend = pcc_suspend,
743 .get_status = pcc_get_status,
744 .get_socket = pcc_get_socket,
745 .set_socket = pcc_set_socket,
746 .set_io_map = pcc_set_io_map,
747 .set_mem_map = pcc_set_mem_map,
750 /*====================================================================*/
752 static int m32r_pcc_suspend(struct device *dev, u32 state, u32 level)
755 if (level == SUSPEND_SAVE_STATE)
756 ret = pcmcia_socket_dev_suspend(dev, state);
760 static int m32r_pcc_resume(struct device *dev, u32 level)
763 if (level == RESUME_RESTORE_STATE)
764 ret = pcmcia_socket_dev_resume(dev);
769 static struct device_driver pcc_driver = {
771 .bus = &platform_bus_type,
772 .suspend = m32r_pcc_suspend,
773 .resume = m32r_pcc_resume,
776 static struct platform_device pcc_device = {
781 /*====================================================================*/
783 static int __init init_m32r_pcc(void)
787 ret = driver_register(&pcc_driver);
791 ret = platform_device_register(&pcc_device);
793 driver_unregister(&pcc_driver);
797 #if defined(CONFIG_PLAT_MAPPI2)
798 pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
799 pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
804 #if !defined(CONFIG_PLAT_USRV)
805 add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
807 #else /* CONFIG_PLAT_USRV */
812 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
813 base = (ulong)PLD_CFRSTCR;
814 base = base | (i << 8);
815 ioaddr = (i + 1) << 12;
816 mapaddr = CFC_ATTR_MAPBASE | (i << 20);
817 add_pcc_socket(base, 0, mapaddr, ioaddr);
820 #endif /* CONFIG_PLAT_USRV */
822 if (pcc_sockets == 0) {
823 printk("socket is not found.\n");
824 platform_device_unregister(&pcc_device);
825 driver_unregister(&pcc_driver);
829 /* Set up interrupt handler(s) */
831 for (i = 0 ; i < pcc_sockets ; i++) {
832 socket[i].socket.dev.dev = &pcc_device.dev;
833 socket[i].socket.ops = &pcc_operations;
834 socket[i].socket.owner = THIS_MODULE;
835 socket[i].number = i;
836 ret = pcmcia_register_socket(&socket[i].socket);
839 pcmcia_unregister_socket(&socket[i].socket);
842 #if 0 /* driver model ordering issue */
843 class_device_create_file(&socket[i].socket.dev,
844 &class_device_attr_info);
845 class_device_create_file(&socket[i].socket.dev,
846 &class_device_attr_exca);
850 /* Finally, schedule a polling interrupt */
851 if (poll_interval != 0) {
852 poll_timer.function = pcc_interrupt_wrapper;
854 init_timer(&poll_timer);
855 poll_timer.expires = jiffies + poll_interval;
856 add_timer(&poll_timer);
860 } /* init_m32r_pcc */
862 static void __exit exit_m32r_pcc(void)
866 for (i = 0; i < pcc_sockets; i++)
867 pcmcia_unregister_socket(&socket[i].socket);
869 platform_device_unregister(&pcc_device);
870 if (poll_interval != 0)
871 del_timer_sync(&poll_timer);
873 driver_unregister(&pcc_driver);
874 } /* exit_m32r_pcc */
876 module_init(init_m32r_pcc);
877 module_exit(exit_m32r_pcc);
878 MODULE_LICENSE("Dual MPL/GPL");
879 /*====================================================================*/