1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* NCR Quad 720 MCA SCSI Driver
5 * Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
8 #include <linux/blkdev.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/mca.h>
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
21 #include "ncr53c8xx.h"
25 static ncr_chip q720_chip __initdata = {
26 .device_id = PSEUDO_720_ID,
32 .features = FE_WIDE | FE_DIFF | FE_VARCLK,
35 MODULE_AUTHOR("James Bottomley");
36 MODULE_DESCRIPTION("NCR Quad 720 SCSI Driver");
37 MODULE_LICENSE("GPL");
39 #define NCR_Q720_VERSION "0.9"
41 /* We needs this helper because we have up to four hosts per struct device */
42 struct NCR_Q720_private {
50 struct Scsi_Host *hosts[4];
53 Scsi_Host_Template NCR_Q720_tpnt = {
54 .module = THIS_MODULE,
55 .proc_name = "NCR_Q720",
59 NCR_Q720_intr(int irq, void *data, struct pt_regs * regs)
61 struct NCR_Q720_private *p = (struct NCR_Q720_private *)data;
62 __u8 sir = (readb(p->mem_base + 0x0d) & 0xf0) >> 4;
65 sir |= ~p->irq_enable;
71 while((siop = ffz(sir)) < p->siops) {
73 ncr53c8xx_intr(irq, p->hosts[siop], regs);
79 NCR_Q720_probe_one(struct NCR_Q720_private *p, int siop,
80 int irq, int slot, __u32 paddr, __u32 vaddr)
82 struct ncr_device device;
85 __u8 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
86 __u8 differential = readb(vaddr + NCR_Q720_SCSR_OFFSET) & 0x20;
91 /* enable burst length 16 (FIXME: should allow this) */
93 /* force a siop reset */
95 writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
97 version = readb(vaddr + 0x18) >> 4;
99 memset(&device, 0, sizeof(struct ncr_device));
100 /* Initialise ncr_device structure with items required by ncr_attach. */
101 device.chip = q720_chip;
102 device.chip.revision_id = version;
103 device.host_id = scsi_id;
105 device.slot.base = paddr;
106 device.slot.base_c = paddr;
107 device.slot.base_v = vaddr;
108 device.slot.irq = irq;
109 device.differential = differential ? 2 : 0;
110 printk("Q720 probe unit %d (siop%d) at 0x%lx, diff = %d, vers = %d\n", unit, siop,
111 (unsigned long)paddr, differential, version);
113 p->hosts[siop] = ncr_attach(&NCR_Q720_tpnt, unit++, &device);
118 p->irq_enable |= (1<<siop);
119 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
120 /* clear the disable interrupt bit */
122 writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
124 error = scsi_add_host(p->hosts[siop], p->dev);
126 ncr53c8xx_release(p->hosts[siop]);
128 scsi_scan_host(p->hosts[siop]);
135 /* Detect a Q720 card. Note, because of the setup --- the chips are
136 * essentially connectecd to the MCA bus independently, it is easier
137 * to set them up as two separate host adapters, rather than one
138 * adapter with two channels */
140 NCR_Q720_probe(struct device *dev)
142 struct NCR_Q720_private *p;
143 static int banner = 1;
144 struct mca_device *mca_dev = to_mca_device(dev);
145 int slot = mca_dev->slot;
148 __u8 pos2, pos4, asr2, asr9, asr10;
150 __u32 base_addr, mem_size;
153 p = kmalloc(sizeof(*p), GFP_KERNEL);
157 memset(p, 0, sizeof(*p));
158 pos2 = mca_device_read_pos(mca_dev, 2);
160 pos2 |= NCR_Q720_POS2_BOARD_ENABLE | NCR_Q720_POS2_INTERRUPT_ENABLE;
161 mca_device_write_pos(mca_dev, 2, pos2);
163 io_base = (pos2 & NCR_Q720_POS2_IO_MASK) << NCR_Q720_POS2_IO_SHIFT;
167 printk(KERN_NOTICE "NCR Q720: Driver Version " NCR_Q720_VERSION "\n"
168 "NCR Q720: Copyright (c) 2003 by James.Bottomley@HansenPartnership.com\n"
172 io_base = mca_device_transform_ioport(mca_dev, io_base);
174 /* OK, this is phase one of the bootstrap, we now know the
175 * I/O space base address. All the configuration registers
176 * are mapped here (including pos) */
178 /* sanity check I/O mapping */
179 i = inb(io_base) | (inb(io_base+1)<<8);
180 if(i != NCR_Q720_MCA_ID) {
181 printk(KERN_ERR "NCR_Q720, adapter failed to I/O map registers correctly at 0x%x(0x%x)\n", io_base, i);
186 /* Phase II, find the ram base and memory map the board register */
187 pos4 = inb(io_base + 4);
188 /* enable streaming data */
190 outb(pos4, io_base + 4);
191 base_addr = (pos4 & 0x7e) << 20;
192 base_addr += (pos4 & 0x80) << 23;
193 asr10 = inb(io_base + 0x12);
194 base_addr += (asr10 & 0x80) << 24;
195 base_addr += (asr10 & 0x70) << 23;
197 /* OK, got the base addr, now we need to find the ram size,
198 * enable and map it */
199 asr9 = inb(io_base + 0x11);
200 i = (asr9 & 0xc0) >> 6;
204 mem_size = 1 << (19 + i);
206 /* enable the sram mapping */
209 /* disable the rom mapping */
212 outb(asr9, io_base + 0x11);
214 if(!request_mem_region(base_addr, mem_size, "NCR_Q720")) {
215 printk(KERN_ERR "NCR_Q720: Failed to claim memory region 0x%lx\n-0x%lx",
216 (unsigned long)base_addr,
217 (unsigned long)(base_addr + mem_size));
221 mem_base = (__u32)ioremap(base_addr, mem_size);
223 /* now also enable accesses in asr 2 */
224 asr2 = inb(io_base + 0x0a);
228 outb(asr2, io_base + 0x0a);
230 /* get the number of SIOPs (this should be 2 or 4) */
231 siops = ((asr2 & 0xe0) >> 5) + 1;
233 /* sanity check mapping (again) */
235 if(i != NCR_Q720_MCA_ID) {
236 printk(KERN_ERR "NCR_Q720, adapter failed to memory map registers correctly at 0x%lx(0x%x)\n", (unsigned long)base_addr, i);
240 irq = readb(mem_base + 5) & 0x0f;
243 /* now do the bus related transforms */
244 irq = mca_device_transform_irq(mca_dev, irq);
246 printk(KERN_NOTICE "NCR Q720: found in slot %d irq = %d mem base = 0x%lx siops = %d\n", slot, irq, (unsigned long)base_addr, siops);
247 printk(KERN_NOTICE "NCR Q720: On board ram %dk\n", mem_size/1024);
250 p->mem_base = mem_base;
251 p->phys_mem_base = base_addr;
252 p->mem_size = mem_size;
256 if (request_irq(irq, NCR_Q720_intr, SA_SHIRQ, "NCR_Q720", p)) {
257 printk(KERN_ERR "NCR_Q720: request irq %d failed\n", irq);
260 /* disable all the siop interrupts */
261 for(i = 0; i < siops; i++) {
262 __u32 reg_scsr1 = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
263 + i*NCR_Q720_SIOP_SHIFT + NCR_Q720_SCSR_OFFSET + 1;
264 __u8 scsr1 = readb(reg_scsr1);
266 writeb(scsr1, reg_scsr1);
269 /* plumb in all 720 chips */
270 for (i = 0; i < siops; i++) {
271 __u32 siop_v_base = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
272 + i*NCR_Q720_SIOP_SHIFT;
273 __u32 siop_p_base = base_addr + NCR_Q720_CHIP_REGISTER_OFFSET
274 + i*NCR_Q720_SIOP_SHIFT;
275 __u16 port = io_base + NCR_Q720_CHIP_REGISTER_OFFSET
276 + i*NCR_Q720_SIOP_SHIFT;
279 outb(0xff, port + 0x40);
280 outb(0x07, port + 0x41);
281 if ((err = NCR_Q720_probe_one(p, i, irq, slot,
282 siop_p_base, siop_v_base)) != 0)
283 printk("Q720: SIOP%d: probe failed, error = %d\n",
294 mca_device_set_claim(mca_dev, 1);
295 mca_device_set_name(mca_dev, "NCR_Q720");
296 dev_set_drvdata(dev, p);
301 iounmap((void *)mem_base);
302 release_mem_region(base_addr, mem_size);
310 NCR_Q720_remove_one(struct Scsi_Host *host)
312 scsi_remove_host(host);
313 ncr53c8xx_release(host);
317 NCR_Q720_remove(struct device *dev)
319 struct NCR_Q720_private *p = dev_get_drvdata(dev);
322 for (i = 0; i < p->siops; i++)
324 NCR_Q720_remove_one(p->hosts[i]);
326 iounmap((void *)p->mem_base);
327 release_mem_region(p->phys_mem_base, p->mem_size);
333 static short NCR_Q720_id_table[] = { NCR_Q720_MCA_ID, 0 };
335 struct mca_driver NCR_Q720_driver = {
336 .id_table = NCR_Q720_id_table,
339 .bus = &mca_bus_type,
340 .probe = NCR_Q720_probe,
341 .remove = __devexit_p(NCR_Q720_remove),
348 return mca_register_driver(&NCR_Q720_driver);
354 mca_unregister_driver(&NCR_Q720_driver);
357 module_init(NCR_Q720_init);
358 module_exit(NCR_Q720_exit);