2 * sata_promise.c - Promise SATA
4 * Copyright 2003-2004 Red Hat, Inc.
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
34 #include <linux/libata.h>
37 #define DRV_NAME "sata_promise"
38 #define DRV_VERSION "0.92"
42 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
44 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
45 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
46 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
47 PDC_TBG_MODE = 0x41, /* TBG mode */
48 PDC_FLASH_CTL = 0x44, /* Flash control register */
49 PDC_PCI_CTL = 0x48, /* PCI control and status register */
50 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
51 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
52 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
53 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
54 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
56 PDC_20621_SEQCTL = 0x400,
57 PDC_20621_SEQMASK = 0x480,
58 PDC_20621_GENERAL_CTL = 0x484,
59 PDC_20621_PAGE_SIZE = (32 * 1024),
61 /* chosen, not constant, values; we design our own DIMM mem map */
62 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
63 PDC_20621_DIMM_BASE = 0x00200000,
64 PDC_20621_DIMM_DATA = (64 * 1024),
65 PDC_DIMM_DATA_STEP = (256 * 1024),
66 PDC_DIMM_WINDOW_STEP = (8 * 1024),
67 PDC_DIMM_HOST_PRD = (6 * 1024),
68 PDC_DIMM_HOST_PKT = (128 * 0),
69 PDC_DIMM_HPKT_PRD = (128 * 1),
70 PDC_DIMM_ATA_PKT = (128 * 2),
71 PDC_DIMM_APKT_PRD = (128 * 3),
72 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
73 PDC_PAGE_WINDOW = 0x40,
74 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
75 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
76 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
78 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
80 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
82 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
83 (1<<8) | (1<<9) | (1<<10),
85 board_2037x = 0, /* FastTrak S150 TX2plus */
86 board_20319 = 1, /* FastTrak S150 TX4 */
87 board_20621 = 2, /* FastTrak S150 SX4 */
89 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
91 PDC_FLAG_20621 = (1 << 30), /* we have a 20621 */
92 PDC_RESET = (1 << 11), /* HDMA reset */
95 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
97 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
98 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
99 PDC_MAX_DIMM_MODULE = 0x02,
100 PDC_I2C_CONTROL_OFFSET = 0x48,
101 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
102 PDC_DIMM0_CONTROL_OFFSET = 0x80,
103 PDC_DIMM1_CONTROL_OFFSET = 0x84,
104 PDC_SDRAM_CONTROL_OFFSET = 0x88,
105 PDC_I2C_WRITE = 0x00000000,
106 PDC_I2C_READ = 0x00000040,
107 PDC_I2C_START = 0x00000080,
108 PDC_I2C_MASK_INT = 0x00000020,
109 PDC_I2C_COMPLETE = 0x00010000,
110 PDC_I2C_NO_ACK = 0x00100000,
111 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
112 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
113 PDC_DIMM_SPD_ROW_NUM = 3,
114 PDC_DIMM_SPD_COLUMN_NUM = 4,
115 PDC_DIMM_SPD_MODULE_ROW = 5,
116 PDC_DIMM_SPD_TYPE = 11,
117 PDC_DIMM_SPD_FRESH_RATE = 12,
118 PDC_DIMM_SPD_BANK_NUM = 17,
119 PDC_DIMM_SPD_CAS_LATENCY = 18,
120 PDC_DIMM_SPD_ATTRIBUTE = 21,
121 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
122 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
123 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
124 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
125 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
126 PDC_CTL_STATUS = 0x08,
127 PDC_DIMM_WINDOW_CTLR = 0x0C,
128 PDC_TIME_CONTROL = 0x3C,
129 PDC_TIME_PERIOD = 0x40,
130 PDC_TIME_COUNTER = 0x44,
131 PDC_GENERAL_CTLR = 0x484,
132 PCI_PLL_INIT = 0x8A531824,
133 PCI_X_TCOUNT = 0xEE1E5CFF
137 struct pdc_port_priv {
138 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
143 struct pdc_host_priv {
146 unsigned int doing_hdma;
147 unsigned int hdma_prod;
148 unsigned int hdma_cons;
150 struct ata_queued_cmd *qc;
152 unsigned long pkt_ofs;
157 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
158 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
159 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
160 static void pdc_dma_start(struct ata_queued_cmd *qc);
161 static void pdc20621_dma_start(struct ata_queued_cmd *qc);
162 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
163 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
164 static void pdc_eng_timeout(struct ata_port *ap);
165 static void pdc_20621_phy_reset (struct ata_port *ap);
166 static int pdc_port_start(struct ata_port *ap);
167 static void pdc_port_stop(struct ata_port *ap);
168 static void pdc_phy_reset(struct ata_port *ap);
169 static void pdc_fill_sg(struct ata_queued_cmd *qc);
170 static void pdc20621_fill_sg(struct ata_queued_cmd *qc);
171 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
172 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
173 static void pdc20621_host_stop(struct ata_host_set *host_set);
174 static inline void pdc_dma_complete (struct ata_port *ap,
175 struct ata_queued_cmd *qc, int have_err);
176 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
177 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
178 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
179 u32 device, u32 subaddr, u32 *pdata);
180 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
181 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
182 #ifdef ATA_VERBOSE_DEBUG
183 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
184 void *psource, u32 offset, u32 size);
186 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
187 void *psource, u32 offset, u32 size);
190 static Scsi_Host_Template pdc_sata_sht = {
191 .module = THIS_MODULE,
193 .queuecommand = ata_scsi_queuecmd,
194 .eh_strategy_handler = ata_scsi_error,
195 .can_queue = ATA_DEF_QUEUE,
196 .this_id = ATA_SHT_THIS_ID,
197 .sg_tablesize = LIBATA_MAX_PRD,
198 .max_sectors = ATA_MAX_SECTORS,
199 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
200 .emulated = ATA_SHT_EMULATED,
201 .use_clustering = ATA_SHT_USE_CLUSTERING,
202 .proc_name = DRV_NAME,
203 .dma_boundary = ATA_DMA_BOUNDARY,
204 .slave_configure = ata_scsi_slave_config,
205 .bios_param = ata_std_bios_param,
208 static struct ata_port_operations pdc_sata_ops = {
209 .port_disable = ata_port_disable,
210 .tf_load = pdc_tf_load_mmio,
211 .tf_read = ata_tf_read_mmio,
212 .check_status = ata_check_status_mmio,
213 .exec_command = pdc_exec_command_mmio,
214 .phy_reset = pdc_phy_reset,
215 .bmdma_start = pdc_dma_start,
216 .fill_sg = pdc_fill_sg,
217 .eng_timeout = pdc_eng_timeout,
218 .irq_handler = pdc_interrupt,
219 .scr_read = pdc_sata_scr_read,
220 .scr_write = pdc_sata_scr_write,
221 .port_start = pdc_port_start,
222 .port_stop = pdc_port_stop,
225 static struct ata_port_operations pdc_20621_ops = {
226 .port_disable = ata_port_disable,
227 .tf_load = pdc_tf_load_mmio,
228 .tf_read = ata_tf_read_mmio,
229 .check_status = ata_check_status_mmio,
230 .exec_command = pdc_exec_command_mmio,
231 .phy_reset = pdc_20621_phy_reset,
232 .bmdma_start = pdc20621_dma_start,
233 .fill_sg = pdc20621_fill_sg,
234 .eng_timeout = pdc_eng_timeout,
235 .irq_handler = pdc20621_interrupt,
236 .port_start = pdc_port_start,
237 .port_stop = pdc_port_stop,
238 .host_stop = pdc20621_host_stop,
241 static struct ata_port_info pdc_port_info[] = {
244 .sht = &pdc_sata_sht,
245 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
246 ATA_FLAG_SRST | ATA_FLAG_MMIO,
247 .pio_mask = 0x03, /* pio3-4 */
248 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
249 .port_ops = &pdc_sata_ops,
254 .sht = &pdc_sata_sht,
255 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
256 ATA_FLAG_SRST | ATA_FLAG_MMIO,
257 .pio_mask = 0x03, /* pio3-4 */
258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
259 .port_ops = &pdc_sata_ops,
264 .sht = &pdc_sata_sht,
265 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
266 ATA_FLAG_SRST | ATA_FLAG_MMIO |
268 .pio_mask = 0x03, /* pio3-4 */
269 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
270 .port_ops = &pdc_20621_ops,
275 static struct pci_device_id pdc_sata_pci_tbl[] = {
276 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 { } /* terminate list */
294 static struct pci_driver pdc_sata_pci_driver = {
296 .id_table = pdc_sata_pci_tbl,
297 .probe = pdc_sata_init_one,
298 .remove = ata_pci_remove_one,
302 static void pdc20621_host_stop(struct ata_host_set *host_set)
304 struct pdc_host_priv *hpriv = host_set->private_data;
305 void *dimm_mmio = hpriv->dimm_mmio;
311 static int pdc_port_start(struct ata_port *ap)
313 struct pci_dev *pdev = ap->host_set->pdev;
314 struct pdc_port_priv *pp;
317 rc = ata_port_start(ap);
321 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
326 memset(pp, 0, sizeof(*pp));
328 pp->pkt = pci_alloc_consistent(pdev, 128, &pp->pkt_dma);
334 ap->private_data = pp;
346 static void pdc_port_stop(struct ata_port *ap)
348 struct pci_dev *pdev = ap->host_set->pdev;
349 struct pdc_port_priv *pp = ap->private_data;
351 ap->private_data = NULL;
352 pci_free_consistent(pdev, 128, pp->pkt, pp->pkt_dma);
358 static void pdc_20621_phy_reset (struct ata_port *ap)
361 ap->cbl = ATA_CBL_SATA;
366 static void pdc_reset_port(struct ata_port *ap)
368 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
372 for (i = 11; i > 0; i--) {
385 readl(mmio); /* flush */
388 static void pdc_phy_reset(struct ata_port *ap)
394 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
396 if (sc_reg > SCR_CONTROL)
398 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
402 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
405 if (sc_reg > SCR_CONTROL)
407 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
410 enum pdc_packet_bits {
411 PDC_PKT_READ = (1 << 2),
412 PDC_PKT_NODATA = (1 << 3),
414 PDC_PKT_SIZEMASK = (1 << 7) | (1 << 6) | (1 << 5),
415 PDC_PKT_CLEAR_BSY = (1 << 4),
416 PDC_PKT_WAIT_DRDY = (1 << 3) | (1 << 4),
417 PDC_LAST_REG = (1 << 3),
419 PDC_REG_DEVCTL = (1 << 3) | (1 << 2) | (1 << 1),
422 static inline unsigned int pdc_pkt_header(struct ata_taskfile *tf,
424 unsigned int devno, u8 *buf)
427 u32 *buf32 = (u32 *) buf;
429 /* set control bits (byte 0), zero delay seq id (byte 3),
430 * and seq id (byte 2)
432 switch (tf->protocol) {
434 if (!(tf->flags & ATA_TFLAG_WRITE))
435 buf32[0] = cpu_to_le32(PDC_PKT_READ);
440 case ATA_PROT_NODATA:
441 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
449 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
450 buf32[2] = 0; /* no next-packet */
453 dev_reg = ATA_DEVICE_OBS;
455 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
458 buf[12] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
461 /* device control register */
462 buf[14] = (1 << 5) | PDC_REG_DEVCTL;
465 return 16; /* offset of next byte */
468 static inline unsigned int pdc_pkt_footer(struct ata_taskfile *tf, u8 *buf,
471 if (tf->flags & ATA_TFLAG_DEVICE) {
472 buf[i++] = (1 << 5) | ATA_REG_DEVICE;
473 buf[i++] = tf->device;
476 /* and finally the command itself; also includes end-of-pkt marker */
477 buf[i++] = (1 << 5) | PDC_LAST_REG | ATA_REG_CMD;
478 buf[i++] = tf->command;
483 static inline unsigned int pdc_prep_lba28(struct ata_taskfile *tf, u8 *buf, unsigned int i)
485 /* the "(1 << 5)" should be read "(count << 5)" */
487 /* ATA command block registers */
488 buf[i++] = (1 << 5) | ATA_REG_FEATURE;
489 buf[i++] = tf->feature;
491 buf[i++] = (1 << 5) | ATA_REG_NSECT;
492 buf[i++] = tf->nsect;
494 buf[i++] = (1 << 5) | ATA_REG_LBAL;
497 buf[i++] = (1 << 5) | ATA_REG_LBAM;
500 buf[i++] = (1 << 5) | ATA_REG_LBAH;
506 static inline unsigned int pdc_prep_lba48(struct ata_taskfile *tf, u8 *buf, unsigned int i)
508 /* the "(2 << 5)" should be read "(count << 5)" */
510 /* ATA command block registers */
511 buf[i++] = (2 << 5) | ATA_REG_FEATURE;
512 buf[i++] = tf->hob_feature;
513 buf[i++] = tf->feature;
515 buf[i++] = (2 << 5) | ATA_REG_NSECT;
516 buf[i++] = tf->hob_nsect;
517 buf[i++] = tf->nsect;
519 buf[i++] = (2 << 5) | ATA_REG_LBAL;
520 buf[i++] = tf->hob_lbal;
523 buf[i++] = (2 << 5) | ATA_REG_LBAM;
524 buf[i++] = tf->hob_lbam;
527 buf[i++] = (2 << 5) | ATA_REG_LBAH;
528 buf[i++] = tf->hob_lbah;
534 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
536 unsigned int total_len)
539 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
540 u32 *buf32 = (u32 *) buf;
542 /* output ATA packet S/G table */
543 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
544 (PDC_DIMM_DATA_STEP * portno);
545 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
546 buf32[dw] = cpu_to_le32(addr);
547 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
549 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
550 PDC_20621_DIMM_BASE +
551 (PDC_DIMM_WINDOW_STEP * portno) +
553 buf32[dw], buf32[dw + 1]);
556 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
558 unsigned int total_len)
561 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
562 u32 *buf32 = (u32 *) buf;
564 /* output Host DMA packet S/G table */
565 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
566 (PDC_DIMM_DATA_STEP * portno);
568 buf32[dw] = cpu_to_le32(addr);
569 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
571 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
572 PDC_20621_DIMM_BASE +
573 (PDC_DIMM_WINDOW_STEP * portno) +
575 buf32[dw], buf32[dw + 1]);
578 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
579 unsigned int devno, u8 *buf,
583 u32 *buf32 = (u32 *) buf;
586 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
587 (PDC_DIMM_WINDOW_STEP * portno) +
589 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
591 i = PDC_DIMM_ATA_PKT;
596 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
597 buf[i++] = PDC_PKT_READ;
598 else if (tf->protocol == ATA_PROT_NODATA)
599 buf[i++] = PDC_PKT_NODATA;
602 buf[i++] = 0; /* reserved */
603 buf[i++] = portno + 1; /* seq. id */
604 buf[i++] = 0xff; /* delay seq. id */
606 /* dimm dma S/G, and next-pkt */
608 buf32[dw] = cpu_to_le32(dimm_sg);
613 dev_reg = ATA_DEVICE_OBS;
615 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
618 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
621 /* device control register */
622 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
628 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
632 u32 tmp, *buf32 = (u32 *) buf;
634 unsigned int host_sg = PDC_20621_DIMM_BASE +
635 (PDC_DIMM_WINDOW_STEP * portno) +
637 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
638 (PDC_DIMM_WINDOW_STEP * portno) +
640 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
641 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
643 dw = PDC_DIMM_HOST_PKT >> 2;
646 * Set up Host DMA packet
648 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
652 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
653 tmp |= (0xff << 24); /* delay seq. id */
654 buf32[dw + 0] = cpu_to_le32(tmp);
655 buf32[dw + 1] = cpu_to_le32(host_sg);
656 buf32[dw + 2] = cpu_to_le32(dimm_sg);
659 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
660 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
668 static void pdc20621_fill_sg(struct ata_queued_cmd *qc)
670 struct scatterlist *sg = qc->sg;
671 struct ata_port *ap = qc->ap;
672 struct pdc_port_priv *pp = ap->private_data;
673 void *mmio = ap->host_set->mmio_base;
674 struct pdc_host_priv *hpriv = ap->host_set->private_data;
675 void *dimm_mmio = hpriv->dimm_mmio;
676 unsigned int portno = ap->port_no;
677 unsigned int i, last, idx, total_len = 0, sgt_len;
678 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
680 VPRINTK("ata%u: ENTER\n", ap->id);
682 /* hard-code chip #0 */
683 mmio += PDC_CHIP0_OFS;
690 for (i = 0; i < last; i++) {
691 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
692 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
693 total_len += sg[i].length;
695 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
699 * Build ATA, host DMA packets
701 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
702 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
704 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
705 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
707 if (qc->tf.flags & ATA_TFLAG_LBA48)
708 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
710 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
712 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
714 /* copy three S/G tables and two packets to DIMM MMIO window */
715 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
716 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
717 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
719 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
721 /* force host FIFO dump */
722 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
724 readl(dimm_mmio); /* MMIO PCI posting flush */
726 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
729 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
733 struct ata_port *ap = qc->ap;
734 struct ata_host_set *host_set = ap->host_set;
735 void *mmio = host_set->mmio_base;
737 /* hard-code chip #0 */
738 mmio += PDC_CHIP0_OFS;
740 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
741 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
743 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
744 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
747 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
751 struct ata_port *ap = qc->ap;
752 struct pdc_host_priv *pp = ap->host_set->private_data;
753 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
755 if (!pp->doing_hdma) {
756 __pdc20621_push_hdma(qc, seq, pkt_ofs);
761 pp->hdma[idx].qc = qc;
762 pp->hdma[idx].seq = seq;
763 pp->hdma[idx].pkt_ofs = pkt_ofs;
767 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
769 struct ata_port *ap = qc->ap;
770 struct pdc_host_priv *pp = ap->host_set->private_data;
771 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
773 /* if nothing on queue, we're done */
774 if (pp->hdma_prod == pp->hdma_cons) {
779 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
780 pp->hdma[idx].pkt_ofs);
784 #ifdef ATA_VERBOSE_DEBUG
785 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
787 struct ata_port *ap = qc->ap;
788 unsigned int port_no = ap->port_no;
789 struct pdc_host_priv *hpriv = ap->host_set->private_data;
790 void *dimm_mmio = hpriv->dimm_mmio;
792 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
793 dimm_mmio += PDC_DIMM_HOST_PKT;
795 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
796 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
797 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
798 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
801 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
802 #endif /* ATA_VERBOSE_DEBUG */
804 static void pdc20621_dma_start(struct ata_queued_cmd *qc)
806 struct ata_port *ap = qc->ap;
807 struct ata_host_set *host_set = ap->host_set;
808 unsigned int port_no = ap->port_no;
809 void *mmio = host_set->mmio_base;
810 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
811 u8 seq = (u8) (port_no + 1);
812 unsigned int doing_hdma = 0, port_ofs;
814 /* hard-code chip #0 */
815 mmio += PDC_CHIP0_OFS;
817 VPRINTK("ata%u: ENTER\n", ap->id);
819 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
821 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
827 wmb(); /* flush PRD, pkt writes */
830 pdc20621_dump_hdma(qc);
831 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
832 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
833 port_ofs + PDC_DIMM_HOST_PKT,
834 port_ofs + PDC_DIMM_HOST_PKT,
837 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
838 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
840 writel(port_ofs + PDC_DIMM_ATA_PKT,
841 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
842 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
843 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
844 port_ofs + PDC_DIMM_ATA_PKT,
845 port_ofs + PDC_DIMM_ATA_PKT,
850 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
851 struct ata_queued_cmd *qc,
852 unsigned int doing_hdma,
855 unsigned int port_no = ap->port_no;
856 unsigned int port_ofs =
857 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
859 unsigned int handled = 0;
863 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
864 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
866 /* step two - DMA from DIMM to host */
868 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
869 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
870 pdc_dma_complete(ap, qc, 0);
871 pdc20621_pop_hdma(qc);
874 /* step one - exec ATA command */
876 u8 seq = (u8) (port_no + 1 + 4);
877 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
878 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
880 /* submit hdma pkt */
881 pdc20621_dump_hdma(qc);
882 pdc20621_push_hdma(qc, seq,
883 port_ofs + PDC_DIMM_HOST_PKT);
887 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
889 /* step one - DMA from host to DIMM */
891 u8 seq = (u8) (port_no + 1);
892 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
893 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
896 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
897 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
898 writel(port_ofs + PDC_DIMM_ATA_PKT,
899 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
900 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
903 /* step two - execute ATA command */
905 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
906 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
907 pdc_dma_complete(ap, qc, 0);
908 pdc20621_pop_hdma(qc);
912 /* command completion, but no data xfer */
913 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
915 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
916 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
917 ata_qc_complete(qc, status, 0);
921 ap->stats.idle_irq++;
927 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
929 struct ata_host_set *host_set = dev_instance;
932 unsigned int i, tmp, port_no;
933 unsigned int handled = 0;
938 if (!host_set || !host_set->mmio_base) {
939 VPRINTK("QUICK EXIT\n");
943 mmio_base = host_set->mmio_base;
945 /* reading should also clear interrupts */
946 mmio_base += PDC_CHIP0_OFS;
947 mask = readl(mmio_base + PDC_20621_SEQMASK);
948 VPRINTK("mask == 0x%x\n", mask);
950 if (mask == 0xffffffff) {
951 VPRINTK("QUICK EXIT 2\n");
954 mask &= 0xffff; /* only 16 tags possible */
956 VPRINTK("QUICK EXIT 3\n");
960 spin_lock(&host_set->lock);
962 for (i = 1; i < 9; i++) {
966 if (port_no >= host_set->n_ports)
969 ap = host_set->ports[port_no];
970 tmp = mask & (1 << i);
971 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
972 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
973 struct ata_queued_cmd *qc;
975 qc = ata_qc_from_tag(ap, ap->active_tag);
976 if (qc && ((qc->flags & ATA_QCFLAG_POLL) == 0))
977 handled += pdc20621_host_intr(ap, qc, (i > 4),
982 spin_unlock(&host_set->lock);
984 VPRINTK("mask == 0x%x\n", mask);
988 return IRQ_RETVAL(handled);
991 static void pdc_fill_sg(struct ata_queued_cmd *qc)
993 struct pdc_port_priv *pp = qc->ap->private_data;
1000 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, qc->dev->devno, pp->pkt);
1002 if (qc->tf.flags & ATA_TFLAG_LBA48)
1003 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
1005 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
1007 pdc_pkt_footer(&qc->tf, pp->pkt, i);
1010 static inline void pdc_dma_complete (struct ata_port *ap,
1011 struct ata_queued_cmd *qc,
1014 u8 err_bit = have_err ? ATA_ERR : 0;
1016 /* get drive status; clear intr; complete txn */
1017 ata_qc_complete(ata_qc_from_tag(ap, ap->active_tag),
1018 ata_wait_idle(ap) | err_bit, 0);
1021 static void pdc_eng_timeout(struct ata_port *ap)
1024 struct ata_queued_cmd *qc;
1028 qc = ata_qc_from_tag(ap, ap->active_tag);
1030 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1035 /* hack alert! We cannot use the supplied completion
1036 * function from inside the ->eh_strategy_handler() thread.
1037 * libata is the only user of ->eh_strategy_handler() in
1038 * any kernel, so the default scsi_done() assumes it is
1039 * not being called from the SCSI EH.
1041 qc->scsidone = scsi_finish_command;
1043 switch (qc->tf.protocol) {
1045 printk(KERN_ERR "ata%u: DMA timeout\n", ap->id);
1046 ata_qc_complete(ata_qc_from_tag(ap, ap->active_tag),
1047 ata_wait_idle(ap) | ATA_ERR, 0);
1050 case ATA_PROT_NODATA:
1051 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
1053 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x\n",
1054 ap->id, qc->tf.command, drv_stat);
1056 ata_qc_complete(qc, drv_stat, 1);
1060 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
1062 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
1063 ap->id, qc->tf.command, drv_stat);
1065 ata_qc_complete(qc, drv_stat, 1);
1073 static inline unsigned int pdc_host_intr( struct ata_port *ap,
1074 struct ata_queued_cmd *qc)
1077 unsigned int handled = 0, have_err = 0;
1079 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
1082 if (tmp & PDC_ERR_MASK) {
1087 switch (qc->tf.protocol) {
1089 pdc_dma_complete(ap, qc, have_err);
1093 case ATA_PROT_NODATA: /* command completion, but no data xfer */
1094 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
1095 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
1098 ata_qc_complete(qc, status, 0);
1103 ap->stats.idle_irq++;
1110 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
1112 struct ata_host_set *host_set = dev_instance;
1113 struct ata_port *ap;
1115 unsigned int i, tmp;
1116 unsigned int handled = 0;
1121 if (!host_set || !host_set->mmio_base) {
1122 VPRINTK("QUICK EXIT\n");
1126 mmio_base = host_set->mmio_base;
1128 /* reading should also clear interrupts */
1129 mask = readl(mmio_base + PDC_INT_SEQMASK);
1131 if (mask == 0xffffffff) {
1132 VPRINTK("QUICK EXIT 2\n");
1135 mask &= 0xffff; /* only 16 tags possible */
1137 VPRINTK("QUICK EXIT 3\n");
1141 spin_lock(&host_set->lock);
1143 for (i = 0; i < host_set->n_ports; i++) {
1144 VPRINTK("port %u\n", i);
1145 ap = host_set->ports[i];
1146 tmp = mask & (1 << (i + 1));
1147 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
1148 struct ata_queued_cmd *qc;
1150 qc = ata_qc_from_tag(ap, ap->active_tag);
1151 if (qc && ((qc->flags & ATA_QCFLAG_POLL) == 0))
1152 handled += pdc_host_intr(ap, qc);
1156 spin_unlock(&host_set->lock);
1160 return IRQ_RETVAL(handled);
1163 static void pdc_dma_start(struct ata_queued_cmd *qc)
1165 struct ata_port *ap = qc->ap;
1166 struct pdc_port_priv *pp = ap->private_data;
1167 unsigned int port_no = ap->port_no;
1168 u8 seq = (u8) (port_no + 1);
1170 VPRINTK("ENTER, ap %p\n", ap);
1172 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
1173 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
1176 wmb(); /* flush PRD, pkt writes */
1177 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
1178 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
1181 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
1183 if (tf->protocol == ATA_PROT_PIO)
1184 ata_tf_load_mmio(ap, tf);
1188 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
1190 if (tf->protocol == ATA_PROT_PIO)
1191 ata_exec_command_mmio(ap, tf);
1195 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
1197 port->cmd_addr = base;
1198 port->data_addr = base;
1199 port->feature_addr =
1200 port->error_addr = base + 0x4;
1201 port->nsect_addr = base + 0x8;
1202 port->lbal_addr = base + 0xc;
1203 port->lbam_addr = base + 0x10;
1204 port->lbah_addr = base + 0x14;
1205 port->device_addr = base + 0x18;
1206 port->command_addr =
1207 port->status_addr = base + 0x1c;
1208 port->altstatus_addr =
1209 port->ctl_addr = base + 0x38;
1213 #ifdef ATA_VERBOSE_DEBUG
1214 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
1215 u32 offset, u32 size)
1221 void *mmio = pe->mmio_base;
1222 struct pdc_host_priv *hpriv = pe->private_data;
1223 void *dimm_mmio = hpriv->dimm_mmio;
1225 /* hard-code chip #0 */
1226 mmio += PDC_CHIP0_OFS;
1229 window_size = 0x2000 * 4; /* 32K byte uchar size */
1230 idx = (u16) (offset / window_size);
1232 writel(0x01, mmio + PDC_GENERAL_CTLR);
1233 readl(mmio + PDC_GENERAL_CTLR);
1234 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1235 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1237 offset -= (idx * window_size);
1239 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1240 (long) (window_size - offset);
1241 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1246 for (; (long) size >= (long) window_size ;) {
1247 writel(0x01, mmio + PDC_GENERAL_CTLR);
1248 readl(mmio + PDC_GENERAL_CTLR);
1249 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1250 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1251 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1253 psource += window_size;
1254 size -= window_size;
1259 writel(0x01, mmio + PDC_GENERAL_CTLR);
1260 readl(mmio + PDC_GENERAL_CTLR);
1261 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1262 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1263 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1270 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
1271 u32 offset, u32 size)
1277 void *mmio = pe->mmio_base;
1278 struct pdc_host_priv *hpriv = pe->private_data;
1279 void *dimm_mmio = hpriv->dimm_mmio;
1281 /* hard-code chip #0 */
1282 mmio += PDC_CHIP0_OFS;
1285 window_size = 0x2000 * 4; /* 32K byte uchar size */
1286 idx = (u16) (offset / window_size);
1288 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1289 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1290 offset -= (idx * window_size);
1292 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1293 (long) (window_size - offset);
1294 memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
1295 writel(0x01, mmio + PDC_GENERAL_CTLR);
1296 readl(mmio + PDC_GENERAL_CTLR);
1300 for (; (long) size >= (long) window_size ;) {
1301 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1302 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1303 memcpy_toio((char *) (dimm_mmio), (char *) psource,
1305 writel(0x01, mmio + PDC_GENERAL_CTLR);
1306 readl(mmio + PDC_GENERAL_CTLR);
1307 psource += window_size;
1308 size -= window_size;
1313 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1314 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1315 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
1316 writel(0x01, mmio + PDC_GENERAL_CTLR);
1317 readl(mmio + PDC_GENERAL_CTLR);
1322 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1323 u32 subaddr, u32 *pdata)
1325 void *mmio = pe->mmio_base;
1330 /* hard-code chip #0 */
1331 mmio += PDC_CHIP0_OFS;
1333 i2creg |= device << 24;
1334 i2creg |= subaddr << 16;
1336 /* Set the device and subaddress */
1337 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1338 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1340 /* Write Control to perform read operation, mask int */
1341 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1342 mmio + PDC_I2C_CONTROL_OFFSET);
1344 for (count = 0; count <= 1000; count ++) {
1345 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1346 if (status & PDC_I2C_COMPLETE) {
1347 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1349 } else if (count == 1000)
1353 *pdata = (status >> 8) & 0x000000ff;
1358 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1361 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1362 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1368 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1378 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1384 void *mmio = pe->mmio_base;
1385 static const struct {
1388 } pdc_i2c_read_data [] = {
1389 { PDC_DIMM_SPD_TYPE, 11 },
1390 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1391 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1392 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1393 { PDC_DIMM_SPD_ROW_NUM, 3 },
1394 { PDC_DIMM_SPD_BANK_NUM, 17 },
1395 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1396 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1397 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1398 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1399 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1400 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1403 /* hard-code chip #0 */
1404 mmio += PDC_CHIP0_OFS;
1406 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1407 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1408 pdc_i2c_read_data[i].reg,
1409 &spd0[pdc_i2c_read_data[i].ofs]);
1411 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1412 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1413 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1414 data |= (((((spd0[29] > spd0[28])
1415 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1416 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1418 if (spd0[18] & 0x08)
1419 data |= ((0x03) << 14);
1420 else if (spd0[18] & 0x04)
1421 data |= ((0x02) << 14);
1422 else if (spd0[18] & 0x01)
1423 data |= ((0x01) << 14);
1428 Calculate the size of bDIMMSize (power of 2) and
1429 merge the DIMM size by program start/end address.
1432 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1433 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1434 data |= (((size / 16) - 1) << 16);
1437 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1438 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1443 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1447 void *mmio = pe->mmio_base;
1449 /* hard-code chip #0 */
1450 mmio += PDC_CHIP0_OFS;
1453 Set To Default : DIMM Module Global Control Register (0x022259F1)
1454 DIMM Arbitration Disable (bit 20)
1455 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1456 Refresh Enable (bit 17)
1460 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1461 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1463 /* Turn on for ECC */
1464 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1465 PDC_DIMM_SPD_TYPE, &spd0);
1467 data |= (0x01 << 16);
1468 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1469 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1470 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1473 /* DIMM Initialization Select/Enable (bit 18/19) */
1476 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1479 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1480 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1481 if (!(data & (1<<19))) {
1485 set_current_state(TASK_INTERRUPTIBLE);
1486 schedule_timeout((i * 100) * HZ / 1000);
1492 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1494 int speed, size, length;
1495 u32 addr,spd0,pci_status;
1502 void *mmio = pe->mmio_base;
1504 /* hard-code chip #0 */
1505 mmio += PDC_CHIP0_OFS;
1507 /* Initialize PLL based upon PCI Bus Frequency */
1509 /* Initialize Time Period Register */
1510 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1511 time_period = readl(mmio + PDC_TIME_PERIOD);
1512 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1515 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1516 readl(mmio + PDC_TIME_CONTROL);
1518 /* Wait 3 seconds */
1519 set_current_state(TASK_UNINTERRUPTIBLE);
1520 schedule_timeout(3 * HZ);
1523 When timer is enabled, counter is decreased every internal
1527 tcount = readl(mmio + PDC_TIME_COUNTER);
1528 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1531 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1532 register should be >= (0xffffffff - 3x10^8).
1534 if(tcount >= PCI_X_TCOUNT) {
1535 ticks = (time_period - tcount);
1536 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1538 clock = (ticks / 300000);
1539 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1541 clock = (clock * 33);
1542 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1544 /* PLL F Param (bit 22:16) */
1545 fparam = (1400000 / clock) - 2;
1546 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1548 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1549 pci_status = (0x8a001824 | (fparam << 16));
1551 pci_status = PCI_PLL_INIT;
1553 /* Initialize PLL. */
1554 VPRINTK("pci_status: 0x%x\n", pci_status);
1555 writel(pci_status, mmio + PDC_CTL_STATUS);
1556 readl(mmio + PDC_CTL_STATUS);
1559 Read SPD of DIMM by I2C interface,
1560 and program the DIMM Module Controller.
1562 if (!(speed = pdc20621_detect_dimm(pe))) {
1563 printk(KERN_ERR "Detect Local DIMM Fail\n");
1564 return 1; /* DIMM error */
1566 VPRINTK("Local DIMM Speed = %d\n", speed);
1568 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1569 size = pdc20621_prog_dimm0(pe);
1570 VPRINTK("Local DIMM Size = %dMB\n",size);
1572 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1573 if (pdc20621_prog_dimm_global(pe)) {
1574 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1578 #ifdef ATA_VERBOSE_DEBUG
1580 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1581 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1583 '9','8','0','3','1','6','1','2',0,0};
1584 u8 test_parttern2[40] = {0};
1586 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1587 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1589 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1590 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1591 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1592 test_parttern2[1], &(test_parttern2[2]));
1593 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1595 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1596 test_parttern2[1], &(test_parttern2[2]));
1598 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1599 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1600 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1601 test_parttern2[1], &(test_parttern2[2]));
1605 /* ECC initiliazation. */
1607 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1608 PDC_DIMM_SPD_TYPE, &spd0);
1610 VPRINTK("Start ECC initialization\n");
1612 length = size * 1024 * 1024;
1613 while (addr < length) {
1614 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1616 addr += sizeof(u32);
1618 VPRINTK("Finish ECC initialization\n");
1624 static void pdc_20621_init(struct ata_probe_ent *pe)
1627 void *mmio = pe->mmio_base;
1629 /* hard-code chip #0 */
1630 mmio += PDC_CHIP0_OFS;
1633 * Select page 0x40 for our 32k DIMM window
1635 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1636 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1637 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1642 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1644 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1645 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1649 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1651 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1652 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1655 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
1657 void *mmio = pe->mmio_base;
1660 if (chip_id == board_20621)
1664 * Except for the hotplug stuff, this is voodoo from the
1665 * Promise driver. Label this entire section
1666 * "TODO: figure out why we do this"
1669 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
1670 tmp = readl(mmio + PDC_FLASH_CTL);
1671 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
1672 writel(tmp, mmio + PDC_FLASH_CTL);
1674 /* clear plug/unplug flags for all ports */
1675 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
1676 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
1678 /* mask plug/unplug ints */
1679 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
1680 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
1682 /* reduce TBG clock to 133 Mhz. */
1683 tmp = readl(mmio + PDC_TBG_MODE);
1684 tmp &= ~0x30000; /* clear bit 17, 16*/
1685 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1686 writel(tmp, mmio + PDC_TBG_MODE);
1688 readl(mmio + PDC_TBG_MODE); /* flush */
1689 set_current_state(TASK_UNINTERRUPTIBLE);
1690 schedule_timeout(msecs_to_jiffies(10));
1692 /* adjust slew rate control register. */
1693 tmp = readl(mmio + PDC_SLEW_CTL);
1694 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1695 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1696 writel(tmp, mmio + PDC_SLEW_CTL);
1699 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1701 static int printed_version;
1702 struct ata_probe_ent *probe_ent = NULL;
1704 void *mmio_base, *dimm_mmio = NULL;
1705 struct pdc_host_priv *hpriv = NULL;
1706 unsigned int board_idx = (unsigned int) ent->driver_data;
1707 unsigned int have_20621 = (board_idx == board_20621);
1710 if (!printed_version++)
1711 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1714 * If this driver happens to only be useful on Apple's K2, then
1715 * we should check that here as it has a normal Serverworks ID
1717 rc = pci_enable_device(pdev);
1721 rc = pci_request_regions(pdev, DRV_NAME);
1725 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1727 goto err_out_regions;
1728 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1730 goto err_out_regions;
1732 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1733 if (probe_ent == NULL) {
1735 goto err_out_regions;
1738 memset(probe_ent, 0, sizeof(*probe_ent));
1739 probe_ent->pdev = pdev;
1740 INIT_LIST_HEAD(&probe_ent->node);
1742 mmio_base = ioremap(pci_resource_start(pdev, 3),
1743 pci_resource_len(pdev, 3));
1744 if (mmio_base == NULL) {
1746 goto err_out_free_ent;
1748 base = (unsigned long) mmio_base;
1751 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1754 goto err_out_iounmap;
1756 memset(hpriv, 0, sizeof(*hpriv));
1758 dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1759 pci_resource_len(pdev, 4));
1763 goto err_out_iounmap;
1766 hpriv->dimm_mmio = dimm_mmio;
1769 probe_ent->sht = pdc_port_info[board_idx].sht;
1770 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1771 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1772 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1773 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1775 probe_ent->irq = pdev->irq;
1776 probe_ent->irq_flags = SA_SHIRQ;
1777 probe_ent->mmio_base = mmio_base;
1780 probe_ent->private_data = hpriv;
1781 base += PDC_CHIP0_OFS;
1784 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1785 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1788 probe_ent->port[0].scr_addr = base + 0x400;
1789 probe_ent->port[1].scr_addr = base + 0x500;
1792 /* notice 4-port boards */
1793 switch (board_idx) {
1796 probe_ent->n_ports = 4;
1798 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1799 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1802 probe_ent->port[2].scr_addr = base + 0x600;
1803 probe_ent->port[3].scr_addr = base + 0x700;
1807 probe_ent->n_ports = 2;
1814 pci_set_master(pdev);
1816 /* initialize adapter */
1818 /* initialize local dimm */
1819 if (pdc20621_dimm_init(probe_ent)) {
1821 goto err_out_iounmap_dimm;
1823 pdc_20621_init(probe_ent);
1825 pdc_host_init(board_idx, probe_ent);
1827 /* FIXME: check ata_device_add return value */
1828 ata_device_add(probe_ent);
1833 err_out_iounmap_dimm: /* only get to this label if 20621 */
1841 pci_release_regions(pdev);
1843 pci_disable_device(pdev);
1848 static int __init pdc_sata_init(void)
1850 return pci_module_init(&pdc_sata_pci_driver);
1854 static void __exit pdc_sata_exit(void)
1856 pci_unregister_driver(&pdc_sata_pci_driver);
1860 MODULE_AUTHOR("Jeff Garzik");
1861 MODULE_DESCRIPTION("Promise SATA low-level driver");
1862 MODULE_LICENSE("GPL");
1863 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1865 module_init(pdc_sata_init);
1866 module_exit(pdc_sata_exit);