2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
18 * Other major contributions:
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *-----------------------------------------------------------------------------
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 #include <linux/config.h>
44 #include <linux/delay.h>
45 #include <linux/ioport.h>
46 #include <linux/pci.h>
47 #include <linux/string.h>
48 #include <linux/timer.h>
49 #include <linux/types.h>
56 #include <scsi/scsi.h>
57 #include <scsi/scsi_cmnd.h>
58 #include <scsi/scsi_device.h>
59 #include <scsi/scsi_host.h>
62 #define bzero(d, n) memset((d), 0, (n))
66 * General driver includes.
73 * Configuration addendum for Linux.
75 #define SYM_CONF_TIMER_INTERVAL ((HZ+1)/2)
77 #define SYM_OPT_HANDLE_DIR_UNKNOWN
78 #define SYM_OPT_HANDLE_DEVICE_QUEUEING
79 #define SYM_OPT_LIMIT_COMMAND_REORDERING
80 #define SYM_OPT_ANNOUNCE_TRANSFER_RATE
83 * Print a message with severity.
85 #define printf_emerg(args...) printk(KERN_EMERG args)
86 #define printf_alert(args...) printk(KERN_ALERT args)
87 #define printf_crit(args...) printk(KERN_CRIT args)
88 #define printf_err(args...) printk(KERN_ERR args)
89 #define printf_warning(args...) printk(KERN_WARNING args)
90 #define printf_notice(args...) printk(KERN_NOTICE args)
91 #define printf_info(args...) printk(KERN_INFO args)
92 #define printf_debug(args...) printk(KERN_DEBUG args)
93 #define printf(args...) printk(args)
96 * Insert a delay in micro-seconds
98 #define sym_udelay(us) udelay(us)
101 * A 'read barrier' flushes any data that have been prefetched
102 * by the processor due to out of order execution. Such a barrier
103 * must notably be inserted prior to looking at data that have
104 * been DMAed, assuming that program does memory READs in proper
105 * order and that the device ensured proper ordering of WRITEs.
107 * A 'write barrier' prevents any previous WRITEs to pass further
108 * WRITEs. Such barriers must be inserted each time another agent
109 * relies on ordering of WRITEs.
111 * Note that, due to posting of PCI memory writes, we also must
112 * insert dummy PCI read transactions when some ordering involving
113 * both directions over the PCI does matter. PCI transactions are
114 * fully ordered in each direction.
117 #define MEMORY_READ_BARRIER() rmb()
118 #define MEMORY_WRITE_BARRIER() wmb()
121 * Let the compiler know about driver data structure names.
123 typedef struct sym_tcb *tcb_p;
124 typedef struct sym_lcb *lcb_p;
125 typedef struct sym_ccb *ccb_p;
126 typedef struct sym_hcb *hcb_p;
129 * Define a reference to the O/S dependent IO request.
131 typedef struct scsi_cmnd *cam_ccb_p; /* Generic */
132 typedef struct scsi_cmnd *cam_scsiio_p;/* SCSI I/O */
136 * IO functions definition for big/little endian CPU support.
137 * For now, PCI chips are only supported in little endian addressing mode,
144 #define outw_b2l outw
145 #define outl_b2l outl
146 #define readw_l2b readw
147 #define readl_l2b readl
148 #define writew_b2l writew
149 #define writel_b2l writel
151 #else /* little endian */
155 #define outw_raw outw
156 #define outl_raw outl
158 #define readw_raw readw
159 #define readl_raw readl
160 #define writew_raw writew
161 #define writel_raw writel
165 #ifdef SYM_CONF_CHIP_BIG_ENDIAN
166 #error "Chips in BIG ENDIAN addressing mode are not (yet) supported"
171 * If the chip uses big endian addressing mode over the
172 * PCI, actual io register addresses for byte and word
173 * accesses must be changed according to lane routing.
174 * Btw, sym_offb() and sym_offw() macros only apply to
175 * constants and so donnot generate bloated code.
178 #if defined(SYM_CONF_CHIP_BIG_ENDIAN)
180 #define sym_offb(o) (((o)&~3)+((~((o)&3))&3))
181 #define sym_offw(o) (((o)&~3)+((~((o)&3))&2))
185 #define sym_offb(o) (o)
186 #define sym_offw(o) (o)
191 * If the CPU and the chip use same endian-ness addressing,
192 * no byte reordering is needed for script patching.
193 * Macro cpu_to_scr() is to be used for script patching.
194 * Macro scr_to_cpu() is to be used for getting a DWORD
198 #if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
200 #define cpu_to_scr(dw) cpu_to_le32(dw)
201 #define scr_to_cpu(dw) le32_to_cpu(dw)
203 #elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
205 #define cpu_to_scr(dw) cpu_to_be32(dw)
206 #define scr_to_cpu(dw) be32_to_cpu(dw)
210 #define cpu_to_scr(dw) (dw)
211 #define scr_to_cpu(dw) (dw)
216 * Access to the controller chip.
218 * If SYM_CONF_IOMAPPED is defined, the driver will use
219 * normal IOs instead of the MEMORY MAPPED IO method
220 * recommended by PCI specifications.
221 * If all PCI bridges, host brigdes and architectures
222 * would have been correctly designed for PCI, this
223 * option would be useless.
225 * If the CPU and the chip use same endian-ness addressing,
226 * no byte reordering is needed for accessing chip io
227 * registers. Functions suffixed by '_raw' are assumed
228 * to access the chip over the PCI without doing byte
229 * reordering. Functions suffixed by '_l2b' are
230 * assumed to perform little-endian to big-endian byte
231 * reordering, those suffixed by '_b2l' blah, blah,
235 #if defined(SYM_CONF_IOMAPPED)
238 * IO mapped only input / ouput
241 #define INB_OFF(o) inb (np->s.io_port + sym_offb(o))
242 #define OUTB_OFF(o, val) outb ((val), np->s.io_port + sym_offb(o))
244 #if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
246 #define INW_OFF(o) inw_l2b (np->s.io_port + sym_offw(o))
247 #define INL_OFF(o) inl_l2b (np->s.io_port + (o))
249 #define OUTW_OFF(o, val) outw_b2l ((val), np->s.io_port + sym_offw(o))
250 #define OUTL_OFF(o, val) outl_b2l ((val), np->s.io_port + (o))
252 #elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
254 #define INW_OFF(o) inw_b2l (np->s.io_port + sym_offw(o))
255 #define INL_OFF(o) inl_b2l (np->s.io_port + (o))
257 #define OUTW_OFF(o, val) outw_l2b ((val), np->s.io_port + sym_offw(o))
258 #define OUTL_OFF(o, val) outl_l2b ((val), np->s.io_port + (o))
262 #define INW_OFF(o) inw_raw (np->s.io_port + sym_offw(o))
263 #define INL_OFF(o) inl_raw (np->s.io_port + (o))
265 #define OUTW_OFF(o, val) outw_raw ((val), np->s.io_port + sym_offw(o))
266 #define OUTL_OFF(o, val) outl_raw ((val), np->s.io_port + (o))
270 #else /* defined SYM_CONF_IOMAPPED */
273 * MEMORY mapped IO input / output
276 #define INB_OFF(o) readb(np->s.mmio_va + sym_offb(o))
277 #define OUTB_OFF(o, val) writeb((val), np->s.mmio_va + sym_offb(o))
279 #if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
281 #define INW_OFF(o) readw_l2b(np->s.mmio_va + sym_offw(o))
282 #define INL_OFF(o) readl_l2b(np->s.mmio_va + (o))
284 #define OUTW_OFF(o, val) writew_b2l((val), np->s.mmio_va + sym_offw(o))
285 #define OUTL_OFF(o, val) writel_b2l((val), np->s.mmio_va + (o))
287 #elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
289 #define INW_OFF(o) readw_b2l(np->s.mmio_va + sym_offw(o))
290 #define INL_OFF(o) readl_b2l(np->s.mmio_va + (o))
292 #define OUTW_OFF(o, val) writew_l2b((val), np->s.mmio_va + sym_offw(o))
293 #define OUTL_OFF(o, val) writel_l2b((val), np->s.mmio_va + (o))
297 #define INW_OFF(o) readw_raw(np->s.mmio_va + sym_offw(o))
298 #define INL_OFF(o) readl_raw(np->s.mmio_va + (o))
300 #define OUTW_OFF(o, val) writew_raw((val), np->s.mmio_va + sym_offw(o))
301 #define OUTL_OFF(o, val) writel_raw((val), np->s.mmio_va + (o))
305 #endif /* defined SYM_CONF_IOMAPPED */
307 #define OUTRAM_OFF(o, a, l) memcpy_toio(np->s.ram_va + (o), (a), (l))
310 * Remap some status field values.
312 #define CAM_REQ_CMP DID_OK
313 #define CAM_SEL_TIMEOUT DID_NO_CONNECT
314 #define CAM_CMD_TIMEOUT DID_TIME_OUT
315 #define CAM_REQ_ABORTED DID_ABORT
316 #define CAM_UNCOR_PARITY DID_PARITY
317 #define CAM_SCSI_BUS_RESET DID_RESET
318 #define CAM_REQUEUE_REQ DID_SOFT_ERROR
319 #define CAM_UNEXP_BUSFREE DID_ERROR
320 #define CAM_SCSI_BUSY DID_BUS_BUSY
322 #define CAM_DEV_NOT_THERE DID_NO_CONNECT
323 #define CAM_REQ_INVALID DID_ERROR
324 #define CAM_REQ_TOO_BIG DID_ERROR
326 #define CAM_RESRC_UNAVAIL DID_ERROR
329 * Remap data direction values.
331 #define CAM_DIR_NONE DMA_NONE
332 #define CAM_DIR_IN DMA_FROM_DEVICE
333 #define CAM_DIR_OUT DMA_TO_DEVICE
334 #define CAM_DIR_UNKNOWN DMA_BIDIRECTIONAL
337 * These ones are used as return code from
338 * error recovery handlers under Linux.
340 #define SCSI_SUCCESS SUCCESS
341 #define SCSI_FAILED FAILED
344 * System specific target data structure.
345 * None for now, under Linux.
347 /* #define SYM_HAVE_STCB */
350 * System specific lun data structure.
352 #define SYM_HAVE_SLCB
354 u_short reqtags; /* Number of tags requested by user */
355 u_short scdev_depth; /* Queue depth set in select_queue_depth() */
359 * System specific command data structure.
360 * Not needed under Linux.
362 /* struct sym_sccb */
365 * System specific host data structure.
369 * Chip and controller indentification.
374 struct pci_dev *device;
376 struct Scsi_Host *host;
378 void __iomem * mmio_va; /* MMIO kernel virtual address */
379 void __iomem * ram_va; /* RAM kernel virtual address */
380 u_long io_port; /* IO port address cookie */
381 u_short io_ws; /* IO window size */
382 int irq; /* IRQ number */
384 struct timer_list timer; /* Timer handler link header */
386 u_long settle_time; /* Resetting the SCSI BUS */
387 u_char settle_time_valid;
391 * Return the name of the controller.
393 #define sym_name(np) (np)->s.inst_name
396 * Data structure used as input for the NVRAM reading.
397 * Must resolve the IO macros and sym_name(), when
398 * used as sub-field 's' of another structure.
406 /* port and address fields to fit INB, OUTB macros */
408 void __iomem * mmio_va;
415 struct pci_dev *pdev;
417 struct sym_pci_chip chip;
418 struct sym_nvram *nvram;
424 * Driver host data structure.
431 * The driver definitions (sym_hipd.h) must know about a
432 * couple of things related to the memory allocator.
434 typedef u_long m_addr_t; /* Enough bits to represent any address */
435 #define SYM_MEM_PAGE_ORDER 0 /* 1 PAGE maximum */
436 #define SYM_MEM_CLUSTER_SHIFT (PAGE_SHIFT+SYM_MEM_PAGE_ORDER)
438 #define SYM_MEM_FREE_UNUSED /* Free unused pages immediately */
440 typedef struct pci_dev *m_pool_ident_t;
443 * Include driver soft definitions.
446 #include "sym_hipd.h"
449 * Memory allocator related stuff.
452 #define SYM_MEM_GFP_FLAGS GFP_ATOMIC
453 #define SYM_MEM_WARN 1 /* Warn on failed operations */
455 #define sym_get_mem_cluster() \
456 __get_free_pages(SYM_MEM_GFP_FLAGS, SYM_MEM_PAGE_ORDER)
457 #define sym_free_mem_cluster(p) \
458 free_pages(p, SYM_MEM_PAGE_ORDER)
460 void *sym_calloc(int size, char *name);
461 void sym_mfree(void *m, int size, char *name);
464 * We have to provide the driver memory allocator with methods for
465 * it to maintain virtual to bus physical address translations.
468 #define sym_m_pool_match(mp_id1, mp_id2) (mp_id1 == mp_id2)
470 static __inline m_addr_t sym_m_get_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp)
473 dma_addr_t baddr = 0;
475 vaddr = pci_alloc_consistent(mp->dev_dmat,SYM_MEM_CLUSTER_SIZE, &baddr);
477 vbp->vaddr = (m_addr_t) vaddr;
478 vbp->baddr = (m_addr_t) baddr;
480 return (m_addr_t) vaddr;
483 static __inline void sym_m_free_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp)
485 pci_free_consistent(mp->dev_dmat, SYM_MEM_CLUSTER_SIZE,
486 (void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
489 #define sym_m_create_dma_mem_tag(mp) (0)
490 #define sym_m_delete_dma_mem_tag(mp) do { ; } while (0)
492 void *__sym_calloc_dma(m_pool_ident_t dev_dmat, int size, char *name);
493 void __sym_mfree_dma(m_pool_ident_t dev_dmat, void *m, int size, char *name);
494 m_addr_t __vtobus(m_pool_ident_t dev_dmat, void *m);
497 * Set the status field of a CAM CCB.
500 sym_set_cam_status(struct scsi_cmnd *ccb, int status)
502 ccb->result &= ~(0xff << 16);
503 ccb->result |= (status << 16);
507 * Get the status field of a CAM CCB.
510 sym_get_cam_status(struct scsi_cmnd *ccb)
512 return ((ccb->result >> 16) & 0xff);
516 * The dma mapping is mostly handled by the
517 * SCSI layer and the driver glue under Linux.
519 #define sym_data_dmamap_create(np, cp) (0)
520 #define sym_data_dmamap_destroy(np, cp) do { ; } while (0)
521 #define sym_data_dmamap_unload(np, cp) do { ; } while (0)
522 #define sym_data_dmamap_presync(np, cp) do { ; } while (0)
523 #define sym_data_dmamap_postsync(np, cp) do { ; } while (0)
526 * Async handler for negotiations.
528 void sym_xpt_async_nego_wide(hcb_p np, int target);
529 #define sym_xpt_async_nego_sync(np, target) \
530 sym_announce_transfer_rate(np, target)
531 #define sym_xpt_async_nego_ppr(np, target) \
532 sym_announce_transfer_rate(np, target)
535 * Build CAM result for a successful IO and for a failed IO.
537 static __inline void sym_set_cam_result_ok(hcb_p np, ccb_p cp, int resid)
539 struct scsi_cmnd *cmd = cp->cam_ccb;
542 cmd->result = (((DID_OK) << 16) + ((cp->ssss_status) & 0x7f));
544 void sym_set_cam_result_error(hcb_p np, ccb_p cp, int resid);
547 * Other O/S specific methods.
549 #define sym_cam_target_id(ccb) (ccb)->target
550 #define sym_cam_target_lun(ccb) (ccb)->lun
551 #define sym_freeze_cam_ccb(ccb) do { ; } while (0)
552 void sym_xpt_done(hcb_p np, cam_ccb_p ccb);
553 void sym_xpt_done2(hcb_p np, cam_ccb_p ccb, int cam_status);
554 void sym_print_addr (ccb_p cp);
555 void sym_xpt_async_bus_reset(hcb_p np);
556 void sym_xpt_async_sent_bdr(hcb_p np, int target);
557 int sym_setup_data_and_start (hcb_p np, cam_scsiio_p csio, ccb_p cp);
558 void sym_log_bus_error(hcb_p np);
559 void sym_sniff_inquiry(hcb_p np, struct scsi_cmnd *cmd, int resid);
561 #endif /* SYM_GLUE_H */