2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
24 /* statistics can be kept for for tuning/monitoring */
29 unsigned long reclaim;
30 unsigned long lost_iaa;
32 /* termination of urbs from core */
33 unsigned long complete;
37 /* ehci_hcd->lock guards shared data against other CPUs:
38 * ehci_hcd: async, reclaim, periodic (and shadow), ...
40 * ehci_qh: qh_next, qtd_list
43 * Also, hold this lock when talking to HC registers or
44 * when updating hw_* fields in shared qh/qtd/... structures.
47 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
49 struct ehci_hcd { /* one per controller */
52 /* async schedule support */
53 struct ehci_qh *async;
54 struct ehci_qh *reclaim;
55 int reclaim_ready : 1;
57 /* periodic schedule support */
58 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
59 unsigned periodic_size;
60 u32 *periodic; /* hw periodic table */
61 dma_addr_t periodic_dma;
62 unsigned i_thresh; /* uframes HC might cache */
64 union ehci_shadow *pshadow; /* mirror hw periodic table */
65 int next_uframe; /* scan periodic, start here */
66 unsigned periodic_sched; /* periodic activity count */
68 /* per root hub port */
69 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
71 /* glue to PCI and HCD framework */
73 struct ehci_caps *caps;
74 struct ehci_regs *regs;
75 u32 hcs_params; /* cached register copy */
77 /* per-HC memory pools (could be per-bus, but ...) */
78 struct dma_pool *qh_pool; /* qh per active urb */
79 struct dma_pool *qtd_pool; /* one or more per qh */
80 struct dma_pool *itd_pool; /* itd per iso urb */
81 struct dma_pool *sitd_pool; /* sitd per split iso urb */
83 struct timer_list watchdog;
84 struct notifier_block reboot_notifier;
85 unsigned long actions;
88 unsigned is_arc_rh_tt:1; /* ARC roothub with TT */
92 struct ehci_stats stats;
93 # define COUNT(x) do { (x)++; } while (0)
95 # define COUNT(x) do {} while (0)
99 /* unwrap an HCD pointer to get an EHCI_HCD pointer */
100 #define hcd_to_ehci(hcd_ptr) container_of(hcd_ptr, struct ehci_hcd, hcd)
102 /* NOTE: urb->transfer_flags expected to not use this bit !!! */
103 #define EHCI_STATE_UNLINK 0x8000 /* urb being unlinked */
105 enum ehci_timer_action {
113 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
115 clear_bit (action, &ehci->actions);
119 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
121 if (!test_and_set_bit (action, &ehci->actions)) {
125 case TIMER_IAA_WATCHDOG:
126 t = EHCI_IAA_JIFFIES;
128 case TIMER_IO_WATCHDOG:
131 case TIMER_ASYNC_OFF:
132 t = EHCI_ASYNC_JIFFIES;
134 // case TIMER_ASYNC_SHRINK:
136 t = EHCI_SHRINK_JIFFIES;
140 // all timings except IAA watchdog can be overridden.
141 // async queue SHRINK often precedes IAA. while it's ready
142 // to go OFF neither can matter, and afterwards the IO
143 // watchdog stops unless there's still periodic traffic.
144 if (action != TIMER_IAA_WATCHDOG
145 && t > ehci->watchdog.expires
146 && timer_pending (&ehci->watchdog))
148 mod_timer (&ehci->watchdog, t);
152 /*-------------------------------------------------------------------------*/
154 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
156 /* Section 2.2 Host Controller Capability Registers */
158 /* these fields are specified as 8 and 16 bit registers,
159 * but some hosts can't perform 8 or 16 bit PCI accesses.
162 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
163 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
164 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
165 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
166 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
167 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
168 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
169 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
170 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
171 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
173 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
174 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
175 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
176 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
177 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
178 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
179 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
180 u8 portroute [8]; /* nibbles for routing - offset 0xC */
181 } __attribute__ ((packed));
184 /* Section 2.3 Host Controller Operational Registers */
187 /* USBCMD: offset 0x00 */
189 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
190 #define CMD_PARK (1<<11) /* enable "park" on async qh */
191 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
192 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
193 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
194 #define CMD_ASE (1<<5) /* async schedule enable */
195 #define CMD_PSE (1<<4) /* periodic schedule enable */
196 /* 3:2 is periodic frame list size */
197 #define CMD_RESET (1<<1) /* reset HC not bus */
198 #define CMD_RUN (1<<0) /* start/stop HC */
200 /* USBSTS: offset 0x04 */
202 #define STS_ASS (1<<15) /* Async Schedule Status */
203 #define STS_PSS (1<<14) /* Periodic Schedule Status */
204 #define STS_RECL (1<<13) /* Reclamation */
205 #define STS_HALT (1<<12) /* Not running (any reason) */
206 /* some bits reserved */
207 /* these STS_* flags are also intr_enable bits (USBINTR) */
208 #define STS_IAA (1<<5) /* Interrupted on async advance */
209 #define STS_FATAL (1<<4) /* such as some PCI access errors */
210 #define STS_FLR (1<<3) /* frame list rolled over */
211 #define STS_PCD (1<<2) /* port change detect */
212 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
213 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
215 /* USBINTR: offset 0x08 */
218 /* FRINDEX: offset 0x0C */
219 u32 frame_index; /* current microframe number */
220 /* CTRLDSSEGMENT: offset 0x10 */
221 u32 segment; /* address bits 63:32 if needed */
222 /* PERIODICLISTBASE: offset 0x14 */
223 u32 frame_list; /* points to periodic list */
224 /* ASYNCICLISTADDR: offset 0x18 */
225 u32 async_next; /* address of next async queue head */
229 /* CONFIGFLAG: offset 0x40 */
231 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
233 /* PORTSC: offset 0x44 */
234 u32 port_status [0]; /* up to N_PORTS */
236 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
237 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
238 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
239 /* 19:16 for port testing */
240 /* 15:14 for using port indicator leds (if HCS_INDICATOR allows) */
241 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
242 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
243 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
244 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
246 #define PORT_RESET (1<<8) /* reset port */
247 #define PORT_SUSPEND (1<<7) /* suspend port */
248 #define PORT_RESUME (1<<6) /* resume it */
249 #define PORT_OCC (1<<5) /* over current change */
250 #define PORT_OC (1<<4) /* over current active */
251 #define PORT_PEC (1<<3) /* port enable change */
252 #define PORT_PE (1<<2) /* port enable */
253 #define PORT_CSC (1<<1) /* connect status change */
254 #define PORT_CONNECT (1<<0) /* device connected */
255 } __attribute__ ((packed));
258 /*-------------------------------------------------------------------------*/
260 #define QTD_NEXT(dma) cpu_to_le32((u32)dma)
263 * EHCI Specification 0.95 Section 3.5
264 * QTD: describe data transfer components (buffer, direction, ...)
265 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
267 * These are associated only with "QH" (Queue Head) structures,
268 * used with control, bulk, and interrupt transfers.
271 /* first part defined by EHCI spec */
272 u32 hw_next; /* see EHCI 3.5.1 */
273 u32 hw_alt_next; /* see EHCI 3.5.2 */
274 u32 hw_token; /* see EHCI 3.5.3 */
275 #define QTD_TOGGLE (1 << 31) /* data toggle */
276 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
277 #define QTD_IOC (1 << 15) /* interrupt on complete */
278 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
279 #define QTD_PID(tok) (((tok)>>8) & 0x3)
280 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
281 #define QTD_STS_HALT (1 << 6) /* halted on error */
282 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
283 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
284 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
285 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
286 #define QTD_STS_STS (1 << 1) /* split transaction state */
287 #define QTD_STS_PING (1 << 0) /* issue PING? */
288 u32 hw_buf [5]; /* see EHCI 3.5.4 */
289 u32 hw_buf_hi [5]; /* Appendix B */
291 /* the rest is HCD-private */
292 dma_addr_t qtd_dma; /* qtd address */
293 struct list_head qtd_list; /* sw qtd list */
294 struct urb *urb; /* qtd's urb */
295 size_t length; /* length of buffer */
296 } __attribute__ ((aligned (32)));
298 /* mask NakCnt+T in qh->hw_alt_next */
299 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
301 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
303 /*-------------------------------------------------------------------------*/
305 /* type tag from {qh,itd,sitd,fstn}->hw_next */
306 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
308 /* values for that type tag */
309 #define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1)
310 #define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1)
311 #define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1)
312 #define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1)
314 /* next async queue entry, or pointer to interrupt/periodic QH */
315 #define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
317 /* for periodic/async schedules and qtd lists, mark end of list */
318 #define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */
321 * Entries in periodic shadow table are pointers to one of four kinds
322 * of data structure. That's dictated by the hardware; a type tag is
323 * encoded in the low bits of the hardware's periodic schedule. Use
324 * Q_NEXT_TYPE to get the tag.
326 * For entries in the async schedule, the type tag always says "qh".
329 struct ehci_qh *qh; /* Q_TYPE_QH */
330 struct ehci_itd *itd; /* Q_TYPE_ITD */
331 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
332 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
333 u32 *hw_next; /* (all types) */
337 /*-------------------------------------------------------------------------*/
340 * EHCI Specification 0.95 Section 3.6
341 * QH: describes control/bulk/interrupt endpoints
342 * See Fig 3-7 "Queue Head Structure Layout".
344 * These appear in both the async and (for interrupt) periodic schedules.
348 /* first part defined by EHCI spec */
349 u32 hw_next; /* see EHCI 3.6.1 */
350 u32 hw_info1; /* see EHCI 3.6.2 */
351 #define QH_HEAD 0x00008000
352 u32 hw_info2; /* see EHCI 3.6.2 */
353 u32 hw_current; /* qtd list - see EHCI 3.6.4 */
355 /* qtd overlay (hardware parts of a struct ehci_qtd) */
362 /* the rest is HCD-private */
363 dma_addr_t qh_dma; /* address of qh */
364 union ehci_shadow qh_next; /* ptr to qh; or periodic */
365 struct list_head qtd_list; /* sw qtd list */
366 struct ehci_qtd *dummy;
367 struct ehci_qh *reclaim; /* next to reclaim */
373 #define QH_STATE_LINKED 1 /* HC sees this */
374 #define QH_STATE_UNLINK 2 /* HC may still see this */
375 #define QH_STATE_IDLE 3 /* HC doesn't see this */
376 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
377 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
379 /* periodic schedule info */
380 u8 usecs; /* intr bandwidth */
381 u8 gap_uf; /* uframes split/csplit gap */
382 u8 c_usecs; /* ... split completion bw */
383 unsigned short period; /* polling interval */
384 unsigned short start; /* where polling starts */
385 #define NO_FRAME ((unsigned short)~0) /* pick new start */
386 struct usb_device *dev; /* access to TT */
387 } __attribute__ ((aligned (32)));
389 /*-------------------------------------------------------------------------*/
391 /* description of one iso transaction (up to 3 KB data if highspeed) */
392 struct ehci_iso_packet {
393 /* These will be copied to iTD when scheduling */
394 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
395 u32 transaction; /* itd->hw_transaction[i] |= */
396 u8 cross; /* buf crosses pages */
397 /* for full speed OUT splits */
401 /* temporary schedule data for packets from iso urbs (both speeds)
402 * each packet is one logical usb transaction to the device (not TT),
403 * beginning at stream->next_uframe
405 struct ehci_iso_sched {
406 struct list_head td_list;
408 struct ehci_iso_packet packet [0];
412 * ehci_iso_stream - groups all (s)itds for this endpoint.
413 * acts like a qh would, if EHCI had them for ISO.
415 struct ehci_iso_stream {
416 /* first two fields match QH, but info1 == 0 */
423 u16 depth; /* depth in uframes */
424 struct list_head td_list; /* queued itds/sitds */
425 struct list_head free_list; /* list of unused itds/sitds */
426 struct usb_device *udev;
428 /* output of (re)scheduling */
429 unsigned long start; /* jiffies */
430 unsigned long rescheduled;
434 /* the rest is derived from the endpoint descriptor,
435 * trusting urb->interval == f(epdesc->bInterval) and
436 * including the extra info for hw_bufp[0..2]
444 /* This is used to initialize iTD's hw_bufp fields */
449 /* this is used to initialize sITD's tt info */
453 /*-------------------------------------------------------------------------*/
456 * EHCI Specification 0.95 Section 3.3
457 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
459 * Schedule records for high speed iso xfers
462 /* first part defined by EHCI spec */
463 u32 hw_next; /* see EHCI 3.3.1 */
464 u32 hw_transaction [8]; /* see EHCI 3.3.2 */
465 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
466 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
467 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
468 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
469 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
470 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
472 #define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
474 u32 hw_bufp [7]; /* see EHCI 3.3.3 */
475 u32 hw_bufp_hi [7]; /* Appendix B */
477 /* the rest is HCD-private */
478 dma_addr_t itd_dma; /* for this itd */
479 union ehci_shadow itd_next; /* ptr to periodic q entry */
482 struct ehci_iso_stream *stream; /* endpoint's queue */
483 struct list_head itd_list; /* list of stream's itds */
485 /* any/all hw_transactions here may be used by that urb */
486 unsigned frame; /* where scheduled */
488 unsigned index[8]; /* in urb->iso_frame_desc */
490 } __attribute__ ((aligned (32)));
492 /*-------------------------------------------------------------------------*/
495 * EHCI Specification 0.95 Section 3.4
496 * siTD, aka split-transaction isochronous Transfer Descriptor
497 * ... describe full speed iso xfers through TT in hubs
498 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
501 /* first part defined by EHCI spec */
503 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
504 u32 hw_fullspeed_ep; /* EHCI table 3-9 */
505 u32 hw_uframe; /* EHCI table 3-10 */
506 u32 hw_results; /* EHCI table 3-11 */
507 #define SITD_IOC (1 << 31) /* interrupt on completion */
508 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
509 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
510 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
511 #define SITD_STS_ERR (1 << 6) /* error from TT */
512 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
513 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
514 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
515 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
516 #define SITD_STS_STS (1 << 1) /* split transaction state */
518 #define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE)
520 u32 hw_buf [2]; /* EHCI table 3-12 */
521 u32 hw_backpointer; /* EHCI table 3-13 */
522 u32 hw_buf_hi [2]; /* Appendix B */
524 /* the rest is HCD-private */
526 union ehci_shadow sitd_next; /* ptr to periodic q entry */
529 struct ehci_iso_stream *stream; /* endpoint's queue */
530 struct list_head sitd_list; /* list of stream's sitds */
533 } __attribute__ ((aligned (32)));
535 /*-------------------------------------------------------------------------*/
538 * EHCI Specification 0.96 Section 3.7
539 * Periodic Frame Span Traversal Node (FSTN)
541 * Manages split interrupt transactions (using TT) that span frame boundaries
542 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
543 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
544 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
547 u32 hw_next; /* any periodic q entry */
548 u32 hw_prev; /* qh or EHCI_LIST_END */
550 /* the rest is HCD-private */
552 union ehci_shadow fstn_next; /* ptr to periodic q entry */
553 } __attribute__ ((aligned (32)));
555 /*-------------------------------------------------------------------------*/
557 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
560 * Some EHCI controllers have a Transaction Translator built into the
561 * root hub. This is a non-standard feature. Each controller will need
562 * to add code to the following inline functions, and call them as
563 * needed (mostly in root hub code).
566 #define ehci_is_ARC(e) ((e)->is_arc_rh_tt)
568 /* Returns the speed of a device attached to a port on the root hub. */
569 static inline unsigned int
570 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
572 if (ehci_is_ARC(ehci)) {
573 switch ((portsc>>26)&3) {
577 return (1<<USB_PORT_FEAT_LOWSPEED);
580 return (1<<USB_PORT_FEAT_HIGHSPEED);
583 return (1<<USB_PORT_FEAT_HIGHSPEED);
588 #define ehci_is_ARC(e) (0)
590 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
593 /*-------------------------------------------------------------------------*/
596 #define STUB_DEBUG_FILES
599 /*-------------------------------------------------------------------------*/
601 #endif /* __LINUX_EHCI_HCD_H */