drivers/video/aty/radeon_base.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2003  Ben. Herrenschmidt <benh@kernel.crashing.org>
   6  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
   7  *
   8  *      i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
   9  *
  10  *      Special thanks to ATI DevRel team for their hardware donations.
  11  *
  12  *      ...Insert GPL boilerplate here...
  13  *
  14  *      Significant portions of this driver apdated from XFree86 Radeon
  15  *      driver which has the following copyright notice:
  16  *
  17  *      Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  18  *                     VA Linux Systems Inc., Fremont, California.
  19  *
  20  *      All Rights Reserved.
  21  *
  22  *      Permission is hereby granted, free of charge, to any person obtaining
  23  *      a copy of this software and associated documentation files (the
  24  *      "Software"), to deal in the Software without restriction, including
  25  *      without limitation on the rights to use, copy, modify, merge,
  26  *      publish, distribute, sublicense, and/or sell copies of the Software,
  27  *      and to permit persons to whom the Software is furnished to do so,
  28  *      subject to the following conditions:
  29  *
  30  *      The above copyright notice and this permission notice (including the
  31  *      next paragraph) shall be included in all copies or substantial
  32  *      portions of the Software.
  33  *
  34  *      THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *      EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  36  *      MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *      NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  38  *      THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *      WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  40  *      OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  41  *      DEALINGS IN THE SOFTWARE.
  42  *
  43  *      XFree86 driver authors:
  44  *
  45  *         Kevin E. Martin <martin@xfree86.org>
  46  *         Rickard E. Faith <faith@valinux.com>
  47  *         Alan Hourihane <alanh@fairlite.demon.co.uk>
  48  *
  49  */
  50
  51
  52 #define RADEON_VERSION  "0.2.0"
  53
  54 #include <linux/config.h>
  55 #include <linux/module.h>
  56 #include <linux/moduleparam.h>
  57 #include <linux/kernel.h>
  58 #include <linux/errno.h>
  59 #include <linux/string.h>
  60 #include <linux/mm.h>
  61 #include <linux/tty.h>
  62 #include <linux/slab.h>
  63 #include <linux/delay.h>
  64 #include <linux/fb.h>
  65 #include <linux/ioport.h>
  66 #include <linux/init.h>
  67 #include <linux/pci.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/device.h>
  70 #include <linux/i2c.h>
  71
  72 #include <asm/io.h>
  73 #include <asm/uaccess.h>
  74
  75 #ifdef CONFIG_PPC_OF
  76
  77 #include <asm/prom.h>
  78 #include <asm/pci-bridge.h>
  79 #include "../macmodes.h"
  80
  81 #ifdef CONFIG_PMAC_BACKLIGHT
  82 #include <asm/backlight.h>
  83 #endif
  84
  85 #ifdef CONFIG_BOOTX_TEXT
  86 #include <asm/btext.h>
  87 #endif
  88
  89 #endif /* CONFIG_PPC_OF */
  90
  91 #ifdef CONFIG_MTRR
  92 #include <asm/mtrr.h>
  93 #endif
  94
  95 #include <video/radeon.h>
  96 #include <linux/radeonfb.h>
  97
  98 #include "../edid.h" // MOVE THAT TO include/video
  99 #include "ati_ids.h"
 100 #include "radeonfb.h"
 101
 102 #define MAX_MAPPED_VRAM (2048*2048*4)
 103 #define MIN_MAPPED_VRAM (1024*768*1)
 104
 105 #define CHIP_DEF(id, family, flags)                                     \
 106         { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
 107
 108 static struct pci_device_id radeonfb_pci_table[] = {
 109         /* Mobility M6 */
 110         CHIP_DEF(PCI_CHIP_RADEON_LY,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 111         CHIP_DEF(PCI_CHIP_RADEON_LZ,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 112         /* Radeon VE/7000 */
 113         CHIP_DEF(PCI_CHIP_RV100_QY,     RV100,  CHIP_HAS_CRTC2),
 114         CHIP_DEF(PCI_CHIP_RV100_QZ,     RV100,  CHIP_HAS_CRTC2),
 115         /* Radeon IGP320M (U1) */
 116         CHIP_DEF(PCI_CHIP_RS100_4336,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 117         /* Radeon IGP320 (A3) */
 118         CHIP_DEF(PCI_CHIP_RS100_4136,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 119         /* IGP330M/340M/350M (U2) */
 120         CHIP_DEF(PCI_CHIP_RS200_4337,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 121         /* IGP330/340/350 (A4) */
 122         CHIP_DEF(PCI_CHIP_RS200_4137,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 123         /* Mobility 7000 IGP */
 124         CHIP_DEF(PCI_CHIP_RS250_4437,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 125         /* 7000 IGP (A4+) */
 126         CHIP_DEF(PCI_CHIP_RS250_4237,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 127         /* 8500 AIW */
 128         CHIP_DEF(PCI_CHIP_R200_BB,      R200,   CHIP_HAS_CRTC2),
 129         CHIP_DEF(PCI_CHIP_R200_BC,      R200,   CHIP_HAS_CRTC2),
 130         /* 8700/8800 */
 131         CHIP_DEF(PCI_CHIP_R200_QH,      R200,   CHIP_HAS_CRTC2),
 132         /* 8500 */
 133         CHIP_DEF(PCI_CHIP_R200_QL,      R200,   CHIP_HAS_CRTC2),
 134         /* 9100 */
 135         CHIP_DEF(PCI_CHIP_R200_QM,      R200,   CHIP_HAS_CRTC2),
 136         /* Mobility M7 */
 137         CHIP_DEF(PCI_CHIP_RADEON_LW,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 138         CHIP_DEF(PCI_CHIP_RADEON_LX,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 139         /* 7500 */
 140         CHIP_DEF(PCI_CHIP_RV200_QW,     RV200,  CHIP_HAS_CRTC2),
 141         CHIP_DEF(PCI_CHIP_RV200_QX,     RV200,  CHIP_HAS_CRTC2),
 142         /* Mobility M9 */
 143         CHIP_DEF(PCI_CHIP_RV250_Ld,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 144         CHIP_DEF(PCI_CHIP_RV250_Le,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 145         CHIP_DEF(PCI_CHIP_RV250_Lf,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 146         CHIP_DEF(PCI_CHIP_RV250_Lg,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 147         /* 9000/Pro */
 148         CHIP_DEF(PCI_CHIP_RV250_If,     RV250,  CHIP_HAS_CRTC2),
 149         CHIP_DEF(PCI_CHIP_RV250_Ig,     RV250,  CHIP_HAS_CRTC2),
 150         /* Mobility 9100 IGP (U3) */
 151         CHIP_DEF(PCI_CHIP_RS300_5835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 152         /* 9100 IGP (A5) */
 153         CHIP_DEF(PCI_CHIP_RS300_5834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 154         /* Mobility 9200 (M9+) */
 155         CHIP_DEF(PCI_CHIP_RV280_5C61,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 156         CHIP_DEF(PCI_CHIP_RV280_5C63,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 157         /* 9200 */
 158         CHIP_DEF(PCI_CHIP_RV280_5960,   RV280,  CHIP_HAS_CRTC2),
 159         CHIP_DEF(PCI_CHIP_RV280_5961,   RV280,  CHIP_HAS_CRTC2),
 160         CHIP_DEF(PCI_CHIP_RV280_5962,   RV280,  CHIP_HAS_CRTC2),
 161         CHIP_DEF(PCI_CHIP_RV280_5964,   RV280,  CHIP_HAS_CRTC2),
 162         /* 9500 */
 163         CHIP_DEF(PCI_CHIP_R300_AD,      R300,   CHIP_HAS_CRTC2),
 164         CHIP_DEF(PCI_CHIP_R300_AE,      R300,   CHIP_HAS_CRTC2),
 165         /* 9600TX / FireGL Z1 */
 166         CHIP_DEF(PCI_CHIP_R300_AF,      R300,   CHIP_HAS_CRTC2),
 167         CHIP_DEF(PCI_CHIP_R300_AG,      R300,   CHIP_HAS_CRTC2),
 168         /* 9700/9500/Pro/FireGL X1 */
 169         CHIP_DEF(PCI_CHIP_R300_ND,      R300,   CHIP_HAS_CRTC2),
 170         CHIP_DEF(PCI_CHIP_R300_NE,      R300,   CHIP_HAS_CRTC2),
 171         CHIP_DEF(PCI_CHIP_R300_NF,      R300,   CHIP_HAS_CRTC2),
 172         CHIP_DEF(PCI_CHIP_R300_NG,      R300,   CHIP_HAS_CRTC2),
 173         /* Mobility M10/M11 */
 174         CHIP_DEF(PCI_CHIP_RV350_NP,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 175         CHIP_DEF(PCI_CHIP_RV350_NQ,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 176         CHIP_DEF(PCI_CHIP_RV350_NR,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 177         CHIP_DEF(PCI_CHIP_RV350_NS,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 178         CHIP_DEF(PCI_CHIP_RV350_NT,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 179         CHIP_DEF(PCI_CHIP_RV350_NV,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 180         /* 9600/FireGL T2 */
 181         CHIP_DEF(PCI_CHIP_RV350_AP,     RV350,  CHIP_HAS_CRTC2),
 182         CHIP_DEF(PCI_CHIP_RV350_AQ,     RV350,  CHIP_HAS_CRTC2),
 183         CHIP_DEF(PCI_CHIP_RV360_AR,     RV350,  CHIP_HAS_CRTC2),
 184         CHIP_DEF(PCI_CHIP_RV350_AS,     RV350,  CHIP_HAS_CRTC2),
 185         CHIP_DEF(PCI_CHIP_RV350_AT,     RV350,  CHIP_HAS_CRTC2),
 186         CHIP_DEF(PCI_CHIP_RV350_AV,     RV350,  CHIP_HAS_CRTC2),
 187         /* 9800/Pro/FileGL X2 */
 188         CHIP_DEF(PCI_CHIP_R350_AH,      R350,   CHIP_HAS_CRTC2),
 189         CHIP_DEF(PCI_CHIP_R350_AI,      R350,   CHIP_HAS_CRTC2),
 190         CHIP_DEF(PCI_CHIP_R350_AJ,      R350,   CHIP_HAS_CRTC2),
 191         CHIP_DEF(PCI_CHIP_R350_AK,      R350,   CHIP_HAS_CRTC2),
 192         CHIP_DEF(PCI_CHIP_R350_NH,      R350,   CHIP_HAS_CRTC2),
 193         CHIP_DEF(PCI_CHIP_R350_NI,      R350,   CHIP_HAS_CRTC2),
 194         CHIP_DEF(PCI_CHIP_R360_NJ,      R350,   CHIP_HAS_CRTC2),
 195         CHIP_DEF(PCI_CHIP_R350_NK,      R350,   CHIP_HAS_CRTC2),
 196         /* Original Radeon/7200 */
 197         CHIP_DEF(PCI_CHIP_RADEON_QD,    RADEON, 0),
 198         CHIP_DEF(PCI_CHIP_RADEON_QE,    RADEON, 0),
 199         CHIP_DEF(PCI_CHIP_RADEON_QF,    RADEON, 0),
 200         CHIP_DEF(PCI_CHIP_RADEON_QG,    RADEON, 0),
 201         { 0, }
 202 };
 203 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 204
 205
 206 typedef struct {
 207         u16 reg;
 208         u32 val;
 209 } reg_val;
 210
 211
 212 /* these common regs are cleared before mode setting so they do not
 213  * interfere with anything
 214  */
 215 static reg_val common_regs[] = {
 216         { OVR_CLR, 0 },
 217         { OVR_WID_LEFT_RIGHT, 0 },
 218         { OVR_WID_TOP_BOTTOM, 0 },
 219         { OV0_SCALE_CNTL, 0 },
 220         { SUBPIC_CNTL, 0 },
 221         { VIPH_CONTROL, 0 },
 222         { I2C_CNTL_1, 0 },
 223         { GEN_INT_CNTL, 0 },
 224         { CAP0_TRIG_CNTL, 0 },
 225         { CAP1_TRIG_CNTL, 0 },
 226 };
 227
 228 /*
 229  * globals
 230  */
 231
 232 static char *mode_option;
 233 static char *monitor_layout;
 234 static int noaccel = 0;
 235 static int nomodeset = 0;
 236 static int ignore_edid = 0;
 237 static int mirror = 0;
 238 static int panel_yres = 0;
 239 static int force_dfp = 0;
 240 static int force_measure_pll = 0;
 241 #ifdef CONFIG_MTRR
 242 static int nomtrr = 0;
 243 #endif
 244
 245 int radeonfb_noaccel = 0;
 246
 247 /*
 248  * prototypes
 249  */
 250
 251
 252 #ifdef CONFIG_PPC_OF
 253
 254 #ifdef CONFIG_PMAC_BACKLIGHT
 255 static int radeon_set_backlight_enable(int on, int level, void *data);
 256 static int radeon_set_backlight_level(int level, void *data);
 257 static struct backlight_controller radeon_backlight_controller = {
 258         radeon_set_backlight_enable,
 259         radeon_set_backlight_level
 260 };
 261 #endif /* CONFIG_PMAC_BACKLIGHT */
 262
 263 #endif /* CONFIG_PPC_OF */
 264
 265 static void __devexit radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 266 {
 267         // leave it disabled and unassigned
 268         struct resource *r = &dev->resource[PCI_ROM_RESOURCE];
 269
 270         if (!rinfo->bios_seg)
 271                 return;
 272         iounmap(rinfo->bios_seg);
 273
 274         /* Release the ROM resource if we used it in the first place */
 275         if (r->parent && r->flags & PCI_ROM_ADDRESS_ENABLE) {
 276                 release_resource(r);
 277                 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
 278                 r->end -= r->start;
 279                 r->start = 0;
 280         }
 281         /* This will disable and set address to unassigned */
 282         pci_write_config_dword(dev, dev->rom_base_reg, 0);
 283 }
 284
 285 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 286 {
 287         void *rom;
 288         struct resource *r;
 289         u16 dptr;
 290         u8 rom_type;
 291
 292         /* If this is a primary card, there is a shadow copy of the
 293          * ROM somewhere in the first meg. We will just ignore the copy
 294          * and use the ROM directly.
 295          */
 296
 297         /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
 298         unsigned int temp;
 299         temp = INREG(MPP_TB_CONFIG);
 300         temp &= 0x00ffffffu;
 301         temp |= 0x04 << 24;
 302         OUTREG(MPP_TB_CONFIG, temp);
 303         temp = INREG(MPP_TB_CONFIG);
 304
 305         /* no need to search for the ROM, just ask the card where it is. */
 306         r = &dev->resource[PCI_ROM_RESOURCE];
 307
 308         /* assign the ROM an address if it doesn't have one */
 309         if (r->parent == NULL)
 310                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 311
 312         /* enable if needed */
 313         if (!(r->flags & PCI_ROM_ADDRESS_ENABLE)) {
 314                 pci_write_config_dword(dev, dev->rom_base_reg,
 315                                        r->start | PCI_ROM_ADDRESS_ENABLE);
 316                 r->flags |= PCI_ROM_ADDRESS_ENABLE;
 317         }
 318
 319         rom = ioremap(r->start, r->end - r->start + 1);
 320         if (!rom) {
 321                 printk(KERN_ERR "radeonfb: ROM failed to map\n");
 322                 return -ENOMEM;
 323         }
 324
 325         rinfo->bios_seg = rom;
 326
 327         /* Very simple test to make sure it appeared */
 328         if (BIOS_IN16(0) != 0xaa55) {
 329                 printk(KERN_ERR "radeonfb: Invalid ROM signature %x should be 0xaa55\n",
 330                        BIOS_IN16(0));
 331                 goto failed;
 332         }
 333         /* Look for the PCI data to check the ROM type */
 334         dptr = BIOS_IN16(0x18);
 335
 336         /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
 337          * for now, until I've verified this works everywhere. The goal here is more
 338          * to phase out Open Firmware images.
 339          *
 340          * Currently, we only look at the first PCI data, we could iteratre and deal with
 341          * them all, and we should use fb_bios_start relative to start of image and not
 342          * relative start of ROM, but so far, I never found a dual-image ATI card
 343          *
 344          * typedef struct {
 345          *      u32     signature;      + 0x00
 346          *      u16     vendor;         + 0x04
 347          *      u16     device;         + 0x06
 348          *      u16     reserved_1;     + 0x08
 349          *      u16     dlen;           + 0x0a
 350          *      u8      drevision;      + 0x0c
 351          *      u8      class_hi;       + 0x0d
 352          *      u16     class_lo;       + 0x0e
 353          *      u16     ilen;           + 0x10
 354          *      u16     irevision;      + 0x12
 355          *      u8      type;           + 0x14
 356          *      u8      indicator;      + 0x15
 357          *      u16     reserved_2;     + 0x16
 358          * } pci_data_t;
 359          */
 360         if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 361                 printk(KERN_WARNING "radeonfb: PCI DATA signature in ROM incorrect: %08x\n",
 362                        BIOS_IN32(dptr));
 363                 goto anyway;
 364         }
 365         rom_type = BIOS_IN8(dptr + 0x14);
 366         switch(rom_type) {
 367         case 0:
 368                 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
 369                 break;
 370         case 1:
 371                 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
 372                 goto failed;
 373         case 2:
 374                 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
 375                 goto failed;
 376         default:
 377                 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
 378                 goto failed;
 379         }
 380  anyway:
 381         /* Locate the flat panel infos, do some sanity checking !!! */
 382         rinfo->fp_bios_start = BIOS_IN16(0x48);
 383         return 0;
 384
 385  failed:
 386         rinfo->bios_seg = NULL;
 387         radeon_unmap_ROM(rinfo, dev);
 388         return -ENXIO;
 389 }
 390
 391 #ifdef __i386__
 392 static int  __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
 393 {
 394         /* I simplified this code as we used to miss the signatures in
 395          * a lot of case. It's now closer to XFree, we just don't check
 396          * for signatures at all... Something better will have to be done
 397          * if we end up having conflicts
 398          */
 399         u32  segstart;
 400         unsigned char *rom_base = NULL;
 401
 402         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 403                 rom_base = (char *)ioremap(segstart, 0x10000);
 404                 if (rom_base == NULL)
 405                         return -ENOMEM;
 406                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
 407                         break;
 408                 iounmap(rom_base);
 409                 rom_base = NULL;
 410         }
 411         if (rom_base == NULL)
 412                 return -ENXIO;
 413
 414         /* Locate the flat panel infos, do some sanity checking !!! */
 415         rinfo->bios_seg = rom_base;
 416         rinfo->fp_bios_start = BIOS_IN16(0x48);
 417
 418         return 0;
 419 }
 420 #endif /* __i386__ */
 421
 422 #ifdef CONFIG_PPC_OF
 423 /*
 424  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
 425  * tree. Hopefully, ATI OF driver is kind enough to fill these
 426  */
 427 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
 428 {
 429         struct device_node *dp;
 430         u32 *val;
 431
 432         dp = pci_device_to_OF_node(rinfo->pdev);
 433         if (dp == NULL) {
 434                 printk(KERN_WARNING "radeonfb: Cannot match card to OF node !\n");
 435                 return -ENODEV;
 436         }
 437         val = (u32 *) get_property(dp, "ATY,RefCLK", 0);
 438         if (!val || !*val) {
 439                 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
 440                 return -EINVAL;
 441         }
 442
 443         rinfo->pll.ref_clk = (*val) / 10;
 444
 445         val = (u32 *) get_property(dp, "ATY,SCLK", 0);
 446         if (val && *val)
 447                 rinfo->pll.sclk = (*val) / 10;
 448
 449         val = (u32 *) get_property(dp, "ATY,MCLK", 0);
 450         if (val && *val)
 451                 rinfo->pll.mclk = (*val) / 10;
 452
 453         return 0;
 454 }
 455 #endif /* CONFIG_PPC_OF */
 456
 457 /*
 458  * Read PLL infos from chip registers
 459  */
 460 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
 461 {
 462         unsigned char ppll_div_sel;
 463         unsigned Ns, Nm, M;
 464         unsigned sclk, mclk, tmp, ref_div;
 465         int hTotal, vTotal, num, denom, m, n;
 466         unsigned long long hz, vclk;
 467         long xtal;
 468         struct timeval start_tv, stop_tv;
 469         long total_secs, total_usecs;
 470         int i;
 471
 472         /* Ugh, we cut interrupts, bad bad bad, but we want some precision
 473          * here, so... --BenH
 474          */
 475
 476         /* Flush PCI buffers ? */
 477         tmp = INREG(DEVICE_ID);
 478
 479         local_irq_disable();
 480
 481         for(i=0; i<1000000; i++)
 482                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 483                         break;
 484
 485         do_gettimeofday(&start_tv);
 486
 487         for(i=0; i<1000000; i++)
 488                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
 489                         break;
 490
 491         for(i=0; i<1000000; i++)
 492                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 493                         break;
 494
 495         do_gettimeofday(&stop_tv);
 496
 497         local_irq_enable();
 498
 499         total_secs = stop_tv.tv_sec - start_tv.tv_sec;
 500         if (total_secs > 10)
 501                 return -1;
 502         total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
 503         total_usecs += total_secs * 1000000;
 504         if (total_usecs < 0)
 505                 total_usecs = -total_usecs;
 506         hz = 1000000/total_usecs;
 507
 508         hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
 509         vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
 510         vclk = (long long)hTotal * (long long)vTotal * hz;
 511
 512         switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
 513         case 0:
 514         default:
 515                 num = 1;
 516                 denom = 1;
 517                 break;
 518         case 1:
 519                 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 16) & 0xff);
 520                 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
 521                 num = 2*n;
 522                 denom = 2*m;
 523                 break;
 524         case 2:
 525                 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 8) & 0xff);
 526                 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
 527                 num = 2*n;
 528                 denom = 2*m;
 529         break;
 530         }
 531
 532         OUTREG8(CLOCK_CNTL_INDEX, 1);
 533         ppll_div_sel = INREG8(CLOCK_CNTL_DATA + 1) & 0x3;
 534
 535         n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
 536         m = (INPLL(PPLL_REF_DIV) & 0x3ff);
 537
 538         num *= n;
 539         denom *= m;
 540
 541         switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
 542         case 1:
 543                 denom *= 2;
 544                 break;
 545         case 2:
 546                 denom *= 4;
 547                 break;
 548         case 3:
 549                 denom *= 8;
 550                 break;
 551         case 4:
 552                 denom *= 3;
 553                 break;
 554         case 6:
 555                 denom *= 6;
 556                 break;
 557         case 7:
 558                 denom *= 12;
 559                 break;
 560         }
 561
 562         vclk *= denom;
 563         do_div(vclk, 1000 * num);
 564         xtal = vclk;
 565
 566         if ((xtal > 26900) && (xtal < 27100))
 567                 xtal = 2700;
 568         else if ((xtal > 14200) && (xtal < 14400))
 569                 xtal = 1432;
 570         else if ((xtal > 29400) && (xtal < 29600))
 571                 xtal = 2950;
 572         else {
 573                 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
 574                 return -1;
 575         }
 576
 577         tmp = INPLL(X_MPLL_REF_FB_DIV);
 578         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 579
 580         Ns = (tmp & 0xff0000) >> 16;
 581         Nm = (tmp & 0xff00) >> 8;
 582         M = (tmp & 0xff);
 583         sclk = round_div((2 * Ns * xtal), (2 * M));
 584         mclk = round_div((2 * Nm * xtal), (2 * M));
 585
 586         /* we're done, hopefully these are sane values */
 587         rinfo->pll.ref_clk = xtal;
 588         rinfo->pll.ref_div = ref_div;
 589         rinfo->pll.sclk = sclk;
 590         rinfo->pll.mclk = mclk;
 591
 592         return 0;
 593 }
 594
 595 /*
 596  * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
 597  */
 598 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
 599 {
 600 #ifdef CONFIG_PPC_OF
 601         /*
 602          * Retreive PLL infos from Open Firmware first
 603          */
 604         if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
 605                 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
 606                 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 607                 /* FIXME: Max clock may be higher on newer chips */
 608                 rinfo->pll.ppll_min = 12000;
 609                 rinfo->pll.ppll_max = 35000;
 610                 goto found;
 611         }
 612 #endif /* CONFIG_PPC_OF */
 613
 614         /*
 615          * Check out if we have an X86 which gave us some PLL informations
 616          * and if yes, retreive them
 617          */
 618         if (!force_measure_pll && rinfo->bios_seg) {
 619                 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
 620
 621                 rinfo->pll.sclk         = BIOS_IN16(pll_info_block + 0x08);
 622                 rinfo->pll.mclk         = BIOS_IN16(pll_info_block + 0x0a);
 623                 rinfo->pll.ref_clk      = BIOS_IN16(pll_info_block + 0x0e);
 624                 rinfo->pll.ref_div      = BIOS_IN16(pll_info_block + 0x10);
 625                 rinfo->pll.ppll_min     = BIOS_IN32(pll_info_block + 0x12);
 626                 rinfo->pll.ppll_max     = BIOS_IN32(pll_info_block + 0x16);
 627
 628                 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
 629                 goto found;
 630         }
 631
 632         /*
 633          * We didn't get PLL parameters from either OF or BIOS, we try to
 634          * probe them
 635          */
 636         if (radeon_probe_pll_params(rinfo) == 0) {
 637                 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
 638                 /* FIXME: Max clock may be higher on newer chips */
 639                 rinfo->pll.ppll_min = 12000;
 640                 rinfo->pll.ppll_max = 35000;
 641                 goto found;
 642         }
 643
 644         /*
 645          * Neither of the above worked, we have a few default values, though
 646          * that's mostly incomplete
 647          */
 648         switch (rinfo->chipset) {
 649         case PCI_DEVICE_ID_ATI_RADEON_QW:
 650         case PCI_DEVICE_ID_ATI_RADEON_QX:
 651                 rinfo->pll.ppll_max = 35000;
 652                 rinfo->pll.ppll_min = 12000;
 653                 rinfo->pll.mclk = 23000;
 654                 rinfo->pll.sclk = 23000;
 655                 rinfo->pll.ref_clk = 2700;
 656                 break;
 657         case PCI_DEVICE_ID_ATI_RADEON_QL:
 658         case PCI_DEVICE_ID_ATI_RADEON_QN:
 659         case PCI_DEVICE_ID_ATI_RADEON_QO:
 660         case PCI_DEVICE_ID_ATI_RADEON_Ql:
 661         case PCI_DEVICE_ID_ATI_RADEON_BB:
 662                 rinfo->pll.ppll_max = 35000;
 663                 rinfo->pll.ppll_min = 12000;
 664                 rinfo->pll.mclk = 27500;
 665                 rinfo->pll.sclk = 27500;
 666                 rinfo->pll.ref_clk = 2700;
 667                 break;
 668         case PCI_DEVICE_ID_ATI_RADEON_Id:
 669         case PCI_DEVICE_ID_ATI_RADEON_Ie:
 670         case PCI_DEVICE_ID_ATI_RADEON_If:
 671         case PCI_DEVICE_ID_ATI_RADEON_Ig:
 672                 rinfo->pll.ppll_max = 35000;
 673                 rinfo->pll.ppll_min = 12000;
 674                 rinfo->pll.mclk = 25000;
 675                 rinfo->pll.sclk = 25000;
 676                 rinfo->pll.ref_clk = 2700;
 677                 break;
 678         case PCI_DEVICE_ID_ATI_RADEON_ND:
 679         case PCI_DEVICE_ID_ATI_RADEON_NE:
 680         case PCI_DEVICE_ID_ATI_RADEON_NF:
 681         case PCI_DEVICE_ID_ATI_RADEON_NG:
 682                 rinfo->pll.ppll_max = 40000;
 683                 rinfo->pll.ppll_min = 20000;
 684                 rinfo->pll.mclk = 27000;
 685                 rinfo->pll.sclk = 27000;
 686                 rinfo->pll.ref_clk = 2700;
 687                 break;
 688         case PCI_DEVICE_ID_ATI_RADEON_QD:
 689         case PCI_DEVICE_ID_ATI_RADEON_QE:
 690         case PCI_DEVICE_ID_ATI_RADEON_QF:
 691         case PCI_DEVICE_ID_ATI_RADEON_QG:
 692         default:
 693                 rinfo->pll.ppll_max = 35000;
 694                 rinfo->pll.ppll_min = 12000;
 695                 rinfo->pll.mclk = 16600;
 696                 rinfo->pll.sclk = 16600;
 697                 rinfo->pll.ref_clk = 2700;
 698                 break;
 699         }
 700         rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 701
 702         printk(KERN_INFO "radeonfb: Used default PLL infos\n");
 703
 704 found:
 705         /*
 706          * Some methods fail to retreive SCLK and MCLK values, we apply default
 707          * settings in this case (200Mhz). If that really happne often, we could
 708          * fetch from registers instead...
 709          */
 710         if (rinfo->pll.mclk == 0)
 711                 rinfo->pll.mclk = 20000;
 712         if (rinfo->pll.sclk == 0)
 713                 rinfo->pll.sclk = 20000;
 714
 715         printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
 716                rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
 717                rinfo->pll.ref_div,
 718                rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
 719                rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
 720 }
 721
 722 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
 723 {
 724         struct radeonfb_info *rinfo = info->par;
 725         struct fb_var_screeninfo v;
 726         int nom, den;
 727         unsigned int pitch;
 728
 729         if (radeon_match_mode(rinfo, &v, var))
 730                 return -EINVAL;
 731
 732         switch (v.bits_per_pixel) {
 733                 case 0 ... 8:
 734                         v.bits_per_pixel = 8;
 735                         break;
 736                 case 9 ... 16:
 737                         v.bits_per_pixel = 16;
 738                         break;
 739                 case 17 ... 24:
 740 #if 0 /* Doesn't seem to work */
 741                         v.bits_per_pixel = 24;
 742                         break;
 743 #endif
 744                         return -EINVAL;
 745                 case 25 ... 32:
 746                         v.bits_per_pixel = 32;
 747                         break;
 748                 default:
 749                         return -EINVAL;
 750         }
 751
 752         switch (var_to_depth(&v)) {
 753                 case 8:
 754                         nom = den = 1;
 755                         v.red.offset = v.green.offset = v.blue.offset = 0;
 756                         v.red.length = v.green.length = v.blue.length = 8;
 757                         v.transp.offset = v.transp.length = 0;
 758                         break;
 759                 case 15:
 760                         nom = 2;
 761                         den = 1;
 762                         v.red.offset = 10;
 763                         v.green.offset = 5;
 764                         v.blue.offset = 0;
 765                         v.red.length = v.green.length = v.blue.length = 5;
 766                         v.transp.offset = v.transp.length = 0;
 767                         break;
 768                 case 16:
 769                         nom = 2;
 770                         den = 1;
 771                         v.red.offset = 11;
 772                         v.green.offset = 5;
 773                         v.blue.offset = 0;
 774                         v.red.length = 5;
 775                         v.green.length = 6;
 776                         v.blue.length = 5;
 777                         v.transp.offset = v.transp.length = 0;
 778                         break;
 779                 case 24:
 780                         nom = 4;
 781                         den = 1;
 782                         v.red.offset = 16;
 783                         v.green.offset = 8;
 784                         v.blue.offset = 0;
 785                         v.red.length = v.blue.length = v.green.length = 8;
 786                         v.transp.offset = v.transp.length = 0;
 787                         break;
 788                 case 32:
 789                         nom = 4;
 790                         den = 1;
 791                         v.red.offset = 16;
 792                         v.green.offset = 8;
 793                         v.blue.offset = 0;
 794                         v.red.length = v.blue.length = v.green.length = 8;
 795                         v.transp.offset = 24;
 796                         v.transp.length = 8;
 797                         break;
 798                 default:
 799                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
 800                                 var->xres, var->yres, var->bits_per_pixel);
 801                         return -EINVAL;
 802         }
 803
 804         if (v.yres_virtual < v.yres)
 805                 v.yres_virtual = v.yres;
 806         if (v.xres_virtual < v.xres)
 807                 v.xres_virtual = v.xres;
 808
 809
 810         /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
 811          * with some panels, though I don't quite like this solution
 812          */
 813         if (radeon_accel_disabled()) {
 814                 v.xres_virtual = v.xres_virtual & ~7ul;
 815                 v.accel_flags = 0;
 816         } else {
 817                 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
 818                                 & ~(0x3f)) >> 6;
 819                 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
 820         }
 821
 822         if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
 823                 return -EINVAL;
 824
 825         if (v.xres_virtual < v.xres)
 826                 v.xres = v.xres_virtual;
 827
 828         if (v.xoffset < 0)
 829                 v.xoffset = 0;
 830         if (v.yoffset < 0)
 831                 v.yoffset = 0;
 832
 833         if (v.xoffset > v.xres_virtual - v.xres)
 834                 v.xoffset = v.xres_virtual - v.xres - 1;
 835
 836         if (v.yoffset > v.yres_virtual - v.yres)
 837                 v.yoffset = v.yres_virtual - v.yres - 1;
 838
 839         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
 840                           v.transp.offset = v.transp.length =
 841                           v.transp.msb_right = 0;
 842
 843         memcpy(var, &v, sizeof(v));
 844
 845         return 0;
 846 }
 847
 848
 849 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
 850                                  struct fb_info *info)
 851 {
 852         struct radeonfb_info *rinfo = info->par;
 853
 854         if ((var->xoffset + var->xres > var->xres_virtual)
 855             || (var->yoffset + var->yres > var->yres_virtual))
 856                return -EINVAL;
 857
 858         if (rinfo->asleep)
 859                 return 0;
 860
 861         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
 862                              * var->bits_per_pixel / 8) & ~7);
 863         return 0;
 864 }
 865
 866
 867 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
 868                            unsigned long arg, struct fb_info *info)
 869 {
 870         struct radeonfb_info *rinfo = info->par;
 871         unsigned int tmp;
 872         u32 value = 0;
 873         int rc;
 874
 875         switch (cmd) {
 876                 /*
 877                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
 878                  *        and do something better using 2nd CRTC instead of just hackish
 879                  *        routing to second output
 880                  */
 881                 case FBIO_RADEON_SET_MIRROR:
 882                         if (!rinfo->is_mobility)
 883                                 return -EINVAL;
 884
 885                         rc = get_user(value, (__u32*)arg);
 886
 887                         if (rc)
 888                                 return rc;
 889
 890                         if (value & 0x01) {
 891                                 tmp = INREG(LVDS_GEN_CNTL);
 892
 893                                 tmp |= (LVDS_ON | LVDS_BLON);
 894                         } else {
 895                                 tmp = INREG(LVDS_GEN_CNTL);
 896
 897                                 tmp &= ~(LVDS_ON | LVDS_BLON);
 898                         }
 899
 900                         OUTREG(LVDS_GEN_CNTL, tmp);
 901
 902                         if (value & 0x02) {
 903                                 tmp = INREG(CRTC_EXT_CNTL);
 904                                 tmp |= CRTC_CRT_ON;
 905
 906                                 mirror = 1;
 907                         } else {
 908                                 tmp = INREG(CRTC_EXT_CNTL);
 909                                 tmp &= ~CRTC_CRT_ON;
 910
 911                                 mirror = 0;
 912                         }
 913
 914                         OUTREG(CRTC_EXT_CNTL, tmp);
 915
 916                         break;
 917                 case FBIO_RADEON_GET_MIRROR:
 918                         if (!rinfo->is_mobility)
 919                                 return -EINVAL;
 920
 921                         tmp = INREG(LVDS_GEN_CNTL);
 922                         if ((LVDS_ON | LVDS_BLON) & tmp)
 923                                 value |= 0x01;
 924
 925                         tmp = INREG(CRTC_EXT_CNTL);
 926                         if (CRTC_CRT_ON & tmp)
 927                                 value |= 0x02;
 928
 929                         return put_user(value, (__u32*)arg);
 930                 default:
 931                         return -EINVAL;
 932         }
 933
 934         return -EINVAL;
 935 }
 936
 937
 938 static int radeon_screen_blank (struct radeonfb_info *rinfo, int blank)
 939 {
 940         u32 val = INREG(CRTC_EXT_CNTL);
 941         u32 val2 = 0;
 942
 943         if (rinfo->mon1_type == MT_LCD)
 944                 val2 = INREG(LVDS_GEN_CNTL) & ~LVDS_DISPLAY_DIS;
 945
 946         /* reset it */
 947         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
 948                  CRTC_VSYNC_DIS);
 949
 950         switch (blank) {
 951                 case VESA_NO_BLANKING:
 952                         break;
 953                 case VESA_VSYNC_SUSPEND:
 954                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
 955                         break;
 956                 case VESA_HSYNC_SUSPEND:
 957                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
 958                         break;
 959                 case VESA_POWERDOWN:
 960                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
 961                                 CRTC_HSYNC_DIS);
 962                         val2 |= (LVDS_DISPLAY_DIS);
 963                         break;
 964         }
 965
 966         switch (rinfo->mon1_type) {
 967                 case MT_LCD:
 968                         OUTREG(LVDS_GEN_CNTL, val2);
 969                         break;
 970                 case MT_CRT:
 971                 default:
 972                         OUTREG(CRTC_EXT_CNTL, val);
 973                         break;
 974         }
 975
 976         return 0;
 977 }
 978
 979 int radeonfb_blank (int blank, struct fb_info *info)
 980 {
 981         struct radeonfb_info *rinfo = info->par;
 982
 983         if (rinfo->asleep)
 984                 return 0;
 985
 986 #ifdef CONFIG_PMAC_BACKLIGHT
 987         if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && blank)
 988                 set_backlight_enable(0);
 989 #endif
 990
 991         radeon_screen_blank(rinfo, blank);
 992
 993 #ifdef CONFIG_PMAC_BACKLIGHT
 994         if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && !blank)
 995                 set_backlight_enable(1);
 996 #endif
 997
 998         return 0;
 999 }
1000
1001 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1002                              unsigned blue, unsigned transp, struct fb_info *info)
1003 {
1004         struct radeonfb_info *rinfo = info->par;
1005         u32 pindex;
1006         unsigned int i;
1007
1008         if (regno > 255)
1009                 return 1;
1010
1011         red >>= 8;
1012         green >>= 8;
1013         blue >>= 8;
1014         rinfo->palette[regno].red = red;
1015         rinfo->palette[regno].green = green;
1016         rinfo->palette[regno].blue = blue;
1017
1018         /* default */
1019         pindex = regno;
1020
1021         if (!rinfo->asleep) {
1022                 u32 dac_cntl2, vclk_cntl = 0;
1023
1024                 if (rinfo->is_mobility) {
1025                         vclk_cntl = INPLL(VCLK_ECP_CNTL);
1026                         OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1027                 }
1028
1029                 /* Make sure we are on first palette */
1030                 if (rinfo->has_CRTC2) {
1031                         dac_cntl2 = INREG(DAC_CNTL2);
1032                         dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1033                         OUTREG(DAC_CNTL2, dac_cntl2);
1034                 }
1035
1036                 if (rinfo->bpp == 16) {
1037                         pindex = regno * 8;
1038
1039                         if (rinfo->depth == 16 && regno > 63)
1040                                 return 1;
1041                         if (rinfo->depth == 15 && regno > 31)
1042                                 return 1;
1043
1044                         /* For 565, the green component is mixed one order below */
1045                         if (rinfo->depth == 16) {
1046                                 OUTREG(PALETTE_INDEX, pindex>>1);
1047                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1048                                         (green << 8) | (rinfo->palette[regno>>1].blue));
1049                                 green = rinfo->palette[regno<<1].green;
1050                         }
1051                 }
1052
1053                 if (rinfo->depth != 16 || regno < 32) {
1054                         OUTREG(PALETTE_INDEX, pindex);
1055                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1056                 }
1057                 if (rinfo->is_mobility)
1058                         OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1059         }
1060         if (regno < 16) {
1061                 u32 *pal = info->pseudo_palette;
1062                 switch (rinfo->depth) {
1063                 case 15:
1064                         pal[regno] = (regno << 10) | (regno << 5) | regno;
1065                         break;
1066                 case 16:
1067                         pal[regno] = (regno << 11) | (regno << 5) | regno;
1068                         break;
1069                 case 24:
1070                         pal[regno] = (regno << 16) | (regno << 8) | regno;
1071                         break;
1072                 case 32:
1073                         i = (regno << 8) | regno;
1074                         pal[regno] = (i << 16) | i;
1075                         break;
1076                 }
1077         }
1078         return 0;
1079 }
1080
1081
1082 static void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save)
1083 {
1084         /* CRTC regs */
1085         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1086         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1087         save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1088         save->dac_cntl = INREG(DAC_CNTL);
1089         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1090         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1091         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1092         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1093         save->crtc_pitch = INREG(CRTC_PITCH);
1094         save->surface_cntl = INREG(SURFACE_CNTL);
1095
1096         /* FP regs */
1097         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1098         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1099         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1100         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1101         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1102         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1103         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1104         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1105         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1106         save->tmds_crc = INREG(TMDS_CRC);       save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1107         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1108 }
1109
1110
1111 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1112 {
1113         int i;
1114
1115         /* Workaround from XFree */
1116         if (rinfo->is_mobility) {
1117                 /* A temporal workaround for the occational blanking on certain laptop panels.
1118                    This appears to related to the PLL divider registers (fail to lock?).
1119                    It occurs even when all dividers are the same with their old settings.
1120                    In this case we really don't need to fiddle with PLL registers.
1121                    By doing this we can avoid the blanking problem with some panels.
1122                 */
1123                 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1124                     (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1125                                           (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1126                         /* We still have to force a switch to PPLL div 3 thanks to
1127                          * an XFree86 driver bug which will switch it away in some cases
1128                          * even when using UseFDev */
1129                         OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1130                         return;
1131                 }
1132         }
1133
1134         /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1135         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1136
1137         /* Reset PPLL & enable atomic update */
1138         OUTPLLP(PPLL_CNTL,
1139                 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1140                 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1141
1142         /* Switch to PPLL div 3 */
1143         OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1144
1145         /* Set PPLL ref. div */
1146         if (rinfo->family == CHIP_FAMILY_R300 ||
1147             rinfo->family == CHIP_FAMILY_RS300 ||
1148             rinfo->family == CHIP_FAMILY_R350 ||
1149             rinfo->family == CHIP_FAMILY_RV350) {
1150                 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1151                         /* When restoring console mode, use saved PPLL_REF_DIV
1152                          * setting.
1153                          */
1154                         OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1155                 } else {
1156                         /* R300 uses ref_div_acc field as real ref divider */
1157                         OUTPLLP(PPLL_REF_DIV,
1158                                 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1159                                 ~R300_PPLL_REF_DIV_ACC_MASK);
1160                 }
1161         } else
1162                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1163
1164         /* Set PPLL divider 3 & post divider*/
1165         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1166         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1167
1168         /* Write update */
1169         while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1170                 ;
1171         OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1172
1173         /* Wait read update complete */
1174         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
1175            the cause yet, but this workaround will mask the problem for now.
1176            Other chips usually will pass at the very first test, so the
1177            workaround shouldn't have any effect on them. */
1178         for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1179                 ;
1180
1181         OUTPLL(HTOTAL_CNTL, 0);
1182
1183         /* Clear reset & atomic update */
1184         OUTPLLP(PPLL_CNTL, 0,
1185                 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1186
1187         /* We may want some locking ... oh well */
1188         msleep(5);
1189
1190         /* Switch back VCLK source to PPLL */
1191         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1192 }
1193
1194 /*
1195  * Timer function for delayed LVDS panel power up/down
1196  */
1197 static void radeon_lvds_timer_func(unsigned long data)
1198 {
1199         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1200
1201         OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1202         if (rinfo->pending_pixclks_cntl) {
1203                 OUTPLL(PIXCLKS_CNTL, rinfo->pending_pixclks_cntl);
1204                 rinfo->pending_pixclks_cntl = 0;
1205         }
1206 }
1207
1208 /*
1209  * Apply a video mode. This will apply the whole register set, including
1210  * the PLL registers, to the card
1211  */
1212 static void radeon_write_mode (struct radeonfb_info *rinfo,
1213                                struct radeon_regs *mode)
1214 {
1215         int i;
1216         int primary_mon = PRIMARY_MONITOR(rinfo);
1217
1218         if (nomodeset)
1219                 return;
1220
1221         del_timer_sync(&rinfo->lvds_timer);
1222
1223         radeon_screen_blank(rinfo, VESA_POWERDOWN);
1224
1225         for (i=0; i<10; i++)
1226                 OUTREG(common_regs[i].reg, common_regs[i].val);
1227
1228         /* Apply surface registers */
1229         for (i=0; i<8; i++) {
1230                 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1231                 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1232                 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1233         }
1234
1235         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1236         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1237                 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1238         OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1239         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1240         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1241         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1242         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1243         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1244         OUTREG(CRTC_OFFSET, 0);
1245         OUTREG(CRTC_OFFSET_CNTL, 0);
1246         OUTREG(CRTC_PITCH, mode->crtc_pitch);
1247         OUTREG(SURFACE_CNTL, mode->surface_cntl);
1248
1249         radeon_write_pll_regs(rinfo, mode);
1250
1251         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1252                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1253                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1254                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1255                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1256                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1257                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1258                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1259                 OUTREG(TMDS_CRC, mode->tmds_crc);
1260                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1261
1262                 if (primary_mon == MT_LCD) {
1263                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
1264
1265                         /* HACK: The backlight control code may have modified init_state.lvds_gen_cntl,
1266                          * so we update ourselves
1267                          */
1268                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
1269                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
1270
1271                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
1272                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
1273                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
1274                         } else {
1275                                 rinfo->pending_pixclks_cntl = INPLL(PIXCLKS_CNTL);
1276                                 if (rinfo->is_mobility || rinfo->is_IGP)
1277                                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1278                                 if (!(tmp & (LVDS_ON | LVDS_BLON)))
1279                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl | LVDS_BLON);
1280                                 rinfo->pending_lvds_gen_cntl = mode->lvds_gen_cntl;
1281                                 mod_timer(&rinfo->lvds_timer,
1282                                           jiffies + MS_TO_HZ(rinfo->panel_info.pwr_delay));
1283                         }
1284                 }
1285         }
1286
1287         RTRACE("lvds_gen_cntl: %08x\n", INREG(LVDS_GEN_CNTL));
1288
1289         radeon_screen_blank(rinfo, VESA_NO_BLANKING);
1290
1291         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1292
1293         return;
1294 }
1295
1296 /*
1297  * Calculate the PLL values for a given mode
1298  */
1299 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1300                                  unsigned long freq)
1301 {
1302         const struct {
1303                 int divider;
1304                 int bitvalue;
1305         } *post_div,
1306           post_divs[] = {
1307                 { 1,  0 },
1308                 { 2,  1 },
1309                 { 4,  2 },
1310                 { 8,  3 },
1311                 { 3,  4 },
1312                 { 16, 5 },
1313                 { 6,  6 },
1314                 { 12, 7 },
1315                 { 0,  0 },
1316         };
1317         int fb_div, pll_output_freq = 0;
1318         int uses_dvo = 0;
1319
1320         /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1321          * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1322          * recent than an r(v)100...
1323          */
1324 #if 0
1325         /* XXX I had reports of flicker happening with the cinema display
1326          * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1327          * this case. This could just be a bandwidth calculation issue, I
1328          * haven't implemented the bandwidth code yet, but in the meantime,
1329          * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1330          * I haven't seen a case were were absolutely needed an odd PLL
1331          * divider. I'll find a better fix once I have more infos on the
1332          * real cause of the problem.
1333          */
1334         while (rinfo->has_CRTC2) {
1335                 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1336                 u32 disp_output_cntl;
1337                 int source;
1338
1339                 /* FP2 path not enabled */
1340                 if ((fp2_gen_cntl & FP2_ON) == 0)
1341                         break;
1342                 /* Not all chip revs have the same format for this register,
1343                  * extract the source selection
1344                  */
1345                 if (rinfo->family == CHIP_FAMILY_R200 ||
1346                     rinfo->family == CHIP_FAMILY_R300 ||
1347                     rinfo->family == CHIP_FAMILY_R350 ||
1348                     rinfo->family == CHIP_FAMILY_RV350) {
1349                         source = (fp2_gen_cntl >> 10) & 0x3;
1350                         /* sourced from transform unit, check for transform unit
1351                          * own source
1352                          */
1353                         if (source == 3) {
1354                                 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1355                                 source = (disp_output_cntl >> 12) & 0x3;
1356                         }
1357                 } else
1358                         source = (fp2_gen_cntl >> 13) & 0x1;
1359                 /* sourced from CRTC2 -> exit */
1360                 if (source == 1)
1361                         break;
1362
1363                 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1364                 uses_dvo = 1;
1365                 break;
1366         }
1367 #else
1368         uses_dvo = 1;
1369 #endif
1370         if (freq > rinfo->pll.ppll_max)
1371                 freq = rinfo->pll.ppll_max;
1372         if (freq*12 < rinfo->pll.ppll_min)
1373                 freq = rinfo->pll.ppll_min / 12;
1374
1375         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1376                 pll_output_freq = post_div->divider * freq;
1377                 /* If we output to the DVO port (external TMDS), we don't allow an
1378                  * odd PLL divider as those aren't supported on this path
1379                  */
1380                 if (uses_dvo && (post_div->divider & 1))
1381                         continue;
1382                 if (pll_output_freq >= rinfo->pll.ppll_min  &&
1383                     pll_output_freq <= rinfo->pll.ppll_max)
1384                         break;
1385         }
1386
1387         fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1388                                   rinfo->pll.ref_clk);
1389         regs->ppll_ref_div = rinfo->pll.ref_div;
1390         regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1391
1392         RTRACE("post div = 0x%x\n", post_div->bitvalue);
1393         RTRACE("fb_div = 0x%x\n", fb_div);
1394         RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1395 }
1396
1397 int radeonfb_set_par(struct fb_info *info)
1398 {
1399         struct radeonfb_info *rinfo = info->par;
1400         struct fb_var_screeninfo *mode = &info->var;
1401         struct radeon_regs *newmode;
1402         int hTotal, vTotal, hSyncStart, hSyncEnd,
1403             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1404         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1405         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1406         u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1407         int i, freq;
1408         int format = 0;
1409         int nopllcalc = 0;
1410         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1411         int primary_mon = PRIMARY_MONITOR(rinfo);
1412         int depth = var_to_depth(mode);
1413
1414         newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1415         if (!newmode)
1416                 return -ENOMEM;
1417
1418         /* We always want engine to be idle on a mode switch, even
1419          * if we won't actually change the mode
1420          */
1421         radeon_engine_idle();
1422
1423         hSyncStart = mode->xres + mode->right_margin;
1424         hSyncEnd = hSyncStart + mode->hsync_len;
1425         hTotal = hSyncEnd + mode->left_margin;
1426
1427         vSyncStart = mode->yres + mode->lower_margin;
1428         vSyncEnd = vSyncStart + mode->vsync_len;
1429         vTotal = vSyncEnd + mode->upper_margin;
1430         pixClock = mode->pixclock;
1431
1432         sync = mode->sync;
1433         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1434         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1435
1436         if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1437                 if (rinfo->panel_info.xres < mode->xres)
1438                         mode->xres = rinfo->panel_info.xres;
1439                 if (rinfo->panel_info.yres < mode->yres)
1440                         mode->yres = rinfo->panel_info.yres;
1441
1442                 hTotal = mode->xres + rinfo->panel_info.hblank;
1443                 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1444                 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1445
1446                 vTotal = mode->yres + rinfo->panel_info.vblank;
1447                 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1448                 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1449
1450                 h_sync_pol = !rinfo->panel_info.hAct_high;
1451                 v_sync_pol = !rinfo->panel_info.vAct_high;
1452
1453                 pixClock = 100000000 / rinfo->panel_info.clock;
1454
1455                 if (rinfo->panel_info.use_bios_dividers) {
1456                         nopllcalc = 1;
1457                         newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1458                                 (rinfo->panel_info.post_divider << 16);
1459                         newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1460                 }
1461         }
1462         dotClock = 1000000000 / pixClock;
1463         freq = dotClock / 10; /* x100 */
1464
1465         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1466                 hSyncStart, hSyncEnd, hTotal);
1467         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1468                 vSyncStart, vSyncEnd, vTotal);
1469
1470         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1471         vsync_wid = vSyncEnd - vSyncStart;
1472         if (hsync_wid == 0)
1473                 hsync_wid = 1;
1474         else if (hsync_wid > 0x3f)      /* max */
1475                 hsync_wid = 0x3f;
1476
1477         if (vsync_wid == 0)
1478                 vsync_wid = 1;
1479         else if (vsync_wid > 0x1f)      /* max */
1480                 vsync_wid = 0x1f;
1481
1482         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1483         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1484
1485         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1486
1487         format = radeon_get_dstbpp(depth);
1488         bytpp = mode->bits_per_pixel >> 3;
1489
1490         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1491                 hsync_fudge = hsync_fudge_fp[format-1];
1492         else
1493                 hsync_fudge = hsync_adj_tab[format-1];
1494
1495         hsync_start = hSyncStart - 8 + hsync_fudge;
1496
1497         newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1498                                 (format << 8);
1499
1500         /* Clear auto-center etc... */
1501         newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1502         newmode->crtc_more_cntl &= 0xfffffff0;
1503
1504         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1505                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1506                 if (mirror)
1507                         newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1508
1509                 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1510                                            CRTC_INTERLACE_EN);
1511         } else {
1512                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1513                                         CRTC_CRT_ON;
1514         }
1515
1516         newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1517                            DAC_8BIT_EN;
1518
1519         newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1520                                      (((mode->xres / 8) - 1) << 16));
1521
1522         newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1523                                         (hsync_wid << 16) | (h_sync_pol << 23));
1524
1525         newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1526                                     ((mode->yres - 1) << 16);
1527
1528         newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1529                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1530
1531         if (!radeon_accel_disabled()) {
1532                 /* We first calculate the engine pitch */
1533                 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1534                                 & ~(0x3f)) >> 6;
1535
1536                 /* Then, re-multiply it to get the CRTC pitch */
1537                 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1538         } else
1539                 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1540
1541         newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1542
1543         /*
1544          * It looks like recent chips have a problem with SURFACE_CNTL,
1545          * setting SURF_TRANSLATION_DIS completely disables the
1546          * swapper as well, so we leave it unset now.
1547          */
1548         newmode->surface_cntl = 0;
1549
1550 #if defined(__BIG_ENDIAN)
1551
1552         /* Setup swapping on both apertures, though we currently
1553          * only use aperture 0, enabling swapper on aperture 1
1554          * won't harm
1555          */
1556         switch (mode->bits_per_pixel) {
1557                 case 16:
1558                         newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1559                         newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1560                         break;
1561                 case 24:
1562                 case 32:
1563                         newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1564                         newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1565                         break;
1566         }
1567 #endif
1568
1569         /* Clear surface registers */
1570         for (i=0; i<8; i++) {
1571                 newmode->surf_lower_bound[i] = 0;
1572                 newmode->surf_upper_bound[i] = 0x1f;
1573                 newmode->surf_info[i] = 0;
1574         }
1575
1576         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1577                 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1578         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1579                 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1580
1581         rinfo->bpp = mode->bits_per_pixel;
1582         rinfo->depth = depth;
1583
1584         RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1585         RTRACE("freq = %lu\n", (unsigned long)freq);
1586
1587         if (!nopllcalc)
1588                 radeon_calc_pll_regs(rinfo, newmode, freq);
1589
1590         newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1591
1592         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1593                 unsigned int hRatio, vRatio;
1594
1595                 if (mode->xres > rinfo->panel_info.xres)
1596                         mode->xres = rinfo->panel_info.xres;
1597                 if (mode->yres > rinfo->panel_info.yres)
1598                         mode->yres = rinfo->panel_info.yres;
1599
1600                 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1601                                            << HORZ_PANEL_SHIFT);
1602                 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1603                                            << VERT_PANEL_SHIFT);
1604
1605                 if (mode->xres != rinfo->panel_info.xres) {
1606                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1607                                            rinfo->panel_info.xres);
1608                         newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1609                                                    (newmode->fp_horz_stretch &
1610                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1611                                                      HORZ_AUTO_RATIO_INC)));
1612                         newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1613                                                     HORZ_STRETCH_ENABLE);
1614                 }
1615                 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1616
1617                 if (mode->yres != rinfo->panel_info.yres) {
1618                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1619                                            rinfo->panel_info.yres);
1620                         newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1621                                                    (newmode->fp_vert_stretch &
1622                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1623                         newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1624                                                     VERT_STRETCH_ENABLE);
1625                 }
1626                 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1627
1628                 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1629                                        ~(FP_SEL_CRTC2 |
1630                                          FP_RMX_HVSYNC_CONTROL_EN |
1631                                          FP_DFP_SYNC_SEL |
1632                                          FP_CRT_SYNC_SEL |
1633                                          FP_CRTC_LOCK_8DOT |
1634                                          FP_USE_SHADOW_EN |
1635                                          FP_CRTC_USE_SHADOW_VEND |
1636                                          FP_CRT_SYNC_ALT));
1637
1638                 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1639                                         FP_CRTC_DONT_SHADOW_HEND);
1640
1641                 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1642                 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1643                 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1644                 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1645
1646                 if (primary_mon == MT_LCD) {
1647                         newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1648                         newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1649                 } else {
1650                         /* DFP */
1651                         newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1652                         newmode->tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | TMDS_ICHCSEL) &
1653                                                          ~(TMDS_PLLRST);
1654                         /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1655                         if ((rinfo->family == CHIP_FAMILY_R300) ||
1656                             (rinfo->family == CHIP_FAMILY_R350) ||
1657                             (rinfo->family == CHIP_FAMILY_RV350) ||
1658                             (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1659                                 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1660                         else
1661                                 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1662                         newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1663                 }
1664
1665                 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1666                                 (((mode->xres / 8) - 1) << 16));
1667                 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1668                                 ((mode->yres - 1) << 16);
1669                 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1670                                 (hsync_wid << 16) | (h_sync_pol << 23));
1671                 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1672                                 (vsync_wid << 16) | (v_sync_pol  << 23));
1673         }
1674
1675         /* do it! */
1676         if (!rinfo->asleep) {
1677                 radeon_write_mode (rinfo, newmode);
1678                 /* (re)initialize the engine */
1679                 if (!radeon_accel_disabled())
1680                         radeonfb_engine_init (rinfo);
1681
1682         }
1683         /* Update fix */
1684         if (!radeon_accel_disabled())
1685                 info->fix.line_length = rinfo->pitch*64;
1686         else
1687                 info->fix.line_length = mode->xres_virtual
1688                         * ((mode->bits_per_pixel + 1) / 8);
1689         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1690                 : FB_VISUAL_DIRECTCOLOR;
1691
1692 #ifdef CONFIG_BOOTX_TEXT
1693         /* Update debug text engine */
1694         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1695                              rinfo->depth, info->fix.line_length);
1696 #endif
1697
1698         kfree(newmode);
1699         return 0;
1700 }
1701
1702
1703
1704 static ssize_t radeonfb_read(struct file *file, char *buf, size_t count, loff_t *ppos)
1705 {
1706         unsigned long p = *ppos;
1707         struct inode *inode = file->f_dentry->d_inode;
1708         int fbidx = iminor(inode);
1709         struct fb_info *info = registered_fb[fbidx];
1710         struct radeonfb_info *rinfo = info->par;
1711
1712         if (p >= rinfo->mapped_vram)
1713             return 0;
1714         if (count >= rinfo->mapped_vram)
1715             count = rinfo->mapped_vram;
1716         if (count + p > rinfo->mapped_vram)
1717                 count = rinfo->mapped_vram - p;
1718         radeonfb_sync(info);
1719         if (count) {
1720             char *base_addr;
1721
1722             base_addr = info->screen_base;
1723             count -= copy_to_user(buf, base_addr+p, count);
1724             if (!count)
1725                 return -EFAULT;
1726             *ppos += count;
1727         }
1728         return count;
1729 }
1730
1731 static ssize_t radeonfb_write(struct file *file, const char *buf, size_t count,
1732                               loff_t *ppos)
1733 {
1734         unsigned long p = *ppos;
1735         struct inode *inode = file->f_dentry->d_inode;
1736         int fbidx = iminor(inode);
1737         struct fb_info *info = registered_fb[fbidx];
1738         struct radeonfb_info *rinfo = info->par;
1739         int err;
1740
1741         if (p > rinfo->mapped_vram)
1742             return -ENOSPC;
1743         if (count >= rinfo->mapped_vram)
1744             count = rinfo->mapped_vram;
1745         err = 0;
1746         if (count + p > rinfo->mapped_vram) {
1747             count = rinfo->mapped_vram - p;
1748             err = -ENOSPC;
1749         }
1750         radeonfb_sync(info);
1751         if (count) {
1752             char *base_addr;
1753
1754             base_addr = info->screen_base;
1755             count -= copy_from_user(base_addr+p, buf, count);
1756             *ppos += count;
1757             err = -EFAULT;
1758         }
1759         if (count)
1760                 return count;
1761         return err;
1762 }
1763
1764
1765 static struct fb_ops radeonfb_ops = {
1766         .owner                  = THIS_MODULE,
1767         .fb_check_var           = radeonfb_check_var,
1768         .fb_set_par             = radeonfb_set_par,
1769         .fb_setcolreg           = radeonfb_setcolreg,
1770         .fb_pan_display         = radeonfb_pan_display,
1771         .fb_blank               = radeonfb_blank,
1772         .fb_ioctl               = radeonfb_ioctl,
1773         .fb_sync                = radeonfb_sync,
1774         .fb_fillrect            = radeonfb_fillrect,
1775         .fb_copyarea            = radeonfb_copyarea,
1776         .fb_imageblit           = radeonfb_imageblit,
1777         .fb_read                = radeonfb_read,
1778         .fb_write               = radeonfb_write,
1779         .fb_cursor              = soft_cursor,
1780 };
1781
1782
1783 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1784 {
1785         struct fb_info *info = rinfo->info;
1786
1787         info->currcon = -1;
1788         info->par = rinfo;
1789         info->pseudo_palette = rinfo->pseudo_palette;
1790         info->flags = FBINFO_FLAG_DEFAULT;
1791         info->fbops = &radeonfb_ops;
1792         info->screen_base = (char *)rinfo->fb_base;
1793
1794         /* Fill fix common fields */
1795         strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1796         info->fix.smem_start = rinfo->fb_base_phys;
1797         info->fix.smem_len = rinfo->video_ram;
1798         info->fix.type = FB_TYPE_PACKED_PIXELS;
1799         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1800         info->fix.xpanstep = 8;
1801         info->fix.ypanstep = 1;
1802         info->fix.ywrapstep = 0;
1803         info->fix.type_aux = 0;
1804         info->fix.mmio_start = rinfo->mmio_base_phys;
1805         info->fix.mmio_len = RADEON_REGSIZE;
1806         if (radeon_accel_disabled())
1807                 info->fix.accel = FB_ACCEL_NONE;
1808         else
1809                 info->fix.accel = FB_ACCEL_ATI_RADEON;
1810
1811         fb_alloc_cmap(&info->cmap, 256, 0);
1812
1813         if (radeon_accel_disabled())
1814                 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1815         else
1816                 info->var.accel_flags |= FB_ACCELF_TEXT;
1817
1818         return 0;
1819 }
1820
1821
1822 #ifdef CONFIG_PMAC_BACKLIGHT
1823
1824 /* TODO: Dbl check these tables, we don't go up to full ON backlight
1825  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1826  * having some more official numbers from ATI
1827  */
1828 static int backlight_conv_m6[] = {
1829         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1830         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1831 };
1832 static int backlight_conv_m7[] = {
1833         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1834         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1835 };
1836
1837 #define BACKLIGHT_LVDS_OFF
1838 #undef BACKLIGHT_DAC_OFF
1839
1840 /* We turn off the LCD completely instead of just dimming the backlight.
1841  * This provides some greater power saving and the display is useless
1842  * without backlight anyway.
1843  */
1844 static int radeon_set_backlight_enable(int on, int level, void *data)
1845 {
1846         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1847         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1848         unsigned long tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1849         int* conv_table;
1850
1851         if (rinfo->mon1_type != MT_LCD)
1852                 return 0;
1853
1854         /* Pardon me for that hack... maybe some day we can figure
1855          * out in what direction backlight should work on a given
1856          * panel ?
1857          */
1858         if ((rinfo->family == CHIP_FAMILY_RV200 ||
1859              rinfo->family == CHIP_FAMILY_RV250 ||
1860              rinfo->family == CHIP_FAMILY_RV280 ||
1861              rinfo->family == CHIP_FAMILY_RV350) &&
1862             !machine_is_compatible("PowerBook4,3") &&
1863             !machine_is_compatible("PowerBook6,3") &&
1864             !machine_is_compatible("PowerBook6,5"))
1865                 conv_table = backlight_conv_m7;
1866         else
1867                 conv_table = backlight_conv_m6;
1868
1869         del_timer_sync(&rinfo->lvds_timer);
1870
1871         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
1872         if (on && (level > BACKLIGHT_OFF)) {
1873                 lvds_gen_cntl |= LVDS_DIGON;
1874                 if (!(lvds_gen_cntl & LVDS_ON)) {
1875                         lvds_gen_cntl &= ~LVDS_BLON;
1876                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1877                         (void)INREG(LVDS_GEN_CNTL);
1878                         mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1879                         lvds_gen_cntl |= LVDS_BLON;
1880                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1881                 }
1882                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1883                 lvds_gen_cntl |= (conv_table[level] <<
1884                                   LVDS_BL_MOD_LEVEL_SHIFT);
1885                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
1886                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1887         } else {
1888                 /* Asic bug, when turning off LVDS_ON, we have to make sure
1889                    RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1890                 */
1891                 if (rinfo->is_mobility || rinfo->is_IGP)
1892                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1893                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1894                 lvds_gen_cntl |= (conv_table[0] <<
1895                                   LVDS_BL_MOD_LEVEL_SHIFT);
1896                 lvds_gen_cntl |= LVDS_DISPLAY_DIS | LVDS_BLON;
1897                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1898                 mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1899                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
1900         }
1901
1902         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1903         if (rinfo->is_mobility || rinfo->is_IGP)
1904                 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
1905         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1906         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
1907
1908         return 0;
1909 }
1910
1911
1912 static int radeon_set_backlight_level(int level, void *data)
1913 {
1914         return radeon_set_backlight_enable(1, level, data);
1915 }
1916 #endif /* CONFIG_PMAC_BACKLIGHT */
1917
1918
1919 /*
1920  * This reconfigure the card's internal memory map. In theory, we'd like
1921  * to setup the card's memory at the same address as it's PCI bus address,
1922  * and the AGP aperture right after that so that system RAM on 32 bits
1923  * machines at least, is directly accessible. However, doing so would
1924  * conflict with the current XFree drivers...
1925  * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1926  * on the proper way to set this up and duplicate this here. In the meantime,
1927  * I put the card's memory at 0 in card space and AGP at some random high
1928  * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1929  */
1930 #ifdef CONFIG_PPC_OF
1931 #undef SET_MC_FB_FROM_APERTURE
1932 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1933 {
1934         u32 save_crtc_gen_cntl, save_crtc2_gen_cntl;
1935         u32 save_crtc_ext_cntl;
1936         u32 aper_base, aper_size;
1937         u32 agp_base;
1938
1939         /* First, we disable display to avoid interfering */
1940         if (rinfo->has_CRTC2) {
1941                 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1942                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1943         }
1944         save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1945         save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1946
1947         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1948         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1949         mdelay(100);
1950
1951         aper_base = INREG(CONFIG_APER_0_BASE);
1952         aper_size = INREG(CONFIG_APER_SIZE);
1953
1954 #ifdef SET_MC_FB_FROM_APERTURE
1955         /* Set framebuffer to be at the same address as set in PCI BAR */
1956         OUTREG(MC_FB_LOCATION,
1957                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1958         rinfo->fb_local_base = aper_base;
1959 #else
1960         OUTREG(MC_FB_LOCATION, 0x7fff0000);
1961         rinfo->fb_local_base = 0;
1962 #endif
1963         agp_base = aper_base + aper_size;
1964         if (agp_base & 0xf0000000)
1965                 agp_base = (aper_base | 0x0fffffff) + 1;
1966
1967         /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1968          * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1969          * always the case on PPCs afaik.
1970          */
1971 #ifdef SET_MC_FB_FROM_APERTURE
1972         OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1973 #else
1974         OUTREG(MC_AGP_LOCATION, 0xffffe000);
1975 #endif
1976
1977         /* Fixup the display base addresses & engine offsets while we
1978          * are at it as well
1979          */
1980 #ifdef SET_MC_FB_FROM_APERTURE
1981         OUTREG(DISPLAY_BASE_ADDR, aper_base);
1982         if (rinfo->has_CRTC2)
1983                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1984 #else
1985         OUTREG(DISPLAY_BASE_ADDR, 0);
1986         if (rinfo->has_CRTC2)
1987                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1988 #endif
1989         mdelay(100);
1990
1991         /* Restore display settings */
1992         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1993         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1994         if (rinfo->has_CRTC2)
1995                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1996
1997         RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1998                 aper_base,
1999                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2000                 0xffff0000 | (agp_base >> 16));
2001 }
2002 #endif /* CONFIG_PPC_OF */
2003
2004
2005 /*
2006  * Sysfs
2007  */
2008
2009 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2010 {
2011         if (off > EDID_LENGTH)
2012                 return 0;
2013
2014         if (off + count > EDID_LENGTH)
2015                 count = EDID_LENGTH - off;
2016
2017         memcpy(buf, edid + off, count);
2018
2019         return count;
2020 }
2021
2022
2023 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2024 {
2025         struct device *dev = container_of(kobj, struct device, kobj);
2026         struct pci_dev *pdev = to_pci_dev(dev);
2027         struct fb_info *info = pci_get_drvdata(pdev);
2028         struct radeonfb_info *rinfo = info->par;
2029
2030         return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2031 }
2032
2033
2034 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2035 {
2036         struct device *dev = container_of(kobj, struct device, kobj);
2037         struct pci_dev *pdev = to_pci_dev(dev);
2038         struct fb_info *info = pci_get_drvdata(pdev);
2039         struct radeonfb_info *rinfo = info->par;
2040
2041         return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2042 }
2043
2044 static struct bin_attribute edid1_attr = {
2045         .attr   = {
2046                 .name   = "edid1",
2047                 .owner  = THIS_MODULE,
2048                 .mode   = 0444,
2049         },
2050         .size   = EDID_LENGTH,
2051         .read   = radeon_show_edid1,
2052 };
2053
2054 static struct bin_attribute edid2_attr = {
2055         .attr   = {
2056                 .name   = "edid2",
2057                 .owner  = THIS_MODULE,
2058                 .mode   = 0444,
2059         },
2060         .size   = EDID_LENGTH,
2061         .read   = radeon_show_edid2,
2062 };
2063
2064
2065 static int radeonfb_pci_register (struct pci_dev *pdev,
2066                                   const struct pci_device_id *ent)
2067 {
2068         struct fb_info *info;
2069         struct radeonfb_info *rinfo;
2070         u32 tmp;
2071
2072         RTRACE("radeonfb_pci_register BEGIN\n");
2073
2074         /* Enable device in PCI config */
2075         if (pci_enable_device(pdev) != 0) {
2076                 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2077                 return -ENODEV;
2078         }
2079
2080         info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2081         if (!info) {
2082                 printk (KERN_ERR "radeonfb: could not allocate memory\n");
2083                 return -ENODEV;
2084         }
2085         rinfo = info->par;
2086         rinfo->info = info;
2087         rinfo->pdev = pdev;
2088
2089         spin_lock_init(&rinfo->reg_lock);
2090         init_timer(&rinfo->lvds_timer);
2091         rinfo->lvds_timer.function = radeon_lvds_timer_func;
2092         rinfo->lvds_timer.data = (unsigned long)rinfo;
2093
2094         strcpy(rinfo->name, "ATI Radeon XX ");
2095         rinfo->name[11] = ent->device >> 8;
2096         rinfo->name[12] = ent->device & 0xFF;
2097         rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2098         rinfo->chipset = pdev->device;
2099         rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2100         rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2101         rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2102
2103         /* Set base addrs */
2104         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2105         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2106
2107         /* request the mem regions */
2108         if (!request_mem_region (rinfo->fb_base_phys,
2109                                  pci_resource_len(pdev, 0), "radeonfb")) {
2110                 printk (KERN_ERR "radeonfb: cannot reserve FB region\n");
2111                 goto free_rinfo;
2112         }
2113
2114         if (!request_mem_region (rinfo->mmio_base_phys,
2115                                  pci_resource_len(pdev, 2), "radeonfb")) {
2116                 printk (KERN_ERR "radeonfb: cannot reserve MMIO region\n");
2117                 goto release_fb;
2118         }
2119
2120         /* map the regions */
2121         rinfo->mmio_base = (unsigned long) ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2122         if (!rinfo->mmio_base) {
2123                 printk (KERN_ERR "radeonfb: cannot map MMIO\n");
2124                 goto release_mmio;
2125         }
2126
2127         /* On PPC, the firmware sets up a memory mapping that tends
2128          * to cause lockups when enabling the engine. We reconfigure
2129          * the card internal memory mappings properly
2130          */
2131 #ifdef CONFIG_PPC_OF
2132         fixup_memory_mappings(rinfo);
2133 #else
2134         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2135 #endif /* CONFIG_PPC_OF */
2136
2137         /* framebuffer size */
2138         if ((rinfo->family == CHIP_FAMILY_RS100) ||
2139             (rinfo->family == CHIP_FAMILY_RS200) ||
2140             (rinfo->family == CHIP_FAMILY_RS300)) {
2141           u32 tom = INREG(NB_TOM);
2142           tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2143
2144           OUTREG(MC_FB_LOCATION, tom);
2145           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2146           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2147           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2148
2149           /* This is supposed to fix the crtc2 noise problem. */
2150           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2151
2152           if ((rinfo->family == CHIP_FAMILY_RS100) ||
2153               (rinfo->family == CHIP_FAMILY_RS200)) {
2154              /* This is to workaround the asic bug for RMX, some versions
2155                 of BIOS dosen't have this register initialized correctly.
2156              */
2157              OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2158                      ~CRTC_H_CUTOFF_ACTIVE_EN);
2159           }
2160         } else {
2161           tmp = INREG(CONFIG_MEMSIZE);
2162         }
2163
2164         /* mem size is bits [28:0], mask off the rest */
2165         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2166
2167         /* ram type */
2168         tmp = INREG(MEM_SDRAM_MODE_REG);
2169         switch ((MEM_CFG_TYPE & tmp) >> 30) {
2170         case 0:
2171                 /* SDR SGRAM (2:1) */
2172                 strcpy(rinfo->ram_type, "SDR SGRAM");
2173                 rinfo->ram.ml = 4;
2174                 rinfo->ram.mb = 4;
2175                 rinfo->ram.trcd = 1;
2176                 rinfo->ram.trp = 2;
2177                 rinfo->ram.twr = 1;
2178                 rinfo->ram.cl = 2;
2179                 rinfo->ram.loop_latency = 16;
2180                 rinfo->ram.rloop = 16;
2181                 break;
2182         case 1:
2183                 /* DDR SGRAM */
2184                 strcpy(rinfo->ram_type, "DDR SGRAM");
2185                 rinfo->ram.ml = 4;
2186                 rinfo->ram.mb = 4;
2187                 rinfo->ram.trcd = 3;
2188                 rinfo->ram.trp = 3;
2189                 rinfo->ram.twr = 2;
2190                 rinfo->ram.cl = 3;
2191                 rinfo->ram.tr2w = 1;
2192                 rinfo->ram.loop_latency = 16;
2193                 rinfo->ram.rloop = 16;
2194                 break;
2195         default:
2196                 /* 64-bit SDR SGRAM */
2197                 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2198                 rinfo->ram.ml = 4;
2199                 rinfo->ram.mb = 8;
2200                 rinfo->ram.trcd = 3;
2201                 rinfo->ram.trp = 3;
2202                 rinfo->ram.twr = 1;
2203                 rinfo->ram.cl = 3;
2204                 rinfo->ram.tr2w = 1;
2205                 rinfo->ram.loop_latency = 17;
2206                 rinfo->ram.rloop = 17;
2207                 break;
2208         }
2209
2210         /*
2211          * Hack to get around some busted production M6's
2212          * reporting no ram
2213          */
2214         if (rinfo->video_ram == 0) {
2215                 switch (pdev->device) {
2216                 case PCI_CHIP_RADEON_LY:
2217                 case PCI_CHIP_RADEON_LZ:
2218                         rinfo->video_ram = 8192 * 1024;
2219                         break;
2220                 default:
2221                         break;
2222                 }
2223         }
2224
2225         RTRACE("radeonfb: probed %s %ldk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2226
2227         rinfo->mapped_vram = MAX_MAPPED_VRAM;
2228         if (rinfo->video_ram < rinfo->mapped_vram)
2229                 rinfo->mapped_vram = rinfo->video_ram;
2230         for (;;) {
2231                 rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys,
2232                                                           rinfo->mapped_vram);
2233                 if (rinfo->fb_base == 0 && rinfo->mapped_vram > MIN_MAPPED_VRAM) {
2234                         rinfo->mapped_vram /= 2;
2235                         continue;
2236                 }
2237                 memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
2238                 break;
2239         }
2240
2241         if (!rinfo->fb_base) {
2242                 printk (KERN_ERR "radeonfb: cannot map FB\n");
2243                 goto unmap_rom;
2244         }
2245
2246         RTRACE("radeonfb: mapped %ldk videoram\n", rinfo->mapped_vram/1024);
2247
2248
2249         /* Argh. Scary arch !!! */
2250 #ifdef CONFIG_PPC64
2251         rinfo->fb_base = IO_TOKEN_TO_ADDR(rinfo->fb_base);
2252 #endif
2253
2254         /*
2255          * Check for required workaround for PLL accesses
2256          */
2257         rinfo->R300_cg_workaround = (rinfo->family == CHIP_FAMILY_R300 &&
2258                                      (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2259                                      == CFG_ATI_REV_A11);
2260
2261         /*
2262          * Map the BIOS ROM if any and retreive PLL parameters from
2263          * either BIOS or Open Firmware
2264          */
2265         radeon_map_ROM(rinfo, pdev);
2266
2267         /*
2268          * On x86, the primary display on laptop may have it's BIOS
2269          * ROM elsewhere, try to locate it at the legacy memory hole.
2270          * We probably need to make sure this is the primary dispay,
2271          * but that is difficult without some arch support.
2272          */
2273 #ifdef __i386__
2274         if (rinfo->bios_seg == NULL)
2275                 radeon_find_mem_vbios(rinfo);
2276 #endif /* __i386__ */
2277
2278         /* Get informations about the board's PLL */
2279         radeon_get_pllinfo(rinfo);
2280
2281 #ifdef CONFIG_FB_RADEON_I2C
2282         /* Register I2C bus */
2283         radeon_create_i2c_busses(rinfo);
2284 #endif
2285
2286         /* set all the vital stuff */
2287         radeon_set_fbinfo (rinfo);
2288
2289         /* Probe screen types */
2290         radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2291
2292         /* Build mode list, check out panel native model */
2293         radeon_check_modes(rinfo, mode_option);
2294
2295         /* Register some sysfs stuff (should be done better) */
2296         if (rinfo->mon1_EDID)
2297                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2298         if (rinfo->mon2_EDID)
2299                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2300
2301         /* save current mode regs before we switch into the new one
2302          * so we can restore this upon __exit
2303          */
2304         radeon_save_state (rinfo, &rinfo->init_state);
2305
2306         pci_set_drvdata(pdev, info);
2307
2308         /* Enable PM on mobility chips */
2309         if (rinfo->is_mobility) {
2310                 /* Find PM registers in config space */
2311                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2312                 /* Enable dynamic PM of chip clocks */
2313                 radeon_pm_enable_dynamic_mode(rinfo);
2314                 printk("radeonfb: Power Management enabled for Mobility chipsets\n");
2315         }
2316
2317         if (register_framebuffer(info) < 0) {
2318                 printk (KERN_ERR "radeonfb: could not register framebuffer\n");
2319                 goto unmap_fb;
2320         }
2321
2322 #ifdef CONFIG_MTRR
2323         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2324                                                  rinfo->video_ram,
2325                                                  MTRR_TYPE_WRCOMB, 1);
2326 #endif
2327
2328 #ifdef CONFIG_PMAC_BACKLIGHT
2329         if (rinfo->mon1_type == MT_LCD) {
2330                 register_backlight_controller(&radeon_backlight_controller,
2331                                               rinfo, "ati");
2332                 register_backlight_controller(&radeon_backlight_controller,
2333                                               rinfo, "mnca");
2334         }
2335 #endif
2336
2337         printk ("radeonfb: %s %s %ld MB\n", rinfo->name, rinfo->ram_type,
2338                 (rinfo->video_ram/(1024*1024)));
2339
2340         if (rinfo->bios_seg)
2341                 radeon_unmap_ROM(rinfo, pdev);
2342         RTRACE("radeonfb_pci_register END\n");
2343
2344         return 0;
2345 unmap_fb:
2346         iounmap ((void*)rinfo->fb_base);
2347 unmap_rom:
2348         if (rinfo->mon1_EDID)
2349             kfree(rinfo->mon1_EDID);
2350         if (rinfo->mon2_EDID)
2351             kfree(rinfo->mon2_EDID);
2352         if (rinfo->mon1_modedb)
2353                 fb_destroy_modedb(rinfo->mon1_modedb);
2354 #ifdef CONFIG_FB_RADEON_I2C
2355         radeon_delete_i2c_busses(rinfo);
2356 #endif
2357         if (rinfo->bios_seg)
2358                 radeon_unmap_ROM(rinfo, pdev);
2359         iounmap ((void*)rinfo->mmio_base);
2360 release_mmio:
2361         release_mem_region (rinfo->mmio_base_phys,
2362                             pci_resource_len(pdev, 2));
2363 release_fb:
2364         release_mem_region (rinfo->fb_base_phys,
2365                             pci_resource_len(pdev, 0));
2366 free_rinfo:
2367         framebuffer_release(info);
2368         return -ENODEV;
2369 }
2370
2371
2372
2373 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2374 {
2375         struct fb_info *info = pci_get_drvdata(pdev);
2376         struct radeonfb_info *rinfo = info->par;
2377
2378         if (!rinfo)
2379                 return;
2380
2381         /* restore original state
2382          *
2383          * Doesn't quite work yet, possibly because of the PPC hacking
2384          * I do on startup, disable for now. --BenH
2385          */
2386         radeon_write_mode (rinfo, &rinfo->init_state);
2387
2388         del_timer_sync(&rinfo->lvds_timer);
2389
2390 #ifdef CONFIG_MTRR
2391         if (rinfo->mtrr_hdl >= 0)
2392                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2393 #endif
2394
2395         unregister_framebuffer(info);
2396
2397         iounmap ((void*)rinfo->mmio_base);
2398         iounmap ((void*)rinfo->fb_base);
2399
2400         release_mem_region (rinfo->mmio_base_phys,
2401                             pci_resource_len(pdev, 2));
2402         release_mem_region (rinfo->fb_base_phys,
2403                             pci_resource_len(pdev, 0));
2404
2405         if (rinfo->mon1_EDID)
2406                 kfree(rinfo->mon1_EDID);
2407         if (rinfo->mon2_EDID)
2408                 kfree(rinfo->mon2_EDID);
2409         if (rinfo->mon1_modedb)
2410                 fb_destroy_modedb(rinfo->mon1_modedb);
2411 #ifdef CONFIG_FB_RADEON_I2C
2412         radeon_delete_i2c_busses(rinfo);
2413 #endif
2414         framebuffer_release(info);
2415 }
2416
2417
2418 static struct pci_driver radeonfb_driver = {
2419         .name           = "radeonfb",
2420         .id_table       = radeonfb_pci_table,
2421         .probe          = radeonfb_pci_register,
2422         .remove         = __devexit_p(radeonfb_pci_unregister),
2423 #ifdef CONFIG_PM
2424         .suspend        = radeonfb_pci_suspend,
2425         .resume         = radeonfb_pci_resume,
2426 #endif /* CONFIG_PM */
2427 };
2428
2429
2430 int __init radeonfb_init (void)
2431 {
2432         radeonfb_noaccel = noaccel;
2433         return pci_module_init (&radeonfb_driver);
2434 }
2435
2436
2437 void __exit radeonfb_exit (void)
2438 {
2439         pci_unregister_driver (&radeonfb_driver);
2440 }
2441
2442 int __init radeonfb_setup (char *options)
2443 {
2444         char *this_opt;
2445
2446         if (!options || !*options)
2447                 return 0;
2448
2449         while ((this_opt = strsep (&options, ",")) != NULL) {
2450                 if (!*this_opt)
2451                         continue;
2452
2453                 if (!strncmp(this_opt, "noaccel", 7)) {
2454                         noaccel = radeonfb_noaccel = 1;
2455                 } else if (!strncmp(this_opt, "mirror", 6)) {
2456                         mirror = 1;
2457                 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2458                         force_dfp = 1;
2459                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2460                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2461 #ifdef CONFIG_MTRR
2462                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2463                         nomtrr = 1;
2464 #endif
2465                 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2466                         nomodeset = 1;
2467                 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2468                         force_measure_pll = 1;
2469                 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2470                         ignore_edid = 1;
2471                 } else
2472                         mode_option = this_opt;
2473         }
2474         return 0;
2475 }
2476
2477
2478 #ifdef MODULE
2479 module_init(radeonfb_init);
2480 module_exit(radeonfb_exit);
2481 #endif
2482
2483 MODULE_AUTHOR("Ani Joshi");
2484 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2485 MODULE_LICENSE("GPL");
2486 module_param(noaccel, bool, 0);
2487 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2488 module_param(nomodeset, bool, 0);
2489 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2490 module_param(mirror, bool, 0);
2491 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2492 module_param(force_dfp, bool, 0);
2493 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2494 module_param(ignore_edid, bool, 0);
2495 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2496 module_param(monitor_layout, charp, 0);
2497 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2498 module_param(force_measure_pll, bool, 0);
2499 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2500 #ifdef CONFIG_MTRR
2501 module_param(nomtrr, bool, 0);
2502 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2503 #endif
2504 module_param(panel_yres, int, 0);
2505 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2506 module_param(mode_option, charp, 0);
2507 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");