4 #include <linux/config.h>
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/delay.h>
13 #include <linux/i2c.h>
14 #include <linux/i2c-id.h>
15 #include <linux/i2c-algo-bit.h>
19 #include <video/radeon.h>
21 /***************************************************************
22 * Most of the definitions here are adapted right from XFree86 *
23 ***************************************************************/
27 * Chip families. Must fit in the low 16 bits of a long word
34 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
36 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
39 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
50 enum radeon_chip_flags {
51 CHIP_FAMILY_MASK = 0x0000ffffUL,
52 CHIP_FLAGS_MASK = 0xffff0000UL,
53 CHIP_IS_MOBILITY = 0x00010000UL,
54 CHIP_IS_IGP = 0x00020000UL,
55 CHIP_HAS_CRTC2 = 0x00040000UL,
67 MT_CTV, /* composite TV */
68 MT_STV /* S-Video out */
122 * This structure contains the various registers manipulated by this
123 * driver for setting or restoring a mode. It's mostly copied from
124 * XFree's RADEONSaveRec structure. A few chip settings might still be
125 * tweaked without beeing reflected or saved in these registers though
128 /* Common registers */
130 u32 ovr_wid_left_right;
131 u32 ovr_wid_top_bottom;
145 /* Other registers to save for VT switches or driver load/unload */
148 u32 clock_cntl_index;
152 /* Surface/tiling registers */
153 u32 surf_lower_bound[8];
154 u32 surf_upper_bound[8];
161 u32 crtc_h_total_disp;
162 u32 crtc_h_sync_strt_wid;
163 u32 crtc_v_total_disp;
164 u32 crtc_v_sync_strt_wid;
166 u32 crtc_offset_cntl;
169 u32 grph_buffer_cntl;
172 /* CRTC2 registers */
175 u32 disp_output_cntl;
177 u32 disp2_merge_cntl;
178 u32 grph2_buffer_cntl;
179 u32 crtc2_h_total_disp;
180 u32 crtc2_h_sync_strt_wid;
181 u32 crtc2_v_total_disp;
182 u32 crtc2_v_sync_strt_wid;
184 u32 crtc2_offset_cntl;
187 /* Flat panel regs */
188 u32 fp_crtc_h_total_disp;
189 u32 fp_crtc_v_total_disp;
192 u32 fp_h_sync_strt_wid;
193 u32 fp2_h_sync_strt_wid;
196 u32 fp_v_sync_strt_wid;
197 u32 fp2_v_sync_strt_wid;
202 u32 tmds_transmitter_cntl;
204 /* Computed values for PLL */
214 /* Computed values for PLL2 */
215 u32 dot_clock_freq_2;
234 int hOver_plus, hSync_width, hblank;
235 int vOver_plus, vSync_width, vblank;
236 int hAct_high, vAct_high, interlaced;
238 int use_bios_dividers;
244 struct radeonfb_info;
246 #ifdef CONFIG_FB_RADEON_I2C
247 struct radeon_i2c_chan {
248 struct radeonfb_info *rinfo;
250 struct i2c_adapter adapter;
251 struct i2c_algo_bit_data algo;
255 struct radeonfb_info {
256 struct fb_info *info;
258 struct radeon_regs state;
259 struct radeon_regs init_state;
261 char name[DEVICE_NAME_SIZE];
264 unsigned long mmio_base_phys;
265 unsigned long fb_base_phys;
267 unsigned long mmio_base;
268 unsigned long fb_base;
270 unsigned long fb_local_base;
272 struct pci_dev *pdev;
277 u32 pseudo_palette[17];
278 struct { u8 red, green, blue, pad; }
284 unsigned long video_ram;
285 unsigned long mapped_vram;
287 int pitch, bpp, depth;
292 int R300_cg_workaround;
295 struct panel_info panel_info;
298 struct fb_videomode *mon1_modedb;
303 u32 dp_gui_master_cntl;
316 /* Lock on register access */
319 /* Timer used for delayed LVDS operations */
320 struct timer_list lvds_timer;
321 u32 pending_lvds_gen_cntl;
322 u32 pending_pixclks_cntl;
324 #ifdef CONFIG_FB_RADEON_I2C
325 struct radeon_i2c_chan i2c[4];
330 #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
336 #ifdef CONFIG_FB_RADEON_DEBUG
343 #define RTRACE printk
345 #define RTRACE if(0) printk
353 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
354 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
355 #define INREG(addr) readl((rinfo->mmio_base)+addr)
356 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
358 static inline void R300_cg_workardound(struct radeonfb_info *rinfo)
361 save = INREG(CLOCK_CNTL_INDEX);
362 tmp = save & ~(0x3f | PLL_WR_EN);
363 OUTREG(CLOCK_CNTL_INDEX, tmp);
364 tmp = INREG(CLOCK_CNTL_DATA);
365 OUTREG(CLOCK_CNTL_INDEX, save);
368 #define __OUTPLL(addr,val) \
370 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
371 OUTREG(CLOCK_CNTL_DATA, val); \
375 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
378 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
379 data = (INREG(CLOCK_CNTL_DATA));
380 if (rinfo->R300_cg_workaround)
381 R300_cg_workardound(rinfo);
385 static inline u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
390 spin_lock_irqsave(&rinfo->reg_lock, flags);
391 data = __INPLL(rinfo, addr);
392 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
396 #define INPLL(addr) _INPLL(rinfo, addr)
398 #define OUTPLL(addr,val) \
400 unsigned long flags;\
401 spin_lock_irqsave(&rinfo->reg_lock, flags); \
402 __OUTPLL(addr, val); \
403 spin_unlock_irqrestore(&rinfo->reg_lock, flags); \
406 #define OUTPLLP(addr,val,mask) \
408 unsigned long flags; \
410 spin_lock_irqsave(&rinfo->reg_lock, flags); \
411 _tmp = __INPLL(rinfo,addr); \
414 __OUTPLL(addr, _tmp); \
415 spin_unlock_irqrestore(&rinfo->reg_lock, flags); \
418 #define OUTREGP(addr,val,mask) \
420 unsigned long flags; \
422 spin_lock_irqsave(&rinfo->reg_lock, flags); \
423 _tmp = INREG(addr); \
426 OUTREG(addr, _tmp); \
427 spin_unlock_irqrestore(&rinfo->reg_lock, flags); \
430 #define MS_TO_HZ(ms) ((ms * HZ + 999) / 1000)
432 #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
433 #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
434 (readb(rinfo->bios_seg + (v) + 1) << 8))
435 #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
436 (readb(rinfo->bios_seg + (v) + 1) << 8) | \
437 (readb(rinfo->bios_seg + (v) + 2) << 16) | \
438 (readb(rinfo->bios_seg + (v) + 3) << 24))
444 static inline void wait_ms(unsigned long ms)
446 set_current_state(TASK_UNINTERRUPTIBLE);
447 schedule_timeout((ms * HZ + 999) / 1000);
452 static inline int round_div(int num, int den)
454 return (num + (den / 2)) / den;
457 static inline int var_to_depth(const struct fb_var_screeninfo *var)
459 if (var->bits_per_pixel != 16)
460 return var->bits_per_pixel;
461 return (var->green.length == 5) ? 15 : 16;
464 static inline u32 radeon_get_dstbpp(u16 depth)
481 * 2D Engine helper routines
483 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
488 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
491 for (i=0; i < 2000000; i++) {
492 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
496 printk(KERN_ERR "radeonfb: Flush Timeout !\n");
500 static inline void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
504 for (i=0; i<2000000; i++) {
505 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
509 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
513 static inline void _radeon_engine_idle (struct radeonfb_info *rinfo)
517 /* ensure FIFO is empty before waiting for idle */
518 _radeon_fifo_wait (rinfo, 64);
520 for (i=0; i<2000000; i++) {
521 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
522 radeon_engine_flush (rinfo);
527 printk(KERN_ERR "radeonfb: Idle Timeout !\n");
530 static inline int radeon_accel_disabled(void)
532 extern int radeonfb_noaccel;
533 return radeonfb_noaccel;
536 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
537 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
541 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
542 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
543 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
546 extern void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo);
547 extern void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo);
548 extern int radeonfb_pci_suspend(struct pci_dev *pdev, u32 state);
549 extern int radeonfb_pci_resume(struct pci_dev *pdev);
551 /* Monitor probe functions */
552 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
553 const char *monitor_layout, int ignore_edid);
554 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
555 extern int radeon_match_mode(struct radeonfb_info *rinfo,
556 struct fb_var_screeninfo *dest,
557 const struct fb_var_screeninfo *src);
559 /* Accel functions */
560 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
561 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
562 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
563 extern int radeonfb_sync(struct fb_info *info);
564 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
565 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
567 /* Other functions */
568 extern int radeonfb_blank(int blank, struct fb_info *info);
569 extern int radeonfb_set_par(struct fb_info *info);
571 #endif /* __RADEONFB_H__ */