2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
32 #include <linux/interrupt.h>
33 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/device.h>
40 #include <linux/dma-mapping.h>
42 #include <asm/hardware.h>
45 #include <asm/uaccess.h>
46 #include <asm/arch/bitfield.h>
47 #include <asm/arch/pxafb.h>
50 * Complain if VAR is out of range.
56 /* Bits which should not be set in machine configuration structures */
57 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
58 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
60 static void (*pxafb_backlight_power)(int);
61 static void (*pxafb_lcd_power)(int);
63 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
64 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
66 #ifdef CONFIG_FB_PXA_PARAMETERS
67 #define PXAFB_OPTIONS_SIZE 256
68 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
71 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
75 local_irq_save(flags);
77 * We need to handle two requests being made at the same time.
78 * There are two important cases:
79 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
80 * We must perform the unblanking, which will do our REENABLE for us.
81 * 2. When we are blanking, but immediately unblank before we have
82 * blanked. We do the "REENABLE" thing here as well, just to be sure.
84 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
86 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
89 if (state != (u_int)-1) {
90 fbi->task_state = state;
91 schedule_work(&fbi->task);
93 local_irq_restore(flags);
96 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
99 chan >>= 16 - bf->length;
100 return chan << bf->offset;
104 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
105 u_int trans, struct fb_info *info)
107 struct pxafb_info *fbi = (struct pxafb_info *)info;
110 if (regno < fbi->palette_size) {
111 if (fbi->fb.var.grayscale) {
112 val = ((blue >> 8) & 0x00ff);
114 val = ((red >> 0) & 0xf800);
115 val |= ((green >> 5) & 0x07e0);
116 val |= ((blue >> 11) & 0x001f);
118 fbi->palette_cpu[regno] = val;
125 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
126 u_int trans, struct fb_info *info)
128 struct pxafb_info *fbi = (struct pxafb_info *)info;
133 * If inverse mode was selected, invert all the colours
134 * rather than the register number. The register number
135 * is what you poke into the framebuffer to produce the
136 * colour you requested.
138 if (fbi->cmap_inverse) {
140 green = 0xffff - green;
141 blue = 0xffff - blue;
145 * If greyscale is true, then we convert the RGB value
146 * to greyscale no matter what visual we are using.
148 if (fbi->fb.var.grayscale)
149 red = green = blue = (19595 * red + 38470 * green +
152 switch (fbi->fb.fix.visual) {
153 case FB_VISUAL_TRUECOLOR:
155 * 16-bit True Colour. We encode the RGB value
156 * according to the RGB bitfield information.
159 u32 *pal = fbi->fb.pseudo_palette;
161 val = chan_to_field(red, &fbi->fb.var.red);
162 val |= chan_to_field(green, &fbi->fb.var.green);
163 val |= chan_to_field(blue, &fbi->fb.var.blue);
170 case FB_VISUAL_STATIC_PSEUDOCOLOR:
171 case FB_VISUAL_PSEUDOCOLOR:
172 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
180 * pxafb_bpp_to_lccr3():
181 * Convert a bits per pixel value to the correct bit pattern for LCCR3
183 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
186 switch (var->bits_per_pixel) {
187 case 1: ret = LCCR3_1BPP; break;
188 case 2: ret = LCCR3_2BPP; break;
189 case 4: ret = LCCR3_4BPP; break;
190 case 8: ret = LCCR3_8BPP; break;
191 case 16: ret = LCCR3_16BPP; break;
196 #ifdef CONFIG_CPU_FREQ
198 * pxafb_display_dma_period()
199 * Calculate the minimum period (in picoseconds) between two DMA
200 * requests for the LCD controller. If we hit this, it means we're
201 * doing nothing but LCD DMA.
203 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
206 * Period = pixclock * bits_per_byte * bytes_per_transfer
207 * / memory_bits_per_pixel;
209 return var->pixclock * 8 * 16 / var->bits_per_pixel;
212 extern unsigned int get_clk_frequency_khz(int info);
217 * Get the video params out of 'var'. If a value doesn't fit, round it up,
218 * if it's too big, return -EINVAL.
220 * Round up in the following order: bits_per_pixel, xres,
221 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
222 * bitfields, horizontal timing, vertical timing.
224 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
226 struct pxafb_info *fbi = (struct pxafb_info *)info;
228 if (var->xres < MIN_XRES)
229 var->xres = MIN_XRES;
230 if (var->yres < MIN_YRES)
231 var->yres = MIN_YRES;
232 if (var->xres > fbi->max_xres)
233 var->xres = fbi->max_xres;
234 if (var->yres > fbi->max_yres)
235 var->yres = fbi->max_yres;
237 max(var->xres_virtual, var->xres);
239 max(var->yres_virtual, var->yres);
242 * Setup the RGB parameters for this display.
244 * The pixel packing format is described on page 7-11 of the
245 * PXA2XX Developer's Manual.
247 if (var->bits_per_pixel == 16) {
248 var->red.offset = 11; var->red.length = 5;
249 var->green.offset = 5; var->green.length = 6;
250 var->blue.offset = 0; var->blue.length = 5;
251 var->transp.offset = var->transp.length = 0;
253 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
255 var->green.length = 8;
256 var->blue.length = 8;
257 var->transp.length = 0;
260 #ifdef CONFIG_CPU_FREQ
261 DPRINTK("dma period = %d ps, clock = %d kHz\n",
262 pxafb_display_dma_period(var),
263 get_clk_frequency_khz(0));
269 static inline void pxafb_set_truecolor(u_int is_true_color)
271 DPRINTK("true_color = %d\n", is_true_color);
272 // do your machine-specific setup if needed
277 * Set the user defined part of the display for the specified console
279 static int pxafb_set_par(struct fb_info *info)
281 struct pxafb_info *fbi = (struct pxafb_info *)info;
282 struct fb_var_screeninfo *var = &info->var;
283 unsigned long palette_mem_size;
285 DPRINTK("set_par\n");
287 if (var->bits_per_pixel == 16)
288 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
289 else if (!fbi->cmap_static)
290 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
293 * Some people have weird ideas about wanting static
294 * pseudocolor maps. I suspect their user space
295 * applications are broken.
297 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
300 fbi->fb.fix.line_length = var->xres_virtual *
301 var->bits_per_pixel / 8;
302 if (var->bits_per_pixel == 16)
303 fbi->palette_size = 0;
305 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
307 palette_mem_size = fbi->palette_size * sizeof(u16);
309 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
311 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
312 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
315 * Set (any) board control register to handle new color depth
317 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
319 if (fbi->fb.var.bits_per_pixel == 16)
320 fb_dealloc_cmap(&fbi->fb.cmap);
322 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
324 pxafb_activate_var(var, fbi);
330 * Formal definition of the VESA spec:
332 * This refers to the state of the display when it is in full operation
334 * This defines an optional operating state of minimal power reduction with
335 * the shortest recovery time
337 * This refers to a level of power management in which substantial power
338 * reduction is achieved by the display. The display can have a longer
339 * recovery time from this state than from the Stand-by state
341 * This indicates that the display is consuming the lowest level of power
342 * and is non-operational. Recovery from this state may optionally require
343 * the user to manually power on the monitor
345 * Now, the fbdev driver adds an additional state, (blank), where they
346 * turn off the video (maybe by colormap tricks), but don't mess with the
347 * video itself: think of it semantically between on and Stand-By.
349 * So here's what we should do in our fbdev blank routine:
351 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
352 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
353 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
354 * VESA_POWERDOWN (mode 3) Video off, front/back light off
356 * This will match the matrox implementation.
361 * Blank the display by setting all palette values to zero. Note, the
362 * 16 bpp mode does not really use the palette, so this will not
363 * blank the display in all modes.
365 static int pxafb_blank(int blank, struct fb_info *info)
367 struct pxafb_info *fbi = (struct pxafb_info *)info;
370 DPRINTK("pxafb_blank: blank=%d\n", blank);
374 case VESA_VSYNC_SUSPEND:
375 case VESA_HSYNC_SUSPEND:
376 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
377 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
378 for (i = 0; i < fbi->palette_size; i++)
379 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
381 pxafb_schedule_work(fbi, C_DISABLE);
382 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
385 case VESA_NO_BLANKING:
386 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
387 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
388 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
389 fb_set_cmap(&fbi->fb.cmap, info);
390 pxafb_schedule_work(fbi, C_ENABLE);
395 static struct fb_ops pxafb_ops = {
396 .owner = THIS_MODULE,
397 .fb_check_var = pxafb_check_var,
398 .fb_set_par = pxafb_set_par,
399 .fb_setcolreg = pxafb_setcolreg,
400 .fb_fillrect = cfb_fillrect,
401 .fb_copyarea = cfb_copyarea,
402 .fb_imageblit = cfb_imageblit,
403 .fb_blank = pxafb_blank,
404 .fb_cursor = soft_cursor,
408 * Calculate the PCD value from the clock rate (in picoseconds).
409 * We take account of the PPCR clock setting.
410 * From PXA Developer's Manual:
421 * LCLK = LCD/Memory Clock
424 * PixelClock here is in Hz while the pixclock argument given is the
425 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
427 * The function get_lclk_frequency_10khz returns LCLK in units of
428 * 10khz. Calling the result of this function lclk gives us the
431 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
432 * -------------------------------------- - 1
435 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
437 static inline unsigned int get_pcd(unsigned int pixclock)
439 unsigned long long pcd;
441 /* FIXME: Need to take into account Double Pixel Clock mode
442 * (DPC) bit? or perhaps set it based on the various clock
445 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
446 pcd /= 100000000 * 2;
447 /* no need for this, since we should subtract 1 anyway. they cancel */
448 /* pcd += 1; */ /* make up for integer math truncations */
449 return (unsigned int)pcd;
453 * pxafb_activate_var():
454 * Configures LCD Controller based on entries in var parameter. Settings are
455 * only written to the controller if changes were made.
457 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
459 struct pxafb_lcd_reg new_regs;
461 u_int lines_per_panel, pcd = get_pcd(var->pixclock);
463 DPRINTK("Configuring PXA LCD\n");
465 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
466 var->xres, var->hsync_len,
467 var->left_margin, var->right_margin);
468 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
469 var->yres, var->vsync_len,
470 var->upper_margin, var->lower_margin);
471 DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
474 if (var->xres < 16 || var->xres > 1024)
475 printk(KERN_ERR "%s: invalid xres %d\n",
476 fbi->fb.fix.id, var->xres);
477 switch(var->bits_per_pixel) {
485 printk(KERN_ERR "%s: invalid bit depth %d\n",
486 fbi->fb.fix.id, var->bits_per_pixel);
489 if (var->hsync_len < 1 || var->hsync_len > 64)
490 printk(KERN_ERR "%s: invalid hsync_len %d\n",
491 fbi->fb.fix.id, var->hsync_len);
492 if (var->left_margin < 1 || var->left_margin > 255)
493 printk(KERN_ERR "%s: invalid left_margin %d\n",
494 fbi->fb.fix.id, var->left_margin);
495 if (var->right_margin < 1 || var->right_margin > 255)
496 printk(KERN_ERR "%s: invalid right_margin %d\n",
497 fbi->fb.fix.id, var->right_margin);
498 if (var->yres < 1 || var->yres > 1024)
499 printk(KERN_ERR "%s: invalid yres %d\n",
500 fbi->fb.fix.id, var->yres);
501 if (var->vsync_len < 1 || var->vsync_len > 64)
502 printk(KERN_ERR "%s: invalid vsync_len %d\n",
503 fbi->fb.fix.id, var->vsync_len);
504 if (var->upper_margin < 0 || var->upper_margin > 255)
505 printk(KERN_ERR "%s: invalid upper_margin %d\n",
506 fbi->fb.fix.id, var->upper_margin);
507 if (var->lower_margin < 0 || var->lower_margin > 255)
508 printk(KERN_ERR "%s: invalid lower_margin %d\n",
509 fbi->fb.fix.id, var->lower_margin);
512 new_regs.lccr0 = fbi->lccr0 |
513 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
514 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
517 LCCR1_DisWdth(var->xres) +
518 LCCR1_HorSnchWdth(var->hsync_len) +
519 LCCR1_BegLnDel(var->left_margin) +
520 LCCR1_EndLnDel(var->right_margin);
523 * If we have a dual scan LCD, we need to halve
524 * the YRES parameter.
526 lines_per_panel = var->yres;
527 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
528 lines_per_panel /= 2;
531 LCCR2_DisHght(lines_per_panel) +
532 LCCR2_VrtSnchWdth(var->vsync_len) +
533 LCCR2_BegFrmDel(var->upper_margin) +
534 LCCR2_EndFrmDel(var->lower_margin);
536 new_regs.lccr3 = fbi->lccr3 |
537 pxafb_bpp_to_lccr3(var) |
538 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
539 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
542 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
544 DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
545 DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
546 DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
547 DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
549 /* Update shadow copy atomically */
550 local_irq_save(flags);
552 /* setup dma descriptors */
553 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
554 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
555 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
557 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
558 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
559 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
561 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
563 /* populate descriptors */
564 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
565 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
566 fbi->dmadesc_fblow_cpu->fidr = 0;
567 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
569 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
571 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
572 fbi->dmadesc_fbhigh_cpu->fidr = 0;
573 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
575 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
576 fbi->dmadesc_palette_cpu->fidr = 0;
577 fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
579 if (var->bits_per_pixel == 16) {
580 /* palette shouldn't be loaded in true-color mode */
581 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
582 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
583 /* init it to something, even though we won't be using it */
584 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
586 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
587 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
588 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
592 DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
593 DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
594 DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
595 DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
596 DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
597 DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
599 DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
600 DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
601 DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
603 DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
604 DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
605 DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
607 DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
608 DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
609 DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
612 fbi->reg_lccr0 = new_regs.lccr0;
613 fbi->reg_lccr1 = new_regs.lccr1;
614 fbi->reg_lccr2 = new_regs.lccr2;
615 fbi->reg_lccr3 = new_regs.lccr3;
616 local_irq_restore(flags);
619 * Only update the registers if the controller is enabled
620 * and something has changed.
622 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
623 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
624 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
625 pxafb_schedule_work(fbi, C_REENABLE);
631 * NOTE! The following functions are purely helpers for set_ctrlr_state.
632 * Do not call them directly; set_ctrlr_state does the correct serialisation
633 * to ensure that things happen in the right way 100% of time time.
636 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
638 DPRINTK("backlight o%s\n", on ? "n" : "ff");
640 if (pxafb_backlight_power)
641 pxafb_backlight_power(on);
644 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
646 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
652 static void pxafb_setup_gpio(struct pxafb_info *fbi)
654 unsigned int lccr0 = fbi->lccr0;
657 * setup is based on type of panel supported
660 /* 4 bit interface */
661 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
662 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
663 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
666 GPDR1 |= (0xf << 26);
667 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
670 GPDR2 |= (0xf << 10);
671 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
674 /* 8 bit interface */
675 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
676 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
677 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
678 (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
681 GPDR1 |= (0x3f << 26);
684 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
685 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
688 GPDR2 |= (0xf << 10);
689 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
692 /* 16 bit interface */
693 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
694 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
697 GPDR1 |= (0x3f << 26);
700 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
701 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
705 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
709 static void pxafb_enable_controller(struct pxafb_info *fbi)
711 DPRINTK("Enabling LCD controller\n");
712 DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
713 DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
714 DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
715 DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
716 DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
717 DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
719 /* Sequence from 11.7.10 */
720 LCCR3 = fbi->reg_lccr3;
721 LCCR2 = fbi->reg_lccr2;
722 LCCR1 = fbi->reg_lccr1;
723 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
725 FDADR0 = fbi->fdadr0;
726 FDADR1 = fbi->fdadr1;
729 DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
730 DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
731 DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
732 DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
733 DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
734 DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
737 static void pxafb_disable_controller(struct pxafb_info *fbi)
739 DECLARE_WAITQUEUE(wait, current);
741 DPRINTK("Disabling LCD controller\n");
743 add_wait_queue(&fbi->ctrlr_wait, &wait);
744 set_current_state(TASK_UNINTERRUPTIBLE);
746 LCSR = 0xffffffff; /* Clear LCD Status Register */
747 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
748 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
750 schedule_timeout(20 * HZ / 1000);
751 remove_wait_queue(&fbi->ctrlr_wait, &wait);
755 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
757 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
759 struct pxafb_info *fbi = dev_id;
760 unsigned int lcsr = LCSR;
762 if (lcsr & LCSR_LDD) {
764 wake_up(&fbi->ctrlr_wait);
772 * This function must be called from task context only, since it will
773 * sleep when disabling the LCD controller, or if we get two contending
774 * processes trying to alter state.
776 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
780 down(&fbi->ctrlr_sem);
782 old_state = fbi->state;
785 * Hack around fbcon initialisation.
787 if (old_state == C_STARTUP && state == C_REENABLE)
791 case C_DISABLE_CLKCHANGE:
793 * Disable controller for clock change. If the
794 * controller is already disabled, then do nothing.
796 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
798 //TODO __pxafb_lcd_power(fbi, 0);
799 pxafb_disable_controller(fbi);
808 if (old_state != C_DISABLE) {
810 __pxafb_backlight_power(fbi, 0);
811 __pxafb_lcd_power(fbi, 0);
812 if (old_state != C_DISABLE_CLKCHANGE)
813 pxafb_disable_controller(fbi);
817 case C_ENABLE_CLKCHANGE:
819 * Enable the controller after clock change. Only
820 * do this if we were disabled for the clock change.
822 if (old_state == C_DISABLE_CLKCHANGE) {
823 fbi->state = C_ENABLE;
824 pxafb_enable_controller(fbi);
825 //TODO __pxafb_lcd_power(fbi, 1);
831 * Re-enable the controller only if it was already
832 * enabled. This is so we reprogram the control
835 if (old_state == C_ENABLE) {
836 pxafb_disable_controller(fbi);
837 pxafb_setup_gpio(fbi);
838 pxafb_enable_controller(fbi);
844 * Re-enable the controller after PM. This is not
845 * perfect - think about the case where we were doing
846 * a clock change, and we suspended half-way through.
848 if (old_state != C_DISABLE_PM)
854 * Power up the LCD screen, enable controller, and
855 * turn on the backlight.
857 if (old_state != C_ENABLE) {
858 fbi->state = C_ENABLE;
859 pxafb_setup_gpio(fbi);
860 pxafb_enable_controller(fbi);
861 __pxafb_lcd_power(fbi, 1);
862 __pxafb_backlight_power(fbi, 1);
870 * Our LCD controller task (which is called when we blank or unblank)
873 static void pxafb_task(void *dummy)
875 struct pxafb_info *fbi = dummy;
876 u_int state = xchg(&fbi->task_state, -1);
878 set_ctrlr_state(fbi, state);
881 #ifdef CONFIG_CPU_FREQ
883 * CPU clock speed change handler. We need to adjust the LCD timing
884 * parameters when the CPU clock is adjusted by the power management
887 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
890 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
892 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
893 //TODO struct cpufreq_freqs *f = data;
897 case CPUFREQ_PRECHANGE:
898 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
901 case CPUFREQ_POSTCHANGE:
902 pcd = get_pcd(fbi->fb.var.pixclock);
903 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
904 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
911 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
913 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
914 struct fb_var_screeninfo *var = &fbi->fb.var;
915 struct cpufreq_policy *policy = data;
919 case CPUFREQ_INCOMPATIBLE:
920 printk(KERN_DEBUG "min dma period: %d ps, "
921 "new clock %d kHz\n", pxafb_display_dma_period(var),
923 // TODO: fill in min/max values
927 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
929 /* todo: panic if min/max values aren't fulfilled
930 * [can't really happen unless there's a bug in the
931 * CPU policy verification process *
942 * Power management hooks. Note that we won't be called from IRQ context,
943 * unlike the blank functions above, so we may sleep.
945 static int pxafb_suspend(struct device *dev, u32 state, u32 level)
947 struct pxafb_info *fbi = dev_get_drvdata(dev);
949 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
950 set_ctrlr_state(fbi, C_DISABLE_PM);
954 static int pxafb_resume(struct device *dev, u32 level)
956 struct pxafb_info *fbi = dev_get_drvdata(dev);
958 if (level == RESUME_ENABLE)
959 set_ctrlr_state(fbi, C_ENABLE_PM);
963 #define pxafb_suspend NULL
964 #define pxafb_resume NULL
968 * pxafb_map_video_memory():
969 * Allocates the DRAM memory for the frame buffer. This buffer is
970 * remapped into a non-cached, non-buffered, memory region to
971 * allow palette and pixel writes to occur without flushing the
972 * cache. Once this area is remapped, all virtual memory
973 * access to the video memory should occur at the new region.
975 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
977 u_long palette_mem_size;
980 * We reserve one page for the palette, plus the size
981 * of the framebuffer.
983 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
984 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
985 &fbi->map_dma, GFP_KERNEL);
988 /* prevent initial garbage on screen */
989 memset(fbi->map_cpu, 0, fbi->map_size);
990 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
991 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
993 * FIXME: this is actually the wrong thing to place in
994 * smem_start. But fbdev suffers from the problem that
995 * it needs an API which doesn't exist (in this case,
996 * dma_writecombine_mmap)
998 fbi->fb.fix.smem_start = fbi->screen_dma;
1000 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1002 palette_mem_size = fbi->palette_size * sizeof(u16);
1003 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
1005 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1006 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1009 return fbi->map_cpu ? 0 : -ENOMEM;
1012 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1014 struct pxafb_info *fbi;
1016 struct pxafb_mach_info *inf = dev->platform_data;
1018 /* Alloc the pxafb_info and pseudo_palette in one step */
1019 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1023 memset(fbi, 0, sizeof(struct pxafb_info));
1026 strcpy(fbi->fb.fix.id, PXA_NAME);
1028 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1029 fbi->fb.fix.type_aux = 0;
1030 fbi->fb.fix.xpanstep = 0;
1031 fbi->fb.fix.ypanstep = 0;
1032 fbi->fb.fix.ywrapstep = 0;
1033 fbi->fb.fix.accel = FB_ACCEL_NONE;
1035 fbi->fb.var.nonstd = 0;
1036 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1037 fbi->fb.var.height = -1;
1038 fbi->fb.var.width = -1;
1039 fbi->fb.var.accel_flags = 0;
1040 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1042 fbi->fb.fbops = &pxafb_ops;
1043 fbi->fb.flags = FBINFO_FLAG_DEFAULT;
1045 fbi->fb.currcon = -1;
1048 addr = addr + sizeof(struct pxafb_info);
1049 fbi->fb.pseudo_palette = addr;
1051 fbi->max_xres = inf->xres;
1052 fbi->fb.var.xres = inf->xres;
1053 fbi->fb.var.xres_virtual = inf->xres;
1054 fbi->max_yres = inf->yres;
1055 fbi->fb.var.yres = inf->yres;
1056 fbi->fb.var.yres_virtual = inf->yres;
1057 fbi->max_bpp = inf->bpp;
1058 fbi->fb.var.bits_per_pixel = inf->bpp;
1059 fbi->fb.var.pixclock = inf->pixclock;
1060 fbi->fb.var.hsync_len = inf->hsync_len;
1061 fbi->fb.var.left_margin = inf->left_margin;
1062 fbi->fb.var.right_margin = inf->right_margin;
1063 fbi->fb.var.vsync_len = inf->vsync_len;
1064 fbi->fb.var.upper_margin = inf->upper_margin;
1065 fbi->fb.var.lower_margin = inf->lower_margin;
1066 fbi->fb.var.sync = inf->sync;
1067 fbi->fb.var.grayscale = inf->cmap_greyscale;
1068 fbi->cmap_inverse = inf->cmap_inverse;
1069 fbi->cmap_static = inf->cmap_static;
1070 fbi->lccr0 = inf->lccr0;
1071 fbi->lccr3 = inf->lccr3;
1072 fbi->state = C_STARTUP;
1073 fbi->task_state = (u_char)-1;
1074 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1077 init_waitqueue_head(&fbi->ctrlr_wait);
1078 INIT_WORK(&fbi->task, pxafb_task, fbi);
1079 init_MUTEX(&fbi->ctrlr_sem);
1084 #ifdef CONFIG_FB_PXA_PARAMETERS
1085 static int __init pxafb_parse_options(struct device *dev, char *options)
1087 struct pxafb_mach_info *inf = dev->platform_data;
1090 if (!options || !*options)
1093 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1095 /* could be made table driven or similar?... */
1096 while ((this_opt = strsep(&options, ",")) != NULL) {
1097 if (!strncmp(this_opt, "mode:", 5)) {
1098 const char *name = this_opt+5;
1099 unsigned int namelen = strlen(name);
1100 int res_specified = 0, bpp_specified = 0;
1101 unsigned int xres = 0, yres = 0, bpp = 0;
1102 int yres_specified = 0;
1104 for (i = namelen-1; i >= 0; i--) {
1108 if (!bpp_specified && !yres_specified) {
1109 bpp = simple_strtoul(&name[i+1], NULL, 0);
1115 if (!yres_specified) {
1116 yres = simple_strtoul(&name[i+1], NULL, 0);
1127 if (i < 0 && yres_specified) {
1128 xres = simple_strtoul(name, NULL, 0);
1132 if (res_specified) {
1133 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1134 inf->xres = xres; inf->yres = yres;
1144 dev_info(dev, "overriding bit depth: %d\n", bpp);
1147 dev_err(dev, "Depth %d is not valid\n", bpp);
1149 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1150 inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1151 dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1152 } else if (!strncmp(this_opt, "left:", 5)) {
1153 inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1154 dev_info(dev, "override left: %u\n", inf->left_margin);
1155 } else if (!strncmp(this_opt, "right:", 6)) {
1156 inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1157 dev_info(dev, "override right: %u\n", inf->right_margin);
1158 } else if (!strncmp(this_opt, "upper:", 6)) {
1159 inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1160 dev_info(dev, "override upper: %u\n", inf->upper_margin);
1161 } else if (!strncmp(this_opt, "lower:", 6)) {
1162 inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1163 dev_info(dev, "override lower: %u\n", inf->lower_margin);
1164 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1165 inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1166 dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1167 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1168 inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1169 dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1170 } else if (!strncmp(this_opt, "hsync:", 6)) {
1171 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1172 dev_info(dev, "override hsync: Active Low\n");
1173 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1175 dev_info(dev, "override hsync: Active High\n");
1176 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1178 } else if (!strncmp(this_opt, "vsync:", 6)) {
1179 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1180 dev_info(dev, "override vsync: Active Low\n");
1181 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1183 dev_info(dev, "override vsync: Active High\n");
1184 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1186 } else if (!strncmp(this_opt, "dpc:", 4)) {
1187 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1188 dev_info(dev, "override double pixel clock: false\n");
1189 inf->lccr3 &= ~LCCR3_DPC;
1191 dev_info(dev, "override double pixel clock: true\n");
1192 inf->lccr3 |= LCCR3_DPC;
1194 } else if (!strncmp(this_opt, "outputen:", 9)) {
1195 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1196 dev_info(dev, "override output enable: active low\n");
1197 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1199 dev_info(dev, "override output enable: active high\n");
1200 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1202 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1203 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1204 dev_info(dev, "override pixel clock polarity: falling edge\n");
1205 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1207 dev_info(dev, "override pixel clock polarity: rising edge\n");
1208 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1210 } else if (!strncmp(this_opt, "color", 5)) {
1211 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1212 } else if (!strncmp(this_opt, "mono", 4)) {
1213 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1214 } else if (!strncmp(this_opt, "active", 6)) {
1215 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1216 } else if (!strncmp(this_opt, "passive", 7)) {
1217 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1218 } else if (!strncmp(this_opt, "single", 6)) {
1219 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1220 } else if (!strncmp(this_opt, "dual", 4)) {
1221 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1222 } else if (!strncmp(this_opt, "4pix", 4)) {
1223 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1224 } else if (!strncmp(this_opt, "8pix", 4)) {
1225 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1227 dev_err(dev, "unknown option: %s\n", this_opt);
1236 int __init pxafb_probe(struct device *dev)
1238 struct pxafb_info *fbi;
1239 struct pxafb_mach_info *inf;
1242 dev_dbg(dev, "pxafb_probe\n");
1244 inf = dev->platform_data;
1250 #ifdef CONFIG_FB_PXA_PARAMETERS
1251 ret = pxafb_parse_options(dev, g_options);
1257 /* Check for various illegal bit-combinations. Currently only
1258 * a warning is given. */
1260 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1261 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1262 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1263 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1264 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1265 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1266 if (inf->lccr0 & LCCR0_DPD &&
1267 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1268 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1269 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1270 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1271 " single panel mode\n");
1272 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1273 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1274 dev_warn(dev, "Dual panel only valid in passive mode\n");
1275 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1276 (inf->upper_margin || inf->lower_margin))
1277 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1280 dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1281 if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1282 dev_err(dev, "Invalid resolution or bit depth\n");
1286 pxafb_backlight_power = inf->pxafb_backlight_power;
1287 pxafb_lcd_power = inf->pxafb_lcd_power;
1288 fbi = pxafb_init_fbinfo(dev);
1290 dev_err(dev, "Failed to initialize framebuffer device\n");
1291 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1295 /* Initialize video memory */
1296 ret = pxafb_map_video_memory(fbi);
1298 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1302 /* enable LCD controller clock */
1303 pxa_set_cken(CKEN16_LCD, 1);
1305 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1307 dev_err(dev, "request_irq failed: %d\n", ret);
1313 * This makes sure that our colour bitfield
1314 * descriptors are correctly initialised.
1316 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1317 pxafb_set_par(&fbi->fb);
1319 dev_set_drvdata(dev, fbi);
1321 ret = register_framebuffer(&fbi->fb);
1323 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1331 #ifdef CONFIG_CPU_FREQ
1332 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1333 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1334 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1335 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1339 * Ok, now enable the LCD controller
1341 set_ctrlr_state(fbi, C_ENABLE);
1346 dev_set_drvdata(dev, NULL);
1352 static struct device_driver pxafb_driver = {
1353 .name = "pxa2xx-fb",
1354 .bus = &platform_bus_type,
1355 .probe = pxafb_probe,
1357 .suspend = pxafb_suspend,
1358 .resume = pxafb_resume,
1362 int __devinit pxafb_init(void)
1364 return driver_register(&pxafb_driver);
1368 int __devinit pxafb_setup(char *options)
1370 # ifdef CONFIG_FB_PXA_PARAMETERS
1371 strlcpy(g_options, options, sizeof(g_options));
1376 module_init(pxafb_init);
1377 # ifdef CONFIG_FB_PXA_PARAMETERS
1378 module_param_string(options, g_options, sizeof(g_options), 0);
1379 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1383 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1384 MODULE_LICENSE("GPL");