drivers/video/pxafb.c

   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  */
  24
  25 #include <linux/config.h>
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/kernel.h>
  29 #include <linux/sched.h>
  30 #include <linux/errno.h>
  31 #include <linux/string.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/slab.h>
  34 #include <linux/fb.h>
  35 #include <linux/delay.h>
  36 #include <linux/init.h>
  37 #include <linux/ioport.h>
  38 #include <linux/cpufreq.h>
  39 #include <linux/device.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <asm/hardware.h>
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/uaccess.h>
  46 #include <asm/arch/pxa-regs.h>
  47 #include <asm/arch/bitfield.h>
  48 #include <asm/arch/pxafb.h>
  49
  50 /*
  51  * Complain if VAR is out of range.
  52  */
  53 #define DEBUG_VAR 1
  54
  55 #include "pxafb.h"
  56
  57 /* Bits which should not be set in machine configuration structures */
  58 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
  59 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
  60
  61 static void (*pxafb_backlight_power)(int);
  62 static void (*pxafb_lcd_power)(int);
  63
  64 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
  65 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  66
  67 #ifdef CONFIG_FB_PXA_PARAMETERS
  68 #define PXAFB_OPTIONS_SIZE 256
  69 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
  70 #endif
  71
  72 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  73 {
  74         unsigned long flags;
  75
  76         local_irq_save(flags);
  77         /*
  78          * We need to handle two requests being made at the same time.
  79          * There are two important cases:
  80          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
  81          *     We must perform the unblanking, which will do our REENABLE for us.
  82          *  2. When we are blanking, but immediately unblank before we have
  83          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
  84          */
  85         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  86                 state = (u_int) -1;
  87         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  88                 state = C_REENABLE;
  89
  90         if (state != (u_int)-1) {
  91                 fbi->task_state = state;
  92                 schedule_work(&fbi->task);
  93         }
  94         local_irq_restore(flags);
  95 }
  96
  97 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  98 {
  99         chan &= 0xffff;
 100         chan >>= 16 - bf->length;
 101         return chan << bf->offset;
 102 }
 103
 104 static int
 105 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 106                        u_int trans, struct fb_info *info)
 107 {
 108         struct pxafb_info *fbi = (struct pxafb_info *)info;
 109         u_int val, ret = 1;
 110
 111         if (regno < fbi->palette_size) {
 112                 if (fbi->fb.var.grayscale) {
 113                         val = ((blue >> 8) & 0x00ff);
 114                 } else {
 115                         val  = ((red   >>  0) & 0xf800);
 116                         val |= ((green >>  5) & 0x07e0);
 117                         val |= ((blue  >> 11) & 0x001f);
 118                 }
 119                 fbi->palette_cpu[regno] = val;
 120                 ret = 0;
 121         }
 122         return ret;
 123 }
 124
 125 static int
 126 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 127                    u_int trans, struct fb_info *info)
 128 {
 129         struct pxafb_info *fbi = (struct pxafb_info *)info;
 130         unsigned int val;
 131         int ret = 1;
 132
 133         /*
 134          * If inverse mode was selected, invert all the colours
 135          * rather than the register number.  The register number
 136          * is what you poke into the framebuffer to produce the
 137          * colour you requested.
 138          */
 139         if (fbi->cmap_inverse) {
 140                 red   = 0xffff - red;
 141                 green = 0xffff - green;
 142                 blue  = 0xffff - blue;
 143         }
 144
 145         /*
 146          * If greyscale is true, then we convert the RGB value
 147          * to greyscale no matter what visual we are using.
 148          */
 149         if (fbi->fb.var.grayscale)
 150                 red = green = blue = (19595 * red + 38470 * green +
 151                                         7471 * blue) >> 16;
 152
 153         switch (fbi->fb.fix.visual) {
 154         case FB_VISUAL_TRUECOLOR:
 155                 /*
 156                  * 16-bit True Colour.  We encode the RGB value
 157                  * according to the RGB bitfield information.
 158                  */
 159                 if (regno < 16) {
 160                         u32 *pal = fbi->fb.pseudo_palette;
 161
 162                         val  = chan_to_field(red, &fbi->fb.var.red);
 163                         val |= chan_to_field(green, &fbi->fb.var.green);
 164                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 165
 166                         pal[regno] = val;
 167                         ret = 0;
 168                 }
 169                 break;
 170
 171         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 172         case FB_VISUAL_PSEUDOCOLOR:
 173                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 174                 break;
 175         }
 176
 177         return ret;
 178 }
 179
 180 /*
 181  *  pxafb_bpp_to_lccr3():
 182  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 183  */
 184 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
 185 {
 186         int ret = 0;
 187         switch (var->bits_per_pixel) {
 188         case 1:  ret = LCCR3_1BPP; break;
 189         case 2:  ret = LCCR3_2BPP; break;
 190         case 4:  ret = LCCR3_4BPP; break;
 191         case 8:  ret = LCCR3_8BPP; break;
 192         case 16: ret = LCCR3_16BPP; break;
 193         }
 194         return ret;
 195 }
 196
 197 #ifdef CONFIG_CPU_FREQ
 198 /*
 199  *  pxafb_display_dma_period()
 200  *    Calculate the minimum period (in picoseconds) between two DMA
 201  *    requests for the LCD controller.  If we hit this, it means we're
 202  *    doing nothing but LCD DMA.
 203  */
 204 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 205 {
 206        /*
 207         * Period = pixclock * bits_per_byte * bytes_per_transfer
 208         *              / memory_bits_per_pixel;
 209         */
 210        return var->pixclock * 8 * 16 / var->bits_per_pixel;
 211 }
 212
 213 extern unsigned int get_clk_frequency_khz(int info);
 214 #endif
 215
 216 /*
 217  *  pxafb_check_var():
 218  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 219  *    if it's too big, return -EINVAL.
 220  *
 221  *    Round up in the following order: bits_per_pixel, xres,
 222  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 223  *    bitfields, horizontal timing, vertical timing.
 224  */
 225 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 226 {
 227         struct pxafb_info *fbi = (struct pxafb_info *)info;
 228
 229         if (var->xres < MIN_XRES)
 230                 var->xres = MIN_XRES;
 231         if (var->yres < MIN_YRES)
 232                 var->yres = MIN_YRES;
 233         if (var->xres > fbi->max_xres)
 234                 var->xres = fbi->max_xres;
 235         if (var->yres > fbi->max_yres)
 236                 var->yres = fbi->max_yres;
 237         var->xres_virtual =
 238                 max(var->xres_virtual, var->xres);
 239         var->yres_virtual =
 240                 max(var->yres_virtual, var->yres);
 241
 242         /*
 243          * Setup the RGB parameters for this display.
 244          *
 245          * The pixel packing format is described on page 7-11 of the
 246          * PXA2XX Developer's Manual.
 247          */
 248         if (var->bits_per_pixel == 16) {
 249                 var->red.offset   = 11; var->red.length   = 5;
 250                 var->green.offset = 5;  var->green.length = 6;
 251                 var->blue.offset  = 0;  var->blue.length  = 5;
 252                 var->transp.offset = var->transp.length = 0;
 253         } else {
 254                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
 255                 var->red.length   = 8;
 256                 var->green.length = 8;
 257                 var->blue.length  = 8;
 258                 var->transp.length = 0;
 259         }
 260
 261 #ifdef CONFIG_CPU_FREQ
 262         DPRINTK("dma period = %d ps, clock = %d kHz\n",
 263                 pxafb_display_dma_period(var),
 264                 get_clk_frequency_khz(0));
 265 #endif
 266
 267         return 0;
 268 }
 269
 270 static inline void pxafb_set_truecolor(u_int is_true_color)
 271 {
 272         DPRINTK("true_color = %d\n", is_true_color);
 273         // do your machine-specific setup if needed
 274 }
 275
 276 /*
 277  * pxafb_set_par():
 278  *      Set the user defined part of the display for the specified console
 279  */
 280 static int pxafb_set_par(struct fb_info *info)
 281 {
 282         struct pxafb_info *fbi = (struct pxafb_info *)info;
 283         struct fb_var_screeninfo *var = &info->var;
 284         unsigned long palette_mem_size;
 285
 286         DPRINTK("set_par\n");
 287
 288         if (var->bits_per_pixel == 16)
 289                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 290         else if (!fbi->cmap_static)
 291                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 292         else {
 293                 /*
 294                  * Some people have weird ideas about wanting static
 295                  * pseudocolor maps.  I suspect their user space
 296                  * applications are broken.
 297                  */
 298                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 299         }
 300
 301         fbi->fb.fix.line_length = var->xres_virtual *
 302                                   var->bits_per_pixel / 8;
 303         if (var->bits_per_pixel == 16)
 304                 fbi->palette_size = 0;
 305         else
 306                 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
 307
 308         palette_mem_size = fbi->palette_size * sizeof(u16);
 309
 310         DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 311
 312         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
 313         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
 314
 315         /*
 316          * Set (any) board control register to handle new color depth
 317          */
 318         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
 319
 320         if (fbi->fb.var.bits_per_pixel == 16)
 321                 fb_dealloc_cmap(&fbi->fb.cmap);
 322         else
 323                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 324
 325         pxafb_activate_var(var, fbi);
 326
 327         return 0;
 328 }
 329
 330 /*
 331  * Formal definition of the VESA spec:
 332  *  On
 333  *      This refers to the state of the display when it is in full operation
 334  *  Stand-By
 335  *      This defines an optional operating state of minimal power reduction with
 336  *      the shortest recovery time
 337  *  Suspend
 338  *      This refers to a level of power management in which substantial power
 339  *      reduction is achieved by the display.  The display can have a longer
 340  *      recovery time from this state than from the Stand-by state
 341  *  Off
 342  *      This indicates that the display is consuming the lowest level of power
 343  *      and is non-operational. Recovery from this state may optionally require
 344  *      the user to manually power on the monitor
 345  *
 346  *  Now, the fbdev driver adds an additional state, (blank), where they
 347  *  turn off the video (maybe by colormap tricks), but don't mess with the
 348  *  video itself: think of it semantically between on and Stand-By.
 349  *
 350  *  So here's what we should do in our fbdev blank routine:
 351  *
 352  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
 353  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
 354  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
 355  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
 356  *
 357  *  This will match the matrox implementation.
 358  */
 359
 360 /*
 361  * pxafb_blank():
 362  *      Blank the display by setting all palette values to zero.  Note, the
 363  *      16 bpp mode does not really use the palette, so this will not
 364  *      blank the display in all modes.
 365  */
 366 static int pxafb_blank(int blank, struct fb_info *info)
 367 {
 368         struct pxafb_info *fbi = (struct pxafb_info *)info;
 369         int i;
 370
 371         DPRINTK("pxafb_blank: blank=%d\n", blank);
 372
 373         switch (blank) {
 374         case FB_BLANK_POWERDOWN:
 375         case FB_BLANK_VSYNC_SUSPEND:
 376         case FB_BLANK_HSYNC_SUSPEND:
 377         case FB_BLANK_NORMAL:
 378                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 379                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 380                         for (i = 0; i < fbi->palette_size; i++)
 381                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 382
 383                 pxafb_schedule_work(fbi, C_DISABLE);
 384                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 385                 break;
 386
 387         case FB_BLANK_UNBLANK:
 388                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 389                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 390                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 391                         fb_set_cmap(&fbi->fb.cmap, info);
 392                 pxafb_schedule_work(fbi, C_ENABLE);
 393         }
 394         return 0;
 395 }
 396
 397 static struct fb_ops pxafb_ops = {
 398         .owner          = THIS_MODULE,
 399         .fb_check_var   = pxafb_check_var,
 400         .fb_set_par     = pxafb_set_par,
 401         .fb_setcolreg   = pxafb_setcolreg,
 402         .fb_fillrect    = cfb_fillrect,
 403         .fb_copyarea    = cfb_copyarea,
 404         .fb_imageblit   = cfb_imageblit,
 405         .fb_blank       = pxafb_blank,
 406         .fb_cursor      = soft_cursor,
 407 };
 408
 409 /*
 410  * Calculate the PCD value from the clock rate (in picoseconds).
 411  * We take account of the PPCR clock setting.
 412  * From PXA Developer's Manual:
 413  *
 414  *   PixelClock =      LCLK
 415  *                -------------
 416  *                2 ( PCD + 1 )
 417  *
 418  *   PCD =      LCLK
 419  *         ------------- - 1
 420  *         2(PixelClock)
 421  *
 422  * Where:
 423  *   LCLK = LCD/Memory Clock
 424  *   PCD = LCCR3[7:0]
 425  *
 426  * PixelClock here is in Hz while the pixclock argument given is the
 427  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
 428  *
 429  * The function get_lclk_frequency_10khz returns LCLK in units of
 430  * 10khz. Calling the result of this function lclk gives us the
 431  * following
 432  *
 433  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
 434  *          -------------------------------------- - 1
 435  *                          2
 436  *
 437  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
 438  */
 439 static inline unsigned int get_pcd(unsigned int pixclock)
 440 {
 441         unsigned long long pcd;
 442
 443         /* FIXME: Need to take into account Double Pixel Clock mode
 444          * (DPC) bit? or perhaps set it based on the various clock
 445          * speeds */
 446
 447         pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
 448         pcd /= 100000000 * 2;
 449         /* no need for this, since we should subtract 1 anyway. they cancel */
 450         /* pcd += 1; */ /* make up for integer math truncations */
 451         return (unsigned int)pcd;
 452 }
 453
 454 /*
 455  * pxafb_activate_var():
 456  *      Configures LCD Controller based on entries in var parameter.  Settings are
 457  *      only written to the controller if changes were made.
 458  */
 459 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
 460 {
 461         struct pxafb_lcd_reg new_regs;
 462         u_long flags;
 463         u_int lines_per_panel, pcd = get_pcd(var->pixclock);
 464
 465         DPRINTK("Configuring PXA LCD\n");
 466
 467         DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
 468                 var->xres, var->hsync_len,
 469                 var->left_margin, var->right_margin);
 470         DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
 471                 var->yres, var->vsync_len,
 472                 var->upper_margin, var->lower_margin);
 473         DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
 474
 475 #if DEBUG_VAR
 476         if (var->xres < 16        || var->xres > 1024)
 477                 printk(KERN_ERR "%s: invalid xres %d\n",
 478                         fbi->fb.fix.id, var->xres);
 479         switch(var->bits_per_pixel) {
 480         case 1:
 481         case 2:
 482         case 4:
 483         case 8:
 484         case 16:
 485                 break;
 486         default:
 487                 printk(KERN_ERR "%s: invalid bit depth %d\n",
 488                        fbi->fb.fix.id, var->bits_per_pixel);
 489                 break;
 490         }
 491         if (var->hsync_len < 1    || var->hsync_len > 64)
 492                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
 493                         fbi->fb.fix.id, var->hsync_len);
 494         if (var->left_margin < 1  || var->left_margin > 255)
 495                 printk(KERN_ERR "%s: invalid left_margin %d\n",
 496                         fbi->fb.fix.id, var->left_margin);
 497         if (var->right_margin < 1 || var->right_margin > 255)
 498                 printk(KERN_ERR "%s: invalid right_margin %d\n",
 499                         fbi->fb.fix.id, var->right_margin);
 500         if (var->yres < 1         || var->yres > 1024)
 501                 printk(KERN_ERR "%s: invalid yres %d\n",
 502                         fbi->fb.fix.id, var->yres);
 503         if (var->vsync_len < 1    || var->vsync_len > 64)
 504                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
 505                         fbi->fb.fix.id, var->vsync_len);
 506         if (var->upper_margin < 0 || var->upper_margin > 255)
 507                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
 508                         fbi->fb.fix.id, var->upper_margin);
 509         if (var->lower_margin < 0 || var->lower_margin > 255)
 510                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
 511                         fbi->fb.fix.id, var->lower_margin);
 512 #endif
 513
 514         new_regs.lccr0 = fbi->lccr0 |
 515                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
 516                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
 517
 518         new_regs.lccr1 =
 519                 LCCR1_DisWdth(var->xres) +
 520                 LCCR1_HorSnchWdth(var->hsync_len) +
 521                 LCCR1_BegLnDel(var->left_margin) +
 522                 LCCR1_EndLnDel(var->right_margin);
 523
 524         /*
 525          * If we have a dual scan LCD, we need to halve
 526          * the YRES parameter.
 527          */
 528         lines_per_panel = var->yres;
 529         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
 530                 lines_per_panel /= 2;
 531
 532         new_regs.lccr2 =
 533                 LCCR2_DisHght(lines_per_panel) +
 534                 LCCR2_VrtSnchWdth(var->vsync_len) +
 535                 LCCR2_BegFrmDel(var->upper_margin) +
 536                 LCCR2_EndFrmDel(var->lower_margin);
 537
 538         new_regs.lccr3 = fbi->lccr3 |
 539                 pxafb_bpp_to_lccr3(var) |
 540                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
 541                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
 542
 543         if (pcd)
 544                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
 545
 546         DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
 547         DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
 548         DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
 549         DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
 550
 551         /* Update shadow copy atomically */
 552         local_irq_save(flags);
 553
 554         /* setup dma descriptors */
 555         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
 556         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
 557         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
 558
 559         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
 560         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
 561         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
 562
 563 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
 564
 565         /* populate descriptors */
 566         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
 567         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
 568         fbi->dmadesc_fblow_cpu->fidr  = 0;
 569         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
 570
 571         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
 572
 573         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
 574         fbi->dmadesc_fbhigh_cpu->fidr = 0;
 575         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
 576
 577         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
 578         fbi->dmadesc_palette_cpu->fidr  = 0;
 579         fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 580
 581         if (var->bits_per_pixel == 16) {
 582                 /* palette shouldn't be loaded in true-color mode */
 583                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 584                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
 585                 /* init it to something, even though we won't be using it */
 586                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
 587         } else {
 588                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 589                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
 590                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
 591         }
 592
 593 #if 0
 594         DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
 595         DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
 596         DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
 597         DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
 598         DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
 599         DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
 600
 601         DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
 602         DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
 603         DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
 604
 605         DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
 606         DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
 607         DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
 608
 609         DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
 610         DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
 611         DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
 612 #endif
 613
 614         fbi->reg_lccr0 = new_regs.lccr0;
 615         fbi->reg_lccr1 = new_regs.lccr1;
 616         fbi->reg_lccr2 = new_regs.lccr2;
 617         fbi->reg_lccr3 = new_regs.lccr3;
 618         local_irq_restore(flags);
 619
 620         /*
 621          * Only update the registers if the controller is enabled
 622          * and something has changed.
 623          */
 624         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
 625             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
 626             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
 627                 pxafb_schedule_work(fbi, C_REENABLE);
 628
 629         return 0;
 630 }
 631
 632 /*
 633  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
 634  * Do not call them directly; set_ctrlr_state does the correct serialisation
 635  * to ensure that things happen in the right way 100% of time time.
 636  *      -- rmk
 637  */
 638 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
 639 {
 640         DPRINTK("backlight o%s\n", on ? "n" : "ff");
 641
 642         if (pxafb_backlight_power)
 643                 pxafb_backlight_power(on);
 644 }
 645
 646 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
 647 {
 648         DPRINTK("LCD power o%s\n", on ? "n" : "ff");
 649
 650         if (pxafb_lcd_power)
 651                 pxafb_lcd_power(on);
 652 }
 653
 654 static void pxafb_setup_gpio(struct pxafb_info *fbi)
 655 {
 656         int gpio, ldd_bits;
 657         unsigned int lccr0 = fbi->lccr0;
 658
 659         /*
 660          * setup is based on type of panel supported
 661         */
 662
 663         /* 4 bit interface */
 664         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 665             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
 666             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
 667                 ldd_bits = 4;
 668
 669         /* 8 bit interface */
 670         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 671                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
 672                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 673                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
 674                 ldd_bits = 8;
 675
 676         /* 16 bit interface */
 677         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 678                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
 679                 ldd_bits = 16;
 680
 681         else {
 682                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
 683                 return;
 684         }
 685
 686         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
 687                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
 688         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
 689         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
 690         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
 691         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
 692 }
 693
 694 static void pxafb_enable_controller(struct pxafb_info *fbi)
 695 {
 696         DPRINTK("Enabling LCD controller\n");
 697         DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
 698         DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
 699         DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
 700         DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
 701         DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
 702         DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
 703
 704         /* Sequence from 11.7.10 */
 705         LCCR3 = fbi->reg_lccr3;
 706         LCCR2 = fbi->reg_lccr2;
 707         LCCR1 = fbi->reg_lccr1;
 708         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
 709
 710         FDADR0 = fbi->fdadr0;
 711         FDADR1 = fbi->fdadr1;
 712         LCCR0 |= LCCR0_ENB;
 713
 714         DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
 715         DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
 716         DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
 717         DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
 718         DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
 719         DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
 720 }
 721
 722 static void pxafb_disable_controller(struct pxafb_info *fbi)
 723 {
 724         DECLARE_WAITQUEUE(wait, current);
 725
 726         DPRINTK("Disabling LCD controller\n");
 727
 728         add_wait_queue(&fbi->ctrlr_wait, &wait);
 729         set_current_state(TASK_UNINTERRUPTIBLE);
 730
 731         LCSR = 0xffffffff;      /* Clear LCD Status Register */
 732         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
 733         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
 734
 735         schedule_timeout(20 * HZ / 1000);
 736         remove_wait_queue(&fbi->ctrlr_wait, &wait);
 737 }
 738
 739 /*
 740  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
 741  */
 742 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
 743 {
 744         struct pxafb_info *fbi = dev_id;
 745         unsigned int lcsr = LCSR;
 746
 747         if (lcsr & LCSR_LDD) {
 748                 LCCR0 |= LCCR0_LDM;
 749                 wake_up(&fbi->ctrlr_wait);
 750         }
 751
 752         LCSR = lcsr;
 753         return IRQ_HANDLED;
 754 }
 755
 756 /*
 757  * This function must be called from task context only, since it will
 758  * sleep when disabling the LCD controller, or if we get two contending
 759  * processes trying to alter state.
 760  */
 761 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
 762 {
 763         u_int old_state;
 764
 765         down(&fbi->ctrlr_sem);
 766
 767         old_state = fbi->state;
 768
 769         /*
 770          * Hack around fbcon initialisation.
 771          */
 772         if (old_state == C_STARTUP && state == C_REENABLE)
 773                 state = C_ENABLE;
 774
 775         switch (state) {
 776         case C_DISABLE_CLKCHANGE:
 777                 /*
 778                  * Disable controller for clock change.  If the
 779                  * controller is already disabled, then do nothing.
 780                  */
 781                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
 782                         fbi->state = state;
 783                         //TODO __pxafb_lcd_power(fbi, 0);
 784                         pxafb_disable_controller(fbi);
 785                 }
 786                 break;
 787
 788         case C_DISABLE_PM:
 789         case C_DISABLE:
 790                 /*
 791                  * Disable controller
 792                  */
 793                 if (old_state != C_DISABLE) {
 794                         fbi->state = state;
 795                         __pxafb_backlight_power(fbi, 0);
 796                         __pxafb_lcd_power(fbi, 0);
 797                         if (old_state != C_DISABLE_CLKCHANGE)
 798                                 pxafb_disable_controller(fbi);
 799                 }
 800                 break;
 801
 802         case C_ENABLE_CLKCHANGE:
 803                 /*
 804                  * Enable the controller after clock change.  Only
 805                  * do this if we were disabled for the clock change.
 806                  */
 807                 if (old_state == C_DISABLE_CLKCHANGE) {
 808                         fbi->state = C_ENABLE;
 809                         pxafb_enable_controller(fbi);
 810                         //TODO __pxafb_lcd_power(fbi, 1);
 811                 }
 812                 break;
 813
 814         case C_REENABLE:
 815                 /*
 816                  * Re-enable the controller only if it was already
 817                  * enabled.  This is so we reprogram the control
 818                  * registers.
 819                  */
 820                 if (old_state == C_ENABLE) {
 821                         pxafb_disable_controller(fbi);
 822                         pxafb_setup_gpio(fbi);
 823                         pxafb_enable_controller(fbi);
 824                 }
 825                 break;
 826
 827         case C_ENABLE_PM:
 828                 /*
 829                  * Re-enable the controller after PM.  This is not
 830                  * perfect - think about the case where we were doing
 831                  * a clock change, and we suspended half-way through.
 832                  */
 833                 if (old_state != C_DISABLE_PM)
 834                         break;
 835                 /* fall through */
 836
 837         case C_ENABLE:
 838                 /*
 839                  * Power up the LCD screen, enable controller, and
 840                  * turn on the backlight.
 841                  */
 842                 if (old_state != C_ENABLE) {
 843                         fbi->state = C_ENABLE;
 844                         pxafb_setup_gpio(fbi);
 845                         pxafb_enable_controller(fbi);
 846                         __pxafb_lcd_power(fbi, 1);
 847                         __pxafb_backlight_power(fbi, 1);
 848                 }
 849                 break;
 850         }
 851         up(&fbi->ctrlr_sem);
 852 }
 853
 854 /*
 855  * Our LCD controller task (which is called when we blank or unblank)
 856  * via keventd.
 857  */
 858 static void pxafb_task(void *dummy)
 859 {
 860         struct pxafb_info *fbi = dummy;
 861         u_int state = xchg(&fbi->task_state, -1);
 862
 863         set_ctrlr_state(fbi, state);
 864 }
 865
 866 #ifdef CONFIG_CPU_FREQ
 867 /*
 868  * CPU clock speed change handler.  We need to adjust the LCD timing
 869  * parameters when the CPU clock is adjusted by the power management
 870  * subsystem.
 871  *
 872  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
 873  */
 874 static int
 875 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
 876 {
 877         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
 878         //TODO struct cpufreq_freqs *f = data;
 879         u_int pcd;
 880
 881         switch (val) {
 882         case CPUFREQ_PRECHANGE:
 883                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
 884                 break;
 885
 886         case CPUFREQ_POSTCHANGE:
 887                 pcd = get_pcd(fbi->fb.var.pixclock);
 888                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
 889                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
 890                 break;
 891         }
 892         return 0;
 893 }
 894
 895 static int
 896 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
 897 {
 898         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
 899         struct fb_var_screeninfo *var = &fbi->fb.var;
 900         struct cpufreq_policy *policy = data;
 901
 902         switch (val) {
 903         case CPUFREQ_ADJUST:
 904         case CPUFREQ_INCOMPATIBLE:
 905                 printk(KERN_DEBUG "min dma period: %d ps, "
 906                         "new clock %d kHz\n", pxafb_display_dma_period(var),
 907                         policy->max);
 908                 // TODO: fill in min/max values
 909                 break;
 910 #if 0
 911         case CPUFREQ_NOTIFY:
 912                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
 913                 do {} while(0);
 914                 /* todo: panic if min/max values aren't fulfilled
 915                  * [can't really happen unless there's a bug in the
 916                  * CPU policy verification process *
 917                  */
 918                 break;
 919 #endif
 920         }
 921         return 0;
 922 }
 923 #endif
 924
 925 #ifdef CONFIG_PM
 926 /*
 927  * Power management hooks.  Note that we won't be called from IRQ context,
 928  * unlike the blank functions above, so we may sleep.
 929  */
 930 static int pxafb_suspend(struct device *dev, u32 state, u32 level)
 931 {
 932         struct pxafb_info *fbi = dev_get_drvdata(dev);
 933
 934         if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
 935                 set_ctrlr_state(fbi, C_DISABLE_PM);
 936         return 0;
 937 }
 938
 939 static int pxafb_resume(struct device *dev, u32 level)
 940 {
 941         struct pxafb_info *fbi = dev_get_drvdata(dev);
 942
 943         if (level == RESUME_ENABLE)
 944                 set_ctrlr_state(fbi, C_ENABLE_PM);
 945         return 0;
 946 }
 947 #else
 948 #define pxafb_suspend   NULL
 949 #define pxafb_resume    NULL
 950 #endif
 951
 952 /*
 953  * pxafb_map_video_memory():
 954  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 955  *      remapped into a non-cached, non-buffered, memory region to
 956  *      allow palette and pixel writes to occur without flushing the
 957  *      cache.  Once this area is remapped, all virtual memory
 958  *      access to the video memory should occur at the new region.
 959  */
 960 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
 961 {
 962         u_long palette_mem_size;
 963
 964         /*
 965          * We reserve one page for the palette, plus the size
 966          * of the framebuffer.
 967          */
 968         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
 969         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
 970                                               &fbi->map_dma, GFP_KERNEL);
 971
 972         if (fbi->map_cpu) {
 973                 /* prevent initial garbage on screen */
 974                 memset(fbi->map_cpu, 0, fbi->map_size);
 975                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
 976                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
 977                 /*
 978                  * FIXME: this is actually the wrong thing to place in
 979                  * smem_start.  But fbdev suffers from the problem that
 980                  * it needs an API which doesn't exist (in this case,
 981                  * dma_writecombine_mmap)
 982                  */
 983                 fbi->fb.fix.smem_start = fbi->screen_dma;
 984
 985                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
 986
 987                 palette_mem_size = fbi->palette_size * sizeof(u16);
 988                 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 989
 990                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
 991                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
 992         }
 993
 994         return fbi->map_cpu ? 0 : -ENOMEM;
 995 }
 996
 997 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
 998 {
 999         struct pxafb_info *fbi;
1000         void *addr;
1001         struct pxafb_mach_info *inf = dev->platform_data;
1002
1003         /* Alloc the pxafb_info and pseudo_palette in one step */
1004         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1005         if (!fbi)
1006                 return NULL;
1007
1008         memset(fbi, 0, sizeof(struct pxafb_info));
1009         fbi->dev = dev;
1010
1011         strcpy(fbi->fb.fix.id, PXA_NAME);
1012
1013         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1014         fbi->fb.fix.type_aux    = 0;
1015         fbi->fb.fix.xpanstep    = 0;
1016         fbi->fb.fix.ypanstep    = 0;
1017         fbi->fb.fix.ywrapstep   = 0;
1018         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1019
1020         fbi->fb.var.nonstd      = 0;
1021         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1022         fbi->fb.var.height      = -1;
1023         fbi->fb.var.width       = -1;
1024         fbi->fb.var.accel_flags = 0;
1025         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1026
1027         fbi->fb.fbops           = &pxafb_ops;
1028         fbi->fb.flags           = FBINFO_DEFAULT;
1029         fbi->fb.node            = -1;
1030
1031         addr = fbi;
1032         addr = addr + sizeof(struct pxafb_info);
1033         fbi->fb.pseudo_palette  = addr;
1034
1035         fbi->max_xres                   = inf->xres;
1036         fbi->fb.var.xres                = inf->xres;
1037         fbi->fb.var.xres_virtual        = inf->xres;
1038         fbi->max_yres                   = inf->yres;
1039         fbi->fb.var.yres                = inf->yres;
1040         fbi->fb.var.yres_virtual        = inf->yres;
1041         fbi->max_bpp                    = inf->bpp;
1042         fbi->fb.var.bits_per_pixel      = inf->bpp;
1043         fbi->fb.var.pixclock            = inf->pixclock;
1044         fbi->fb.var.hsync_len           = inf->hsync_len;
1045         fbi->fb.var.left_margin         = inf->left_margin;
1046         fbi->fb.var.right_margin        = inf->right_margin;
1047         fbi->fb.var.vsync_len           = inf->vsync_len;
1048         fbi->fb.var.upper_margin        = inf->upper_margin;
1049         fbi->fb.var.lower_margin        = inf->lower_margin;
1050         fbi->fb.var.sync                = inf->sync;
1051         fbi->fb.var.grayscale           = inf->cmap_greyscale;
1052         fbi->cmap_inverse               = inf->cmap_inverse;
1053         fbi->cmap_static                = inf->cmap_static;
1054         fbi->lccr0                      = inf->lccr0;
1055         fbi->lccr3                      = inf->lccr3;
1056         fbi->state                      = C_STARTUP;
1057         fbi->task_state                 = (u_char)-1;
1058         fbi->fb.fix.smem_len            = fbi->max_xres * fbi->max_yres *
1059                                           fbi->max_bpp / 8;
1060
1061         init_waitqueue_head(&fbi->ctrlr_wait);
1062         INIT_WORK(&fbi->task, pxafb_task, fbi);
1063         init_MUTEX(&fbi->ctrlr_sem);
1064
1065         return fbi;
1066 }
1067
1068 #ifdef CONFIG_FB_PXA_PARAMETERS
1069 static int __init pxafb_parse_options(struct device *dev, char *options)
1070 {
1071         struct pxafb_mach_info *inf = dev->platform_data;
1072         char *this_opt;
1073
1074         if (!options || !*options)
1075                 return 0;
1076
1077         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1078
1079         /* could be made table driven or similar?... */
1080         while ((this_opt = strsep(&options, ",")) != NULL) {
1081                 if (!strncmp(this_opt, "mode:", 5)) {
1082                         const char *name = this_opt+5;
1083                         unsigned int namelen = strlen(name);
1084                         int res_specified = 0, bpp_specified = 0;
1085                         unsigned int xres = 0, yres = 0, bpp = 0;
1086                         int yres_specified = 0;
1087                         int i;
1088                         for (i = namelen-1; i >= 0; i--) {
1089                                 switch (name[i]) {
1090                                 case '-':
1091                                         namelen = i;
1092                                         if (!bpp_specified && !yres_specified) {
1093                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1094                                                 bpp_specified = 1;
1095                                         } else
1096                                                 goto done;
1097                                         break;
1098                                 case 'x':
1099                                         if (!yres_specified) {
1100                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1101                                                 yres_specified = 1;
1102                                         } else
1103                                                 goto done;
1104                                         break;
1105                                 case '0'...'9':
1106                                         break;
1107                                 default:
1108                                         goto done;
1109                                 }
1110                         }
1111                         if (i < 0 && yres_specified) {
1112                                 xres = simple_strtoul(name, NULL, 0);
1113                                 res_specified = 1;
1114                         }
1115                 done:
1116                         if (res_specified) {
1117                                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1118                                 inf->xres = xres; inf->yres = yres;
1119                         }
1120                         if (bpp_specified)
1121                                 switch (bpp) {
1122                                 case 1:
1123                                 case 2:
1124                                 case 4:
1125                                 case 8:
1126                                 case 16:
1127                                         inf->bpp = bpp;
1128                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1129                                         break;
1130                                 default:
1131                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1132                                 }
1133                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1134                         inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1135                         dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1136                 } else if (!strncmp(this_opt, "left:", 5)) {
1137                         inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1138                         dev_info(dev, "override left: %u\n", inf->left_margin);
1139                 } else if (!strncmp(this_opt, "right:", 6)) {
1140                         inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1141                         dev_info(dev, "override right: %u\n", inf->right_margin);
1142                 } else if (!strncmp(this_opt, "upper:", 6)) {
1143                         inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1144                         dev_info(dev, "override upper: %u\n", inf->upper_margin);
1145                 } else if (!strncmp(this_opt, "lower:", 6)) {
1146                         inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1147                         dev_info(dev, "override lower: %u\n", inf->lower_margin);
1148                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1149                         inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1150                         dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1151                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1152                         inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1153                         dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1154                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1155                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1156                                 dev_info(dev, "override hsync: Active Low\n");
1157                                 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1158                         } else {
1159                                 dev_info(dev, "override hsync: Active High\n");
1160                                 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1161                         }
1162                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1163                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1164                                 dev_info(dev, "override vsync: Active Low\n");
1165                                 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1166                         } else {
1167                                 dev_info(dev, "override vsync: Active High\n");
1168                                 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1169                         }
1170                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1171                         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1172                                 dev_info(dev, "override double pixel clock: false\n");
1173                                 inf->lccr3 &= ~LCCR3_DPC;
1174                         } else {
1175                                 dev_info(dev, "override double pixel clock: true\n");
1176                                 inf->lccr3 |= LCCR3_DPC;
1177                         }
1178                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1179                         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1180                                 dev_info(dev, "override output enable: active low\n");
1181                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1182                         } else {
1183                                 dev_info(dev, "override output enable: active high\n");
1184                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1185                         }
1186                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1187                         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1188                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1189                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1190                         } else {
1191                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1192                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1193                         }
1194                 } else if (!strncmp(this_opt, "color", 5)) {
1195                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1196                 } else if (!strncmp(this_opt, "mono", 4)) {
1197                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1198                 } else if (!strncmp(this_opt, "active", 6)) {
1199                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1200                 } else if (!strncmp(this_opt, "passive", 7)) {
1201                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1202                 } else if (!strncmp(this_opt, "single", 6)) {
1203                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1204                 } else if (!strncmp(this_opt, "dual", 4)) {
1205                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1206                 } else if (!strncmp(this_opt, "4pix", 4)) {
1207                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1208                 } else if (!strncmp(this_opt, "8pix", 4)) {
1209                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1210                 } else {
1211                         dev_err(dev, "unknown option: %s\n", this_opt);
1212                         return -EINVAL;
1213                 }
1214         }
1215         return 0;
1216
1217 }
1218 #endif
1219
1220 int __init pxafb_probe(struct device *dev)
1221 {
1222         struct pxafb_info *fbi;
1223         struct pxafb_mach_info *inf;
1224         int ret;
1225
1226         dev_dbg(dev, "pxafb_probe\n");
1227
1228         inf = dev->platform_data;
1229         ret = -ENOMEM;
1230         fbi = NULL;
1231         if (!inf)
1232                 goto failed;
1233
1234 #ifdef CONFIG_FB_PXA_PARAMETERS
1235         ret = pxafb_parse_options(dev, g_options);
1236         if (ret < 0)
1237                 goto failed;
1238 #endif
1239
1240 #ifdef DEBUG_VAR
1241         /* Check for various illegal bit-combinations. Currently only
1242          * a warning is given. */
1243
1244         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1245                 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1246                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1247         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1248                 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1249                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1250         if (inf->lccr0 & LCCR0_DPD &&
1251             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1252              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1253              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1254                 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1255                          " single panel mode\n");
1256         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1257             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1258                 dev_warn(dev, "Dual panel only valid in passive mode\n");
1259         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1260              (inf->upper_margin || inf->lower_margin))
1261                 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1262 #endif
1263
1264         dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1265         if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1266                 dev_err(dev, "Invalid resolution or bit depth\n");
1267                 ret = -EINVAL;
1268                 goto failed;
1269         }
1270         pxafb_backlight_power = inf->pxafb_backlight_power;
1271         pxafb_lcd_power = inf->pxafb_lcd_power;
1272         fbi = pxafb_init_fbinfo(dev);
1273         if (!fbi) {
1274                 dev_err(dev, "Failed to initialize framebuffer device\n");
1275                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1276                 goto failed;
1277         }
1278
1279         /* Initialize video memory */
1280         ret = pxafb_map_video_memory(fbi);
1281         if (ret) {
1282                 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1283                 ret = -ENOMEM;
1284                 goto failed;
1285         }
1286         /* enable LCD controller clock */
1287         pxa_set_cken(CKEN16_LCD, 1);
1288
1289         ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1290         if (ret) {
1291                 dev_err(dev, "request_irq failed: %d\n", ret);
1292                 ret = -EBUSY;
1293                 goto failed;
1294         }
1295
1296         /*
1297          * This makes sure that our colour bitfield
1298          * descriptors are correctly initialised.
1299          */
1300         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1301         pxafb_set_par(&fbi->fb);
1302
1303         dev_set_drvdata(dev, fbi);
1304
1305         ret = register_framebuffer(&fbi->fb);
1306         if (ret < 0) {
1307                 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1308                 goto failed;
1309         }
1310
1311 #ifdef CONFIG_PM
1312         // TODO
1313 #endif
1314
1315 #ifdef CONFIG_CPU_FREQ
1316         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1317         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1318         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1319         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1320 #endif
1321
1322         /*
1323          * Ok, now enable the LCD controller
1324          */
1325         set_ctrlr_state(fbi, C_ENABLE);
1326
1327         return 0;
1328
1329 failed:
1330         dev_set_drvdata(dev, NULL);
1331         if (fbi)
1332                 kfree(fbi);
1333         return ret;
1334 }
1335
1336 static struct device_driver pxafb_driver = {
1337         .name           = "pxa2xx-fb",
1338         .bus            = &platform_bus_type,
1339         .probe          = pxafb_probe,
1340 #ifdef CONFIG_PM
1341         .suspend        = pxafb_suspend,
1342         .resume         = pxafb_resume,
1343 #endif
1344 };
1345
1346 #ifndef MODULE
1347 int __devinit pxafb_setup(char *options)
1348 {
1349 # ifdef CONFIG_FB_PXA_PARAMETERS
1350         strlcpy(g_options, options, sizeof(g_options));
1351 # endif
1352         return 0;
1353 }
1354 #else
1355 # ifdef CONFIG_FB_PXA_PARAMETERS
1356 module_param_string(options, g_options, sizeof(g_options), 0);
1357 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1358 # endif
1359 #endif
1360
1361 int __devinit pxafb_init(void)
1362 {
1363 #ifndef MODULE
1364         char *option = NULL;
1365
1366         if (fb_get_options("pxafb", &option))
1367                 return -ENODEV;
1368         pxafb_setup(option);
1369 #endif
1370         return driver_register(&pxafb_driver);
1371 }
1372
1373 module_init(pxafb_init);
1374
1375 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1376 MODULE_LICENSE("GPL");