2 * drivers/video/radeonfb.c
3 * framebuffer driver for ATI Radeon chipset video boards
5 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
9 * 2000-08-03 initial version 0.0.1
10 * 2000-09-10 more bug fixes, public release 0.0.5
11 * 2001-02-19 mode bug fixes, 0.0.7
12 * 2001-07-05 fixed scrolling issues, engine initialization,
13 * and minor mode tweaking, 0.0.9
14 * 2001-09-07 Radeon VE support, Nick Kurshev
15 * blanking, pan_display, and cmap fixes, 0.1.0
16 * 2001-10-10 Radeon 7500 and 8500 support, and experimental
17 * flat panel support, 0.1.1
18 * 2001-11-17 Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
19 * 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
20 * 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
21 * 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
22 * 2002-06-02 console switching, mode set fixes, accel fixes
23 * 2002-06-03 MTRR support, Peter Horton, 0.1.5
24 * 2002-09-21 rv250, r300, m9 initial support,
25 * added mirror option, 0.1.6
27 * Special thanks to ATI DevRel team for their hardware donations.
32 #define RADEON_VERSION "0.1.6"
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/errno.h>
39 #include <linux/string.h>
41 #include <linux/tty.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
45 #include <linux/ioport.h>
46 #include <linux/init.h>
47 #include <linux/pci.h>
48 #include <linux/vmalloc.h>
51 #include <asm/uaccess.h>
52 #if defined(__powerpc__)
54 #include <asm/pci-bridge.h>
58 #include <linux/nvram.h>
61 #ifdef CONFIG_PMAC_BACKLIGHT
62 #include <asm/backlight.h>
65 #ifdef CONFIG_BOOTX_TEXT
66 #include <asm/btext.h>
70 #include <linux/adb.h>
71 #include <linux/pmu.h>
74 #endif /* __powerpc__ */
80 #include <video/radeon.h>
81 #include <linux/radeonfb.h>
88 #define RTRACE if(0) printk
92 #undef CONFIG_PMAC_PBOOK
142 static struct radeon_chip_info {
145 } radeon_chip_info[] __devinitdata = {
146 { "QD", RADEON_R100 },
147 { "QE", RADEON_R100 },
148 { "QF", RADEON_R100 },
149 { "QG", RADEON_R100 },
150 { "VE QY", RADEON_RV100 },
151 { "VE QZ", RADEON_RV100 },
152 { "M7 LW", RADEON_M7 },
153 { "M7 LX", RADEON_M7 },
154 { "M6 LY", RADEON_M6 },
155 { "M6 LZ", RADEON_M6 },
156 { "8500 QL", RADEON_R200 },
157 { "8500 QN", RADEON_R200 },
158 { "8500 QO", RADEON_R200 },
159 { "8500 Ql", RADEON_R200 },
160 { "8500 BB", RADEON_R200 },
161 { "7500 QW", RADEON_RV200 },
162 { "7500 QX", RADEON_RV200 },
163 { "9000 Id", RADEON_RV250 },
164 { "9000 Ie", RADEON_RV250 },
165 { "9000 If", RADEON_RV250 },
166 { "9000 Ig", RADEON_RV250 },
167 { "M9 Ld", RADEON_M9 },
168 { "M9 Le", RADEON_M9 },
169 { "M9 Lf", RADEON_M9 },
170 { "M9 Lg", RADEON_M9 },
171 { "9700 ND", RADEON_R300 },
172 { "9700 NE", RADEON_R300 },
173 { "9700 NF", RADEON_R300 },
174 { "9700 NG", RADEON_R300 },
175 { "9100 QM", RADEON_R200 }
185 MT_CTV, /* composite TV */
186 MT_STV /* S-Video out */
190 static struct pci_device_id radeonfb_pci_table[] = {
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
192 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
194 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
196 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
198 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
200 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
202 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
204 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
206 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
208 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
210 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ya, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ya},
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Yd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Yd},
214 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
216 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
218 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
225 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234 /* these common regs are cleared before mode setting so they do not
235 * interfere with anything
237 static reg_val common_regs[] = {
239 { OVR_WID_LEFT_RIGHT, 0 },
240 { OVR_WID_TOP_BOTTOM, 0 },
241 { OV0_SCALE_CNTL, 0 },
246 { CAP0_TRIG_CNTL, 0 },
249 static reg_val common_regs_m6[] = {
251 { OVR_WID_LEFT_RIGHT, 0 },
252 { OVR_WID_TOP_BOTTOM, 0 },
253 { OV0_SCALE_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 }
262 u8 accelerator_entry;
264 u16 VGA_table_offset;
265 u16 POST_table_offset;
271 u16 PCLK_ref_divider;
275 u16 MCLK_ref_divider;
279 u16 XCLK_ref_divider;
282 } __attribute__ ((packed)) PLL_BLOCK;
309 u32 crtc_h_total_disp;
310 u32 crtc_h_sync_strt_wid;
311 u32 crtc_v_total_disp;
312 u32 crtc_v_sync_strt_wid;
331 /* Flat panel regs */
332 u32 fp_crtc_h_total_disp;
333 u32 fp_crtc_v_total_disp;
335 u32 fp_h_sync_strt_wid;
338 u32 fp_v_sync_strt_wid;
343 u32 tmds_transmitter_cntl;
345 #if defined(__BIG_ENDIAN)
351 struct radeonfb_info {
354 struct radeon_regs state;
355 struct radeon_regs init_state;
360 unsigned long mmio_base_phys;
361 unsigned long fb_base_phys;
363 unsigned long mmio_base;
364 unsigned long fb_base;
366 struct pci_dev *pdev;
369 unsigned char *bios_seg;
371 u32 pseudo_palette[17];
372 struct { u8 red, green, blue, pad; } palette[256];
378 int pitch, bpp, depth;
379 int xres, yres, pixclock;
380 int xres_virtual, yres_virtual;
390 int panel_xres, panel_yres;
392 int hOver_plus, hSync_width, hblank;
393 int vOver_plus, vSync_width, vblank;
394 int hAct_high, vAct_high, interlaced;
397 u32 dp_gui_master_cntl;
400 int pll_output_freq, post_div, fb_div;
406 #ifdef CONFIG_PMAC_PBOOK
410 #endif /* CONFIG_PMAC_PBOOK */
413 struct radeonfb_info *next;
417 static struct fb_var_screeninfo radeonfb_default_var = {
418 640, 480, 640, 480, 0, 0, 8, 0,
419 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
420 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
421 0, FB_VMODE_NONINTERLACED
428 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
429 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
430 #define INREG(addr) readl((rinfo->mmio_base)+addr)
431 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
433 #define OUTPLL(addr,val) \
435 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
436 OUTREG(CLOCK_CNTL_DATA, val); \
439 #define OUTPLLP(addr,val,mask) \
441 unsigned int _tmp = INPLL(addr); \
444 OUTPLL(addr, _tmp); \
447 #define OUTREGP(addr,val,mask) \
449 unsigned int _tmp = INREG(addr); \
452 OUTREG(addr, _tmp); \
456 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
458 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
459 return (INREG(CLOCK_CNTL_DATA));
462 #define INPLL(addr) _INPLL(rinfo, addr)
464 #define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
465 (rinfo->dviDisp_type != MT_STV) && \
466 (rinfo->dviDisp_type != MT_CTV) ? \
467 rinfo->dviDisp_type : rinfo->crtDisp_type)
469 static char *GET_MON_NAME(int type)
502 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
507 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
510 for (i=0; i < 2000000; i++) {
511 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
517 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
521 for (i=0; i<2000000; i++)
522 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
527 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
531 /* ensure FIFO is empty before waiting for idle */
532 _radeon_fifo_wait (rinfo, 64);
534 for (i=0; i<2000000; i++) {
535 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
536 radeon_engine_flush (rinfo);
543 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
544 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
552 static __inline__ u32 radeon_get_dstbpp(u16 depth)
569 static inline int var_to_depth(const struct fb_var_screeninfo *var)
571 if (var->bits_per_pixel != 16)
572 return var->bits_per_pixel;
573 return (var->green.length == 6) ? 16 : 15;
577 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
579 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
581 radeon_engine_flush (rinfo);
583 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
584 mclk_cntl = INPLL(MCLK_CNTL);
586 OUTPLL(MCLK_CNTL, (mclk_cntl |
593 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
595 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
603 INREG(RBBM_SOFT_RESET);
604 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
612 INREG(RBBM_SOFT_RESET);
614 OUTPLL(MCLK_CNTL, mclk_cntl);
615 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
616 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
621 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
624 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
648 static __inline__ int round_div(int num, int den)
650 return (num + (den / 2)) / den;
655 static __inline__ int min_bits_req(int val)
671 static __inline__ int _max(int val1, int val2)
685 static char *mode_option __initdata;
686 static char noaccel = 0;
687 static char mirror = 0;
688 static int panel_yres __initdata = 0;
689 static char force_dfp __initdata = 0;
690 static struct radeonfb_info *board_list = NULL;
691 static char nomtrr __initdata = 0;
697 static void radeon_save_state (struct radeonfb_info *rinfo,
698 struct radeon_regs *save);
699 static void radeon_engine_init (struct radeonfb_info *rinfo);
700 static void radeon_write_mode (struct radeonfb_info *rinfo,
701 struct radeon_regs *mode);
702 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
703 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
704 static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
705 static char *radeon_find_rom(struct radeonfb_info *rinfo);
706 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
707 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
708 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
709 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
710 static void radeon_get_EDID(struct radeonfb_info *rinfo);
711 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
712 static void radeon_update_default_var(struct radeonfb_info *rinfo);
716 static int radeon_read_OF (struct radeonfb_info *rinfo);
717 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
718 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
720 #ifdef CONFIG_PMAC_PBOOK
721 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
722 static struct pmu_sleep_notifier radeon_sleep_notifier = {
723 radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
725 #endif /* CONFIG_PMAC_PBOOK */
726 #ifdef CONFIG_PMAC_BACKLIGHT
727 static int radeon_set_backlight_enable(int on, int level, void *data);
728 static int radeon_set_backlight_level(int level, void *data);
729 static struct backlight_controller radeon_backlight_controller = {
730 radeon_set_backlight_enable,
731 radeon_set_backlight_level
733 #endif /* CONFIG_PMAC_BACKLIGHT */
735 #endif /* CONFIG_PPC_OF */
738 static char *radeon_find_rom(struct radeonfb_info *rinfo)
740 #if defined(__i386__)
746 char aty_rom_sig[] = "761295520";
747 char *radeon_sig[] = {
752 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
756 rom_base = (char *)ioremap(segstart, 0x1000);
758 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
769 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
770 if (aty_rom_sig[0] == *rom)
771 if (strncmp(aty_rom_sig, rom,
772 strlen(aty_rom_sig)) == 0)
782 for (i = 0; (i < 512) && (stage != 4); i++) {
783 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
784 if (radeon_sig[j][0] == *rom)
785 if (strncmp(radeon_sig[j], rom,
786 strlen(radeon_sig[j])) == 0) {
807 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
811 u16 bios_header_offset, pll_info_offset;
815 bios_header = bios_seg + 0x48L;
816 header_ptr = bios_header;
818 bios_header_offset = readw(header_ptr);
819 bios_header = bios_seg + bios_header_offset;
822 header_ptr = bios_header;
823 pll_info_offset = readw(header_ptr);
824 header_ptr = bios_seg + pll_info_offset;
826 memcpy_fromio(&pll, header_ptr, 50);
828 rinfo->pll.xclk = (u32)pll.XCLK;
829 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
830 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
831 rinfo->pll.ppll_min = pll.PCLK_min_freq;
832 rinfo->pll.ppll_max = pll.PCLK_max_freq;
834 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
835 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
838 if (radeon_read_OF(rinfo)) {
839 unsigned int tmp, Nx, M, ref_div, xclk;
841 tmp = INPLL(X_MPLL_REF_FB_DIV);
842 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
844 Nx = (tmp & 0xff00) >> 8;
846 xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
849 rinfo->pll.xclk = xclk;
850 rinfo->pll.ref_div = ref_div;
851 rinfo->pll.ppll_min = 12000;
852 rinfo->pll.ppll_max = 35000;
854 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
855 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
860 /* no BIOS or BIOS not found, use defaults */
861 switch (rinfo->chipset) {
862 case PCI_DEVICE_ID_ATI_RADEON_QW:
863 case PCI_DEVICE_ID_ATI_RADEON_QX:
864 rinfo->pll.ppll_max = 35000;
865 rinfo->pll.ppll_min = 12000;
866 rinfo->pll.xclk = 23000;
867 rinfo->pll.ref_div = 12;
868 rinfo->pll.ref_clk = 2700;
870 case PCI_DEVICE_ID_ATI_RADEON_QL:
871 case PCI_DEVICE_ID_ATI_RADEON_QN:
872 case PCI_DEVICE_ID_ATI_RADEON_QO:
873 case PCI_DEVICE_ID_ATI_RADEON_Ql:
874 case PCI_DEVICE_ID_ATI_RADEON_BB:
875 rinfo->pll.ppll_max = 35000;
876 rinfo->pll.ppll_min = 12000;
877 rinfo->pll.xclk = 27500;
878 rinfo->pll.ref_div = 12;
879 rinfo->pll.ref_clk = 2700;
881 case PCI_DEVICE_ID_ATI_RADEON_Id:
882 case PCI_DEVICE_ID_ATI_RADEON_Ie:
883 case PCI_DEVICE_ID_ATI_RADEON_If:
884 case PCI_DEVICE_ID_ATI_RADEON_Ig:
885 rinfo->pll.ppll_max = 35000;
886 rinfo->pll.ppll_min = 12000;
887 rinfo->pll.xclk = 25000;
888 rinfo->pll.ref_div = 12;
889 rinfo->pll.ref_clk = 2700;
891 case PCI_DEVICE_ID_ATI_RADEON_ND:
892 case PCI_DEVICE_ID_ATI_RADEON_NE:
893 case PCI_DEVICE_ID_ATI_RADEON_NF:
894 case PCI_DEVICE_ID_ATI_RADEON_NG:
895 rinfo->pll.ppll_max = 40000;
896 rinfo->pll.ppll_min = 20000;
897 rinfo->pll.xclk = 27000;
898 rinfo->pll.ref_div = 12;
899 rinfo->pll.ref_clk = 2700;
901 case PCI_DEVICE_ID_ATI_RADEON_QD:
902 case PCI_DEVICE_ID_ATI_RADEON_QE:
903 case PCI_DEVICE_ID_ATI_RADEON_QF:
904 case PCI_DEVICE_ID_ATI_RADEON_QG:
906 rinfo->pll.ppll_max = 35000;
907 rinfo->pll.ppll_min = 12000;
908 rinfo->pll.xclk = 16600;
909 rinfo->pll.ref_div = 67;
910 rinfo->pll.ref_clk = 2700;
914 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
915 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
920 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
925 rinfo->dviDisp_type = MT_DFP;
929 tmp = INREG(BIOS_4_SCRATCH);
930 printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
932 if (rinfo->hasCRTC2) {
933 /* primary DVI port */
935 rinfo->dviDisp_type = MT_DFP;
937 rinfo->dviDisp_type = MT_LCD;
938 else if (tmp & 0x200)
939 rinfo->dviDisp_type = MT_CRT;
941 rinfo->dviDisp_type = MT_CTV;
943 rinfo->dviDisp_type = MT_STV;
945 /* secondary CRT port */
947 rinfo->crtDisp_type = MT_CRT;
948 else if (tmp & 0x800)
949 rinfo->crtDisp_type = MT_DFP;
950 else if (tmp & 0x400)
951 rinfo->crtDisp_type = MT_LCD;
952 else if (tmp & 0x1000)
953 rinfo->crtDisp_type = MT_CTV;
954 else if (tmp & 0x2000)
955 rinfo->crtDisp_type = MT_STV;
957 rinfo->dviDisp_type = MT_NONE;
959 tmp = INREG(FP_GEN_CNTL);
961 if (tmp & FP_EN_TMDS)
962 rinfo->crtDisp_type = MT_DFP;
964 rinfo->crtDisp_type = MT_CRT;
970 static void radeon_get_EDID(struct radeonfb_info *rinfo)
973 if (!radeon_get_EDID_OF(rinfo))
974 RTRACE("radeonfb: could not retrieve EDID from OF\n");
976 /* XXX use other methods later */
982 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
984 struct device_node *dp;
985 unsigned char *pedid = NULL;
986 static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
989 dp = pci_device_to_OF_node(rinfo->pdev);
991 for (i = 0; propnames[i] != NULL; ++i) {
992 pedid = (unsigned char *)
993 get_property(dp, propnames[i], NULL);
1003 #endif /* CONFIG_PPC_OF */
1006 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
1008 unsigned char *block = rinfo->EDID;
1013 /* jump to the detailed timing block section */
1016 rinfo->clock = (block[0] + (block[1] << 8));
1017 rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1018 rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1019 rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1020 rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1021 rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1022 rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1023 rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1024 rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1025 rinfo->interlaced = ((block[17] & 0x80) >> 7);
1026 rinfo->synct = ((block[17] & 0x18) >> 3);
1027 rinfo->misc = ((block[17] & 0x06) >> 1);
1028 rinfo->hAct_high = rinfo->vAct_high = 0;
1029 if (rinfo->synct == 3) {
1030 if (rinfo->misc & 2)
1031 rinfo->hAct_high = 1;
1032 if (rinfo->misc & 1)
1033 rinfo->vAct_high = 1;
1036 printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1037 rinfo->panel_xres, rinfo->panel_yres);
1039 rinfo->got_dfpinfo = 1;
1045 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1047 struct fb_var_screeninfo *var = &radeonfb_default_var;
1049 var->xres = rinfo->panel_xres;
1050 var->yres = rinfo->panel_yres;
1051 var->xres_virtual = rinfo->panel_xres;
1052 var->yres_virtual = rinfo->panel_yres;
1053 var->xoffset = var->yoffset = 0;
1054 var->bits_per_pixel = 8;
1055 var->pixclock = 100000000 / rinfo->clock;
1056 var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1057 var->right_margin = rinfo->hOver_plus;
1058 var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1059 var->lower_margin = rinfo->vOver_plus;
1060 var->hsync_len = rinfo->hSync_width;
1061 var->vsync_len = rinfo->vSync_width;
1063 if (rinfo->synct == 3) {
1064 if (rinfo->hAct_high)
1065 var->sync |= FB_SYNC_HOR_HIGH_ACT;
1066 if (rinfo->vAct_high)
1067 var->sync |= FB_SYNC_VERT_HIGH_ACT;
1071 if (rinfo->interlaced)
1072 var->vmode |= FB_VMODE_INTERLACED;
1074 rinfo->use_default_var = 1;
1078 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1080 char *fpbiosstart, *tmp, *tmp0;
1084 if (!rinfo->bios_seg)
1087 if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1088 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1092 if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1093 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1098 stmp[i] = readb(tmp+i+1);
1100 printk("radeonfb: panel ID string: %s\n", stmp);
1101 rinfo->panel_xres = readw(tmp + 25);
1102 rinfo->panel_yres = readw(tmp + 27);
1103 printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1104 rinfo->panel_xres, rinfo->panel_yres);
1106 for(i=0; i<32; i++) {
1107 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1110 if ((readw(tmp0) == rinfo->panel_xres) &&
1111 (readw(tmp0+2) == rinfo->panel_yres)) {
1112 rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1113 rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1114 rinfo->hSync_width = readb(tmp0+23) * 8;
1115 rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1116 rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1117 rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1118 rinfo->clock = readw(tmp0+9);
1120 rinfo->got_dfpinfo = 1;
1130 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1133 unsigned short a, b;
1135 if (radeon_get_dfpinfo_BIOS(rinfo))
1136 radeon_update_default_var(rinfo);
1138 if (radeon_dfp_parse_EDID(rinfo))
1139 radeon_update_default_var(rinfo);
1141 if (!rinfo->got_dfpinfo) {
1143 * it seems all else has failed now and we
1144 * resort to probing registers for our DFP info
1147 rinfo->panel_yres = panel_yres;
1149 tmp = INREG(FP_VERT_STRETCH);
1151 rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1154 switch (rinfo->panel_yres) {
1156 rinfo->panel_xres = 640;
1159 rinfo->panel_xres = 800;
1162 #if defined(__powerpc__)
1163 if (rinfo->dviDisp_type == MT_LCD)
1164 rinfo->panel_xres = 1152;
1167 rinfo->panel_xres = 1024;
1170 rinfo->panel_xres = 1280;
1173 rinfo->panel_xres = 1400;
1176 rinfo->panel_xres = 1600;
1179 printk("radeonfb: Failed to detect DFP panel size\n");
1183 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1184 rinfo->panel_xres, rinfo->panel_yres);
1186 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1187 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1188 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1189 rinfo->hblank = (a - b + 1) * 8;
1191 tmp = INREG(FP_H_SYNC_STRT_WID);
1192 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1193 FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1194 rinfo->hOver_plus *= 8;
1195 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1196 FP_H_SYNC_WID_SHIFT);
1197 rinfo->hSync_width *= 8;
1198 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1199 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1200 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1201 rinfo->vblank = a - b /* + 24 */ ;
1203 tmp = INREG(FP_V_SYNC_STRT_WID);
1204 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1206 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1207 FP_V_SYNC_WID_SHIFT);
1216 #ifdef CONFIG_PPC_OF
1217 static int radeon_read_OF (struct radeonfb_info *rinfo)
1219 struct device_node *dp;
1222 dp = pci_device_to_OF_node(rinfo->pdev);
1224 xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
1226 rinfo->pll.ref_clk = *xtal / 10;
1236 static void radeon_engine_init (struct radeonfb_info *rinfo)
1240 /* disable 3D engine */
1241 OUTREG(RB3D_CNTL, 0);
1243 radeon_engine_reset ();
1245 radeon_fifo_wait (1);
1246 OUTREG(RB2D_DSTCACHE_MODE, 0);
1248 radeon_fifo_wait (1);
1249 temp = INREG(DEFAULT_PITCH_OFFSET);
1250 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1251 (rinfo->pitch << 0x16)));
1253 radeon_fifo_wait (1);
1254 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1256 radeon_fifo_wait (1);
1257 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1258 DEFAULT_SC_BOTTOM_MAX));
1260 temp = radeon_get_dstbpp(rinfo->depth);
1261 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1262 radeon_fifo_wait (1);
1263 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1264 GMC_BRUSH_SOLID_COLOR |
1265 GMC_SRC_DATATYPE_COLOR));
1267 radeon_fifo_wait (7);
1269 /* clear line drawing regs */
1270 OUTREG(DST_LINE_START, 0);
1271 OUTREG(DST_LINE_END, 0);
1273 /* set brush color regs */
1274 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1275 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1277 /* set source color regs */
1278 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1279 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1281 /* default write mask */
1282 OUTREG(DP_WRITE_MSK, 0xffffffff);
1284 radeon_engine_idle ();
1288 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1290 struct fb_info *info = &rinfo->info;
1291 struct fb_var_screeninfo var;
1293 var = radeonfb_default_var;
1294 if ((radeon_init_disp_var(rinfo, &var)) < 0)
1297 rinfo->depth = var_to_depth(&var);
1298 rinfo->bpp = var.bits_per_pixel;
1301 fb_alloc_cmap(&info->cmap, 256, 0);
1303 var.activate = FB_ACTIVATE_NOW;
1308 static int radeon_init_disp_var (struct radeonfb_info *rinfo,
1309 struct fb_var_screeninfo *var)
1313 fb_find_mode (var, &rinfo->info, mode_option,
1317 if (rinfo->use_default_var)
1318 /* We will use the modified default far */
1319 *var = radeonfb_default_var;
1322 fb_find_mode (var, &rinfo->info, "640x480-8@60",
1326 var->accel_flags &= ~FB_ACCELF_TEXT;
1328 var->accel_flags |= FB_ACCELF_TEXT;
1334 static int radeon_do_maximize(struct radeonfb_info *rinfo,
1335 struct fb_var_screeninfo *var,
1336 struct fb_var_screeninfo *v,
1351 /* use highest possible virtual resolution */
1352 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1353 printk("radeonfb: using max available virtual resolution\n");
1354 for (i=0; modes[i].xres != -1; i++) {
1355 if (modes[i].xres * nom / den * modes[i].yres <
1356 rinfo->video_ram / 2)
1359 if (modes[i].xres == -1) {
1360 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1363 v->xres_virtual = modes[i].xres;
1364 v->yres_virtual = modes[i].yres;
1366 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1367 v->xres_virtual, v->yres_virtual);
1368 } else if (v->xres_virtual == -1) {
1369 v->xres_virtual = (rinfo->video_ram * den /
1370 (nom * v->yres_virtual * 2)) & ~15;
1371 } else if (v->yres_virtual == -1) {
1372 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1373 v->yres_virtual = rinfo->video_ram * den /
1374 (nom * v->xres_virtual *2);
1376 if (v->xres_virtual * nom / den * v->yres_virtual >
1382 if (v->xres_virtual * nom / den >= 8192) {
1383 v->xres_virtual = 8192 * den / nom - 16;
1386 if (v->xres_virtual < v->xres)
1389 if (v->yres_virtual < v->yres)
1396 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
1398 struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
1399 struct fb_var_screeninfo v;
1402 memcpy (&v, var, sizeof (v));
1404 switch (v.bits_per_pixel) {
1406 v.bits_per_pixel = 8;
1409 v.bits_per_pixel = 16;
1412 #if 0 /* Doesn't seem to work */
1413 v.bits_per_pixel = 24;
1418 v.bits_per_pixel = 32;
1424 switch (var_to_depth(&v)) {
1427 v.red.offset = v.green.offset = v.blue.offset = 0;
1428 v.red.length = v.green.length = v.blue.length = 8;
1429 v.transp.offset = v.transp.length = 0;
1437 v.red.length = v.green.length = v.blue.length = 5;
1438 v.transp.offset = v.transp.length = 0;
1449 v.transp.offset = v.transp.length = 0;
1457 v.red.length = v.blue.length = v.green.length = 8;
1458 v.transp.offset = v.transp.length = 0;
1466 v.red.length = v.blue.length = v.green.length = 8;
1467 v.transp.offset = 24;
1468 v.transp.length = 8;
1471 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
1472 var->xres, var->yres, var->bits_per_pixel);
1476 if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
1484 if (v.xoffset > v.xres_virtual - v.xres)
1485 v.xoffset = v.xres_virtual - v.xres - 1;
1487 if (v.yoffset > v.yres_virtual - v.yres)
1488 v.yoffset = v.yres_virtual - v.yres - 1;
1490 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
1491 v.transp.offset = v.transp.length =
1492 v.transp.msb_right = 0;
1497 memcpy(var, &v, sizeof(v));
1503 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
1504 struct fb_info *info)
1506 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1508 if ((var->xoffset + var->xres > var->xres_virtual)
1509 || (var->yoffset + var->yres > var->yres_virtual))
1515 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
1516 * var->bits_per_pixel / 8) & ~7);
1521 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
1522 unsigned long arg, struct fb_info *info)
1524 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1531 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
1533 case FBIO_RADEON_SET_MIRROR:
1534 switch (rinfo->arch) {
1543 /* RADEON M6, RADEON_M7, RADEON_M9 */
1547 rc = get_user(value, (__u32*)arg);
1553 tmp = INREG(LVDS_GEN_CNTL);
1555 tmp |= (LVDS_ON | LVDS_BLON);
1557 tmp = INREG(LVDS_GEN_CNTL);
1559 tmp &= ~(LVDS_ON | LVDS_BLON);
1562 OUTREG(LVDS_GEN_CNTL, tmp);
1565 tmp = INREG(CRTC_EXT_CNTL);
1570 tmp = INREG(CRTC_EXT_CNTL);
1571 tmp &= ~CRTC_CRT_ON;
1576 OUTREG(CRTC_EXT_CNTL, tmp);
1579 case FBIO_RADEON_GET_MIRROR:
1580 switch (rinfo->arch) {
1589 /* RADEON M6, RADEON_M7, RADEON_M9 */
1593 tmp = INREG(LVDS_GEN_CNTL);
1594 if ((LVDS_ON | LVDS_BLON) & tmp)
1597 tmp = INREG(CRTC_EXT_CNTL);
1598 if (CRTC_CRT_ON & tmp)
1601 return put_user(value, (__u32*)arg);
1610 static int radeonfb_blank (int blank, struct fb_info *info)
1612 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1613 u32 val = INREG(CRTC_EXT_CNTL);
1614 u32 val2 = INREG(LVDS_GEN_CNTL);
1619 #ifdef CONFIG_PMAC_BACKLIGHT
1620 if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
1621 set_backlight_enable(!blank);
1627 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1629 val2 &= ~(LVDS_DISPLAY_DIS);
1632 case VESA_NO_BLANKING:
1634 case VESA_VSYNC_SUSPEND:
1635 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1637 case VESA_HSYNC_SUSPEND:
1638 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1640 case VESA_POWERDOWN:
1641 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1643 val2 |= (LVDS_DISPLAY_DIS);
1647 switch (rinfo->dviDisp_type) {
1649 OUTREG(LVDS_GEN_CNTL, val2);
1653 OUTREG(CRTC_EXT_CNTL, val);
1661 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1662 unsigned blue, unsigned transp, struct fb_info *info)
1664 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1665 u32 pindex, vclk_cntl;
1674 rinfo->palette[regno].red = red;
1675 rinfo->palette[regno].green = green;
1676 rinfo->palette[regno].blue = blue;
1681 if (!rinfo->asleep) {
1682 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1683 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1685 if (rinfo->bpp == 16) {
1688 if (rinfo->depth == 16 && regno > 63)
1690 if (rinfo->depth == 15 && regno > 31)
1693 /* For 565, the green component is mixed one order below */
1694 if (rinfo->depth == 16) {
1695 OUTREG(PALETTE_INDEX, pindex>>1);
1696 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1697 (green << 8) | (rinfo->palette[regno>>1].blue));
1698 green = rinfo->palette[regno<<1].green;
1702 if (rinfo->depth != 16 || regno < 32) {
1703 OUTREG(PALETTE_INDEX, pindex);
1704 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1707 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1710 switch (rinfo->depth) {
1712 ((u16 *) (info->pseudo_palette))[regno] =
1713 (regno << 10) | (regno << 5) | regno;
1716 ((u16 *) (info->pseudo_palette))[regno] =
1717 (regno << 11) | (regno << 6) | regno;
1720 ((u32 *) (info->pseudo_palette))[regno] =
1721 (regno << 16) | (regno << 8) | regno;
1724 i = (regno << 8) | regno;
1725 ((u32 *) (info->pseudo_palette))[regno] =
1735 static void radeon_save_state (struct radeonfb_info *rinfo,
1736 struct radeon_regs *save)
1739 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1740 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1741 save->dac_cntl = INREG(DAC_CNTL);
1742 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1743 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1744 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1745 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1746 save->crtc_pitch = INREG(CRTC_PITCH);
1747 #if defined(__BIG_ENDIAN)
1748 save->surface_cntl = INREG(SURFACE_CNTL);
1752 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1753 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1754 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1755 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1756 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1757 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1758 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1759 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1760 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1761 save->tmds_crc = INREG(TMDS_CRC);
1762 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1763 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1768 static int radeonfb_set_par (struct fb_info *info)
1770 struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
1771 struct fb_var_screeninfo *mode = &info->var;
1772 struct radeon_regs newmode;
1773 int hTotal, vTotal, hSyncStart, hSyncEnd,
1774 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1775 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1776 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1777 u32 dotClock = 1000000000 / mode->pixclock,
1778 sync, h_sync_pol, v_sync_pol;
1779 int freq = dotClock / 10; /* x 100 */
1780 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
1781 int useable_precision, roff, ron;
1782 int min_bits, format = 0;
1783 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1784 int primary_mon = PRIMARY_MONITOR(rinfo);
1785 int depth = var_to_depth(mode);
1786 int accel = (mode->accel_flags & FB_ACCELF_TEXT) != 0;
1788 rinfo->xres = mode->xres;
1789 rinfo->yres = mode->yres;
1790 rinfo->xres_virtual = mode->xres_virtual;
1791 rinfo->yres_virtual = mode->yres_virtual;
1792 rinfo->pixclock = mode->pixclock;
1794 hSyncStart = mode->xres + mode->right_margin;
1795 hSyncEnd = hSyncStart + mode->hsync_len;
1796 hTotal = hSyncEnd + mode->left_margin;
1798 vSyncStart = mode->yres + mode->lower_margin;
1799 vSyncEnd = vSyncStart + mode->vsync_len;
1800 vTotal = vSyncEnd + mode->upper_margin;
1802 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1803 if (rinfo->panel_xres < mode->xres)
1804 rinfo->xres = mode->xres = rinfo->panel_xres;
1805 if (rinfo->panel_yres < mode->yres)
1806 rinfo->yres = mode->yres = rinfo->panel_yres;
1808 hTotal = mode->xres + rinfo->hblank;
1809 hSyncStart = mode->xres + rinfo->hOver_plus;
1810 hSyncEnd = hSyncStart + rinfo->hSync_width;
1812 vTotal = mode->yres + rinfo->vblank;
1813 vSyncStart = mode->yres + rinfo->vOver_plus;
1814 vSyncEnd = vSyncStart + rinfo->vSync_width;
1818 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1819 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1821 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1822 hSyncStart, hSyncEnd, hTotal);
1823 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1824 vSyncStart, vSyncEnd, vTotal);
1826 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1827 vsync_wid = vSyncEnd - vSyncStart;
1830 else if (hsync_wid > 0x3f) /* max */
1835 else if (vsync_wid > 0x1f) /* max */
1838 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1839 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1841 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1843 format = radeon_get_dstbpp(depth);
1844 bytpp = mode->bits_per_pixel >> 3;
1846 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1847 hsync_fudge = hsync_fudge_fp[format-1];
1849 hsync_fudge = hsync_adj_tab[format-1];
1851 hsync_start = hSyncStart - 8 + hsync_fudge;
1853 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1856 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1857 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1859 newmode.crtc_ext_cntl |= CRTC_CRT_ON;
1861 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1864 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1868 newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1871 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1872 (((mode->xres / 8) - 1) << 16));
1874 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1875 (hsync_wid << 16) | (h_sync_pol << 23));
1877 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1878 ((mode->yres - 1) << 16);
1880 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1881 (vsync_wid << 16) | (v_sync_pol << 23));
1884 /* We first calculate the engine pitch */
1885 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1888 /* Then, re-multiply it to get the CRTC pitch */
1889 newmode.crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1891 newmode.crtc_pitch = (mode->xres_virtual >> 3);
1892 newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
1894 #if defined(__BIG_ENDIAN)
1896 * It looks like recent chips have a problem with SURFACE_CNTL,
1897 * setting SURF_TRANSLATION_DIS completely disables the
1898 * swapper as well, so we leave it unset now.
1900 newmode.surface_cntl = 0;
1902 /* Setup swapping on both apertures, though we currently
1903 * only use aperture 0, enabling swapper on aperture 1
1906 switch (mode->bits_per_pixel) {
1908 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
1909 newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
1913 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
1914 newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
1919 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1922 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1923 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
1924 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1925 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
1927 newmode.xres = mode->xres;
1928 newmode.yres = mode->yres;
1930 rinfo->bpp = mode->bits_per_pixel;
1931 rinfo->depth = depth;
1933 if (freq > rinfo->pll.ppll_max)
1934 freq = rinfo->pll.ppll_max;
1935 if (freq*12 < rinfo->pll.ppll_min)
1936 freq = rinfo->pll.ppll_min / 12;
1955 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1956 rinfo->pll_output_freq = post_div->divider * freq;
1957 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
1958 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
1962 rinfo->post_div = post_div->divider;
1963 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
1964 rinfo->pll.ref_clk);
1965 newmode.ppll_ref_div = rinfo->pll.ref_div;
1966 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
1968 newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1970 #ifdef CONFIG_PPC_OF
1971 /* Gross hack for iBook with M7 until I find out a proper fix */
1972 if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
1973 newmode.ppll_div_3 = 0x000600ad;
1974 #endif /* CONFIG_PPC_OF */
1976 RTRACE("post div = 0x%x\n", rinfo->post_div);
1977 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
1978 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
1981 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
1982 rinfo->pll.ref_div * rinfo->post_div);
1983 xclk_freq = rinfo->pll.xclk;
1985 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
1987 min_bits = min_bits_req(xclk_per_trans);
1988 useable_precision = min_bits + 1;
1990 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
1991 vclk_freq * mode->bits_per_pixel);
1993 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
1994 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
1995 xclk_per_trans) << (11 - useable_precision);
1996 roff = xclk_per_trans_precise * (32 - 4);
1998 RTRACE("ron = %d, roff = %d\n", ron, roff);
1999 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
2001 if ((ron + rinfo->ram.rloop) >= roff) {
2002 printk("radeonfb: error ron out of range\n");
2006 newmode.dda_config = (xclk_per_trans_precise |
2007 (useable_precision << 16) |
2008 (rinfo->ram.rloop << 20));
2009 newmode.dda_on_off = (ron << 16) | roff;
2011 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2012 unsigned int hRatio, vRatio;
2014 /* We force the pixel clock to be always enabled. Allowing it
2015 * to be power managed during blanking would save power, but has
2016 * nasty interactions with the 2D engine & sleep code that haven't
2017 * been solved yet. --BenH
2019 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2021 if (mode->xres > rinfo->panel_xres)
2022 mode->xres = rinfo->panel_xres;
2023 if (mode->yres > rinfo->panel_yres)
2024 mode->yres = rinfo->panel_yres;
2026 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2027 << HORZ_PANEL_SHIFT);
2028 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2029 << VERT_PANEL_SHIFT);
2031 if (mode->xres != rinfo->panel_xres) {
2032 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2034 newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2035 (newmode.fp_horz_stretch &
2036 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2037 HORZ_AUTO_RATIO_INC)));
2038 newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2039 HORZ_STRETCH_ENABLE);
2041 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2043 if (mode->yres != rinfo->panel_yres) {
2044 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2046 newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2047 (newmode.fp_vert_stretch &
2048 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2049 newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2050 VERT_STRETCH_ENABLE);
2052 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2054 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2056 FP_RMX_HVSYNC_CONTROL_EN |
2061 FP_CRTC_USE_SHADOW_VEND |
2064 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2065 FP_CRTC_DONT_SHADOW_HEND);
2067 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2068 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2069 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2070 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2072 if (primary_mon == MT_LCD) {
2073 newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2074 newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2077 newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2078 newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2079 TMDS_ICHCSEL | TMDS_PLL_EN) &
2081 newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2084 newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
2085 (((mode->xres / 8) - 1) << 16));
2086 newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
2087 ((mode->yres - 1) << 16);
2088 newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
2089 (hsync_wid << 16) | (h_sync_pol << 23));
2090 newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
2091 (vsync_wid << 16) | (v_sync_pol << 23));
2095 if (!rinfo->asleep) {
2096 radeon_write_mode (rinfo, &newmode);
2097 /* (re)initialize the engine */
2099 radeon_engine_init (rinfo);
2104 info->fix.line_length = rinfo->pitch*64;
2106 info->fix.line_length = mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8);
2107 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
2109 #ifdef CONFIG_BOOTX_TEXT
2110 /* Update debug text engine */
2111 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2112 rinfo->depth, info->fix.line_length);
2119 static void radeon_write_mode (struct radeonfb_info *rinfo,
2120 struct radeon_regs *mode)
2123 int primary_mon = PRIMARY_MONITOR(rinfo);
2125 radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
2128 if (rinfo->arch == RADEON_M6) {
2130 OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
2133 OUTREG(common_regs[i].reg, common_regs[i].val);
2136 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2137 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2138 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2139 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2140 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2141 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2142 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2143 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2144 OUTREG(CRTC_OFFSET, 0);
2145 OUTREG(CRTC_OFFSET_CNTL, 0);
2146 OUTREG(CRTC_PITCH, mode->crtc_pitch);
2148 #if defined(__BIG_ENDIAN)
2149 OUTREG(SURFACE_CNTL, mode->surface_cntl);
2152 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2153 PPLL_DIV_SEL_MASK) {
2154 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2157 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2159 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2160 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2161 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2164 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2165 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2166 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2169 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2170 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2171 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2174 OUTPLL(HTOTAL_CNTL, 0);
2176 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2178 // OUTREG(DDA_CONFIG, mode->dda_config);
2179 // OUTREG(DDA_ON_OFF, mode->dda_on_off);
2181 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2182 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2183 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2184 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2185 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2186 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2187 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2188 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2189 OUTREG(TMDS_CRC, mode->tmds_crc);
2190 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2192 if (primary_mon == MT_LCD) {
2193 unsigned int tmp = INREG(LVDS_GEN_CNTL);
2195 mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2196 mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2198 if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2199 (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2200 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2202 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2204 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2206 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2209 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2215 radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
2217 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2222 static struct fb_ops radeonfb_ops = {
2223 .owner = THIS_MODULE,
2224 .fb_check_var = radeonfb_check_var,
2225 .fb_set_par = radeonfb_set_par,
2226 .fb_setcolreg = radeonfb_setcolreg,
2227 .fb_pan_display = radeonfb_pan_display,
2228 .fb_blank = radeonfb_blank,
2229 .fb_ioctl = radeonfb_ioctl,
2231 .fb_fillrect = radeonfb_fillrect,
2232 .fb_copyarea = radeonfb_copyarea,
2233 .fb_imageblit = radeonfb_imageblit,
2234 .fb_rasterimg = radeonfb_rasterimg,
2236 .fb_fillrect = cfb_fillrect,
2237 .fb_copyarea = cfb_copyarea,
2238 .fb_imageblit = cfb_imageblit,
2240 .fb_cursor = soft_cursor,
2244 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
2246 struct fb_info *info;
2248 info = &rinfo->info;
2252 info->pseudo_palette = rinfo->pseudo_palette;
2253 info->flags = FBINFO_FLAG_DEFAULT;
2254 info->fbops = &radeonfb_ops;
2255 info->display_fg = NULL;
2256 info->screen_base = (char *)rinfo->fb_base;
2258 /* Fill fix common fields */
2259 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2260 info->fix.smem_start = rinfo->fb_base_phys;
2261 info->fix.smem_len = rinfo->video_ram;
2262 info->fix.type = FB_TYPE_PACKED_PIXELS;
2263 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2264 info->fix.xpanstep = 8;
2265 info->fix.ypanstep = 1;
2266 info->fix.ywrapstep = 0;
2267 info->fix.type_aux = 0;
2268 info->fix.mmio_start = rinfo->mmio_base_phys;
2269 info->fix.mmio_len = RADEON_REGSIZE;
2271 info->fix.accel = FB_ACCEL_NONE;
2273 info->fix.accel = FB_ACCEL_ATI_RADEON;
2275 if (radeon_init_disp (rinfo) < 0)
2282 #ifdef CONFIG_PMAC_BACKLIGHT
2284 /* TODO: Dbl check these tables, we don't go up to full ON backlight
2285 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
2286 * having some more official numbers from ATI
2288 static int backlight_conv_m6[] = {
2289 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2290 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2292 static int backlight_conv_m7[] = {
2293 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
2294 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
2297 #define BACKLIGHT_LVDS_OFF
2298 #undef BACKLIGHT_DAC_OFF
2300 /* We turn off the LCD completely instead of just dimming the backlight.
2301 * This provides some greater power saving and the display is useless
2302 * without backlight anyway.
2305 static int radeon_set_backlight_enable(int on, int level, void *data)
2307 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2308 unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2311 /* Pardon me for that hack... maybe some day we can figure
2312 * out in what direction backlight should work on a given
2315 if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
2316 && !machine_is_compatible("PowerBook4,3"))
2317 conv_table = backlight_conv_m7;
2319 conv_table = backlight_conv_m6;
2321 lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2322 if (on && (level > BACKLIGHT_OFF)) {
2323 lvds_gen_cntl |= LVDS_DIGON;
2324 if (!(lvds_gen_cntl & LVDS_ON)) {
2325 lvds_gen_cntl &= ~LVDS_BLON;
2326 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2327 (void)INREG(LVDS_GEN_CNTL);
2329 lvds_gen_cntl |= LVDS_BLON;
2330 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2332 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2333 lvds_gen_cntl |= (conv_table[level] <<
2334 LVDS_BL_MOD_LEVEL_SHIFT);
2335 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2336 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2338 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2339 lvds_gen_cntl |= (conv_table[0] <<
2340 LVDS_BL_MOD_LEVEL_SHIFT);
2341 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2342 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2344 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2347 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2348 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2349 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2354 static int radeon_set_backlight_level(int level, void *data)
2356 return radeon_set_backlight_enable(1, level, data);
2358 #endif /* CONFIG_PMAC_BACKLIGHT */
2361 #ifdef CONFIG_PMAC_PBOOK
2366 * Radeon M6 Power Management code. This code currently only supports
2367 * the mobile chips, it's based from some informations provided by ATI
2368 * along with hours of tracing of MacOS drivers
2371 static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
2373 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
2374 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
2375 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
2376 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
2377 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
2378 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
2379 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
2380 rinfo->save_regs[7] = INPLL(MCLK_MISC);
2381 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
2383 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
2384 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
2385 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
2386 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
2387 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
2388 rinfo->save_regs[14] = INREG(BUS_CNTL1);
2389 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
2390 rinfo->save_regs[16] = INREG(AGP_CNTL);
2391 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2392 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2393 rinfo->save_regs[19] = INREG(GPIOPAD_A);
2394 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
2395 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
2396 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
2397 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
2398 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
2399 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
2400 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
2401 rinfo->save_regs[27] = INREG(GPIO_MONID);
2402 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
2404 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
2405 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
2406 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
2407 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
2408 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
2411 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
2413 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
2415 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2416 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2417 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
2418 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
2419 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2420 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
2421 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
2422 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
2424 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2425 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
2426 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
2427 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
2428 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
2429 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2430 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
2431 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2432 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
2433 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
2435 // wait VBL before that one ?
2436 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
2438 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2439 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2440 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2441 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
2442 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
2443 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
2444 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
2445 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
2446 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
2447 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
2450 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
2452 OUTREG(GPIOPAD_MASK, 0x0001ffff);
2453 OUTREG(GPIOPAD_EN, 0x00000400);
2454 OUTREG(GPIOPAD_A, 0x00000000);
2455 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
2456 OUTREG(ZV_LCDPAD_EN, 0x00000000);
2457 OUTREG(ZV_LCDPAD_A, 0x00000000);
2458 OUTREG(GPIO_VGA_DDC, 0x00030000);
2459 OUTREG(GPIO_DVI_DDC, 0x00000000);
2460 OUTREG(GPIO_MONID, 0x00030000);
2461 OUTREG(GPIO_CRT2_DDC, 0x00000000);
2464 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
2469 // OUTPLL(P2PLL_REF_DIV, 0x0c);
2471 // .../... figure out what macos does here
2474 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
2478 reg = INREG(BUS_CNTL1);
2479 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
2480 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
2481 OUTREG(BUS_CNTL1, reg);
2483 reg = INPLL(PLL_PWRMGT_CNTL);
2484 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
2485 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
2486 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2487 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
2488 OUTPLL(PLL_PWRMGT_CNTL, reg);
2490 // reg = INPLL(TV_PLL_CNTL1);
2491 // reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
2492 // OUTPLL(TV_PLL_CNTL1, reg);
2494 reg = INREG(TV_DAC_CNTL);
2495 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
2496 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
2497 TV_DAC_CNTL_BDACPD |
2498 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
2499 OUTREG(TV_DAC_CNTL, reg);
2501 reg = INREG(TMDS_TRANSMITTER_CNTL);
2502 reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
2503 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
2505 // lvds_pll_cntl = regr32(g, LVDS_PLL_CNTL);
2506 // lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
2507 // lvds_pll_cntl |= LVDS_PLL_CNTL__LVDS_PLL_RESET;
2508 // regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
2510 reg = INREG(DAC_CNTL);
2512 OUTREG(DAC_CNTL, reg);
2514 reg = INREG(DAC_CNTL2);
2515 reg &= ~DAC2_CMP_EN;
2516 OUTREG(DAC_CNTL2, reg);
2518 reg = INREG(TV_DAC_CNTL);
2519 reg &= ~TV_DAC_CNTL_DETECT;
2520 OUTREG(TV_DAC_CNTL, reg);
2523 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
2525 /* This code is disabled. It does what is in the pm_init
2526 * function of the MacOS driver code ATI sent me. However,
2527 * it doesn't fix my sleep problem, and is causing other issues
2528 * on wakeup (bascially the machine dying when switching consoles
2529 * I haven't had time to investigate this yet
2536 // set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
2537 // TCLK and TEST_MODE to 0
2538 temp = INPLL(CLK_PWRMGT_CNTL);
2539 OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
2541 // Turn on Power Management
2542 temp = INPLL(CLK_PWRMGT_CNTL);
2543 OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
2545 // Turn off display clock if using mobile chips
2546 temp = INPLL(CLK_PWRMGT_CNTL);
2547 OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
2549 // Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
2550 temp = INPLL(VCLK_ECP_CNTL);
2551 OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
2553 // Force ECP_FORCE_ON to 1
2554 temp = INPLL(VCLK_ECP_CNTL);
2555 OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
2557 // Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
2558 temp = INPLL(PIXCLKS_CNTL);
2559 OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
2561 // Forcing SCLK_CNTL to ON
2562 OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
2564 // Set PM control over XTALIN pad
2565 temp = INPLL(CLK_PIN_CNTL);
2566 OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
2568 // Force MCLK and YCLK and MC as dynamic
2569 temp = INPLL(MCLK_CNTL);
2570 OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
2573 temp = INPLL(PLL_PWRMGT_CNTL);
2574 OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
2576 // set MOBILE_SU to 1 if M6 or DDR64 is detected
2577 temp = INPLL(PLL_PWRMGT_CNTL);
2578 OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
2580 // select PM access mode (PM_MODE_SEL) (use ACPI mode)
2581 // temp = INPLL(PLL_PWRMGT_CNTL);
2582 // OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
2583 temp = INPLL(PLL_PWRMGT_CNTL);
2584 OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
2586 // set DISP_MISC_CNTL register
2587 disp_misc_cntl = INREG(DISP_MISC_CNTL);
2588 disp_misc_cntl &= ~( DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
2589 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
2590 DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
2591 DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
2592 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
2593 DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
2594 DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
2595 DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
2596 DISP_MISC_CNTL_SOFT_RESET_LVDS |
2597 DISP_MISC_CNTL_SOFT_RESET_TMDS |
2598 DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
2599 DISP_MISC_CNTL_SOFT_RESET_TV);
2600 OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
2602 // set DISP_PWR_MAN register
2603 disp_pwr_man = INREG(DISP_PWR_MAN);
2604 // clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
2605 disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
2606 DISP_PWR_MAN_TV_ENABLE_RST |
2607 // DISP_PWR_MAN_AUTO_PWRUP_EN |
2608 DISP_PWR_MAN_DISP_D3_GRPH_RST |
2609 DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
2610 DISP_PWR_MAN_DISP_D3_OV0_RST |
2611 DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
2612 DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
2613 DISP_PWR_MAN_DISP_D1D2_OV0_RST);
2614 disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
2615 DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
2616 DISP_PWR_MAN_DISP_D3_RST |
2617 DISP_PWR_MAN_DISP_D3_REG_RST);
2618 OUTREG(DISP_PWR_MAN, disp_pwr_man);
2620 // clau - 10.24.2000
2621 // - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
2622 // - add in setting for AGP_CNTL b7:0 = 0x20
2623 // - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
2625 // the following settings (two lines) are applied at a later part of this function, only on mobile platform
2626 // requres -mobile flag
2627 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
2628 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | 0x80000000);
2629 OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
2630 OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
2632 // yulee - 12.12.2000
2634 // EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
2635 // ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
2636 // only on mobile platform
2637 OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
2639 // yulee -12.12.2000
2640 // AGPCLK_VALID@BUS_CNTL1 = 1
2641 // MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
2642 // CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
2643 // CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
2644 // only on mobile platform
2645 OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
2646 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
2647 OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
2653 OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2654 OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2655 (void)INREG(CRTC2_GEN_CNTL);
2659 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2666 /* Set the chip into appropriate suspend mode (we use D2,
2667 * D3 would require a compete re-initialization of the chip,
2668 * including PCI config registers, clocks, AGP conf, ...)
2671 /* According to ATI, we should program V2CLK here, I have
2672 * to verify what's up exactly
2674 /* Save some registers */
2675 radeon_pm_save_regs(rinfo);
2677 /* Check that on M7 too, might work might not. M7 may also
2678 * need explicit enabling of PM
2680 if (rinfo->arch == RADEON_M6) {
2682 radeon_pm_program_v2clk(rinfo);
2684 /* Disable IO PADs */
2685 radeon_pm_disable_iopad(rinfo);
2687 /* Set low current */
2688 radeon_pm_low_current(rinfo);
2690 /* Prepare chip for power management */
2691 radeon_pm_setup_for_suspend(rinfo);
2693 /* Reset the MDLL */
2694 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2695 (void)INPLL(MDLL_RDCKA);
2696 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2697 (void)INPLL(MDLL_RDCKA);
2700 /* Switch PCI power managment to D2. */
2702 pci_read_config_word(
2703 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2707 pci_write_config_word(
2708 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2709 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2713 /* Switch back PCI powermanagment to D0 */
2715 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2720 /* Do we need that on M7 ? */
2721 if (rinfo->arch == RADEON_M6) {
2722 /* Restore the MDLL */
2723 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2724 (void)INPLL(MDLL_CKO);
2727 /* Restore some registers */
2728 radeon_pm_restore_regs(rinfo);
2733 * Save the contents of the framebuffer when we go to sleep,
2734 * and restore it when we wake up again.
2737 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2739 struct radeonfb_info *rinfo;
2741 for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2742 struct fb_fix_screeninfo fix;
2744 struct display *disp;
2746 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2748 switch (rinfo->arch) {
2754 return PBOOK_SLEEP_REFUSE;
2757 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2758 nb = fb_display[fg_console].var.yres * fix.line_length;
2761 case PBOOK_SLEEP_NOW:
2762 acquire_console_sem();
2763 disp->dispsw = &fbcon_dummy;
2766 /* Make sure engine is reset */
2767 radeon_engine_reset();
2768 radeon_engine_idle();
2771 /* Blank display and LCD */
2772 radeonfb_blank(VESA_POWERDOWN+1,
2773 (struct fb_info *)rinfo);
2777 radeon_set_suspend(rinfo, 1);
2778 release_console_sem();
2782 acquire_console_sem();
2784 radeon_set_suspend(rinfo, 0);
2787 radeon_engine_init(rinfo);
2789 radeon_set_dispsw(rinfo, disp);
2790 radeon_load_video_mode(rinfo, &disp->var);
2791 do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
2792 (struct fb_info *)rinfo);
2794 radeonfb_blank(0, (struct fb_info *)rinfo);
2795 release_console_sem();
2796 printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
2801 return PBOOK_SLEEP_OK;
2804 #endif /* CONFIG_PMAC_PBOOK */
2806 static int radeonfb_pci_register (struct pci_dev *pdev,
2807 const struct pci_device_id *ent)
2809 struct radeonfb_info *rinfo;
2810 struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
2813 RTRACE("radeonfb_pci_register BEGIN\n");
2815 /* Enable device in PCI config */
2816 if (pci_enable_device(pdev) != 0) {
2817 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2821 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
2823 printk ("radeonfb: could not allocate memory\n");
2827 memset (rinfo, 0, sizeof (struct radeonfb_info));
2828 //info = &rinfo->info;
2830 strcpy(rinfo->name, rci->name);
2831 rinfo->arch = rci->arch;
2833 /* Set base addrs */
2834 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2835 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2837 /* request the mem regions */
2838 if (!request_mem_region (rinfo->fb_base_phys,
2839 pci_resource_len(pdev, 0), "radeonfb")) {
2840 printk ("radeonfb: cannot reserve FB region\n");
2845 if (!request_mem_region (rinfo->mmio_base_phys,
2846 pci_resource_len(pdev, 2), "radeonfb")) {
2847 printk ("radeonfb: cannot reserve MMIO region\n");
2848 release_mem_region (rinfo->fb_base_phys,
2849 pci_resource_len(pdev, 0));
2854 /* map the regions */
2855 rinfo->mmio_base = (unsigned long) ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2856 if (!rinfo->mmio_base) {
2857 printk ("radeonfb: cannot map MMIO\n");
2858 release_mem_region (rinfo->mmio_base_phys,
2859 pci_resource_len(pdev, 2));
2860 release_mem_region (rinfo->fb_base_phys,
2861 pci_resource_len(pdev, 0));
2866 rinfo->chipset = pdev->device;
2868 switch (rinfo->arch) {
2870 rinfo->hasCRTC2 = 0;
2873 /* all the rest have it */
2874 rinfo->hasCRTC2 = 1;
2878 if (rinfo->arch == RADEON_M7) {
2880 * Noticed some errors in accel with M7, will have to work these out...
2886 printk("radeonfb: mirroring display to CRT\n");
2888 /* framebuffer size */
2889 tmp = INREG(CONFIG_MEMSIZE);
2891 /* mem size is bits [28:0], mask off the rest */
2892 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2895 tmp = INREG(MEM_SDRAM_MODE_REG);
2896 switch ((MEM_CFG_TYPE & tmp) >> 30) {
2898 /* SDR SGRAM (2:1) */
2899 strcpy(rinfo->ram_type, "SDR SGRAM");
2902 rinfo->ram.trcd = 1;
2906 rinfo->ram.loop_latency = 16;
2907 rinfo->ram.rloop = 16;
2912 strcpy(rinfo->ram_type, "DDR SGRAM");
2915 rinfo->ram.trcd = 3;
2919 rinfo->ram.tr2w = 1;
2920 rinfo->ram.loop_latency = 16;
2921 rinfo->ram.rloop = 16;
2925 /* 64-bit SDR SGRAM */
2926 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2929 rinfo->ram.trcd = 3;
2933 rinfo->ram.tr2w = 1;
2934 rinfo->ram.loop_latency = 17;
2935 rinfo->ram.rloop = 17;
2940 rinfo->bios_seg = radeon_find_rom(rinfo);
2941 radeon_get_pllinfo(rinfo, rinfo->bios_seg);
2944 * Hack to get around some busted production M6's
2947 if (rinfo->video_ram == 0) {
2948 switch (pdev->device) {
2949 case PCI_DEVICE_ID_ATI_RADEON_LY:
2950 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2951 rinfo->video_ram = 8192 * 1024;
2959 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2961 #if !defined(__powerpc__)
2962 radeon_get_moninfo(rinfo);
2964 switch (pdev->device) {
2965 case PCI_DEVICE_ID_ATI_RADEON_LW:
2966 case PCI_DEVICE_ID_ATI_RADEON_LX:
2967 case PCI_DEVICE_ID_ATI_RADEON_LY:
2968 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2969 rinfo->dviDisp_type = MT_LCD;
2972 radeon_get_moninfo(rinfo);
2977 radeon_get_EDID(rinfo);
2979 if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
2980 (rinfo->crtDisp_type == MT_DFP)) {
2981 if (!radeon_get_dfpinfo(rinfo)) {
2982 iounmap ((void*)rinfo->mmio_base);
2983 release_mem_region (rinfo->mmio_base_phys,
2984 pci_resource_len(pdev, 2));
2985 release_mem_region (rinfo->fb_base_phys,
2986 pci_resource_len(pdev, 0));
2992 rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys, rinfo->video_ram);
2993 if (!rinfo->fb_base) {
2994 printk ("radeonfb: cannot map FB\n");
2995 iounmap ((void*)rinfo->mmio_base);
2996 release_mem_region (rinfo->mmio_base_phys,
2997 pci_resource_len(pdev, 2));
2998 release_mem_region (rinfo->fb_base_phys,
2999 pci_resource_len(pdev, 0));
3004 /* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
3005 * driver setup here.
3007 * On PPC, OF based cards setup the internal memory
3008 * mapping in strange ways. We change it so that the
3009 * framebuffer is mapped at 0 and given half of the card's
3010 * address space (2Gb). AGP is mapped high (0xe0000000) and
3011 * can use up to 512Mb. Once DRI is fully implemented, we
3012 * will have to setup the PCI remapper to remap the agp_special_page
3013 * memory page somewhere between those regions so that the card
3014 * use a normal PCI bus master cycle to access the ring read ptr.
3017 #ifdef CONFIG_ALL_PPC
3018 if (rinfo->hasCRTC2)
3019 OUTREG(CRTC2_GEN_CNTL,
3020 (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
3021 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
3022 OUTREG(MC_FB_LOCATION, 0x7fff0000);
3023 OUTREG(MC_AGP_LOCATION, 0xffffe000);
3024 OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
3025 if (rinfo->hasCRTC2)
3026 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
3027 OUTREG(SRC_OFFSET, 0x00000000);
3028 OUTREG(DST_OFFSET, 0x00000000);
3030 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
3031 #endif /* CONFIG_ALL_PPC */
3033 /* save current mode regs before we switch into the new one
3034 * so we can restore this upon __exit
3036 radeon_save_state (rinfo, &rinfo->init_state);
3038 /* set all the vital stuff */
3039 radeon_set_fbinfo (rinfo);
3041 pci_set_drvdata(pdev, rinfo);
3042 rinfo->next = board_list;
3045 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
3046 printk ("radeonfb: could not register framebuffer\n");
3047 iounmap ((void*)rinfo->fb_base);
3048 iounmap ((void*)rinfo->mmio_base);
3049 release_mem_region (rinfo->mmio_base_phys,
3050 pci_resource_len(pdev, 2));
3051 release_mem_region (rinfo->fb_base_phys,
3052 pci_resource_len(pdev, 0));
3058 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
3060 MTRR_TYPE_WRCOMB, 1);
3063 #ifdef CONFIG_PMAC_BACKLIGHT
3064 if (rinfo->dviDisp_type == MT_LCD)
3065 register_backlight_controller(&radeon_backlight_controller,
3069 #ifdef CONFIG_PMAC_PBOOK
3070 if (rinfo->dviDisp_type == MT_LCD) {
3071 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
3072 pmu_register_sleep_notifier(&radeon_sleep_notifier);
3076 printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
3077 (rinfo->video_ram/(1024*1024)));
3079 if (rinfo->hasCRTC2) {
3080 printk("radeonfb: DVI port %s monitor connected\n",
3081 GET_MON_NAME(rinfo->dviDisp_type));
3082 printk("radeonfb: CRT port %s monitor connected\n",
3083 GET_MON_NAME(rinfo->crtDisp_type));
3085 printk("radeonfb: CRT port %s monitor connected\n",
3086 GET_MON_NAME(rinfo->crtDisp_type));
3089 RTRACE("radeonfb_pci_register END\n");
3096 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
3098 struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
3103 /* restore original state
3105 * Doesn't quite work yet, possibly because of the PPC hacking
3106 * I do on startup, disable for now. --BenH
3108 radeon_write_mode (rinfo, &rinfo->init_state);
3111 if (rinfo->mtrr_hdl >= 0)
3112 mtrr_del(rinfo->mtrr_hdl, 0, 0);
3115 unregister_framebuffer ((struct fb_info *) rinfo);
3117 iounmap ((void*)rinfo->mmio_base);
3118 iounmap ((void*)rinfo->fb_base);
3120 release_mem_region (rinfo->mmio_base_phys,
3121 pci_resource_len(pdev, 2));
3122 release_mem_region (rinfo->fb_base_phys,
3123 pci_resource_len(pdev, 0));
3129 static struct pci_driver radeonfb_driver = {
3131 .id_table = radeonfb_pci_table,
3132 .probe = radeonfb_pci_register,
3133 .remove = __devexit_p(radeonfb_pci_unregister),
3137 int __init radeonfb_old_init (void)
3139 return pci_module_init (&radeonfb_driver);
3143 void __exit radeonfb_old_exit (void)
3145 pci_unregister_driver (&radeonfb_driver);
3149 int __init radeonfb_old_setup (char *options)
3153 if (!options || !*options)
3156 while ((this_opt = strsep (&options, ",")) != NULL) {
3159 if (!strncmp(this_opt, "noaccel", 7)) {
3161 } else if (!strncmp(this_opt, "mirror", 6)) {
3163 } else if (!strncmp(this_opt, "dfp", 3)) {
3165 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
3166 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
3167 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3170 mode_option = this_opt;
3177 module_init(radeonfb_old_init);
3178 module_exit(radeonfb_old_exit);
3182 MODULE_AUTHOR("Ani Joshi");
3183 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
3184 MODULE_LICENSE("GPL");