2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/config.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
38 #include <linux/tty.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
49 #include <asm/pci-bridge.h>
51 #ifdef CONFIG_PMAC_BACKLIGHT
52 #include <asm/backlight.h>
58 #ifndef CONFIG_PCI /* sanity check */
59 #error This driver requires PCI support.
62 /* version number of this driver */
63 #define RIVAFB_VERSION "0.9.5b"
65 /* ------------------------------------------------------------------------- *
67 * various helpful macros and constants
69 * ------------------------------------------------------------------------- */
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define NVTRACE printk
73 #define NVTRACE if(0) printk
76 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
79 #ifdef CONFIG_FB_RIVA_DEBUG
80 #define assert(expr) \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
90 #define PFX "rivafb: "
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
97 /* HW cursor parameters */
100 /* ------------------------------------------------------------------------- *
104 * ------------------------------------------------------------------------- */
106 static int rivafb_blank(int blank, struct fb_info *info);
108 /* ------------------------------------------------------------------------- *
110 * card identification
112 * ------------------------------------------------------------------------- */
114 static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { 0, } /* terminate list */
197 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
199 /* ------------------------------------------------------------------------- *
203 * ------------------------------------------------------------------------- */
205 /* command line data, set in rivafb_setup() */
206 static int flatpanel __initdata = -1; /* Autodetect later */
207 static int forceCRTC __initdata = -1;
209 static int nomtrr __initdata = 0;
212 static char *mode_option __initdata = NULL;
213 static int strictmode = 0;
215 static struct fb_fix_screeninfo __initdata rivafb_fix = {
216 .type = FB_TYPE_PACKED_PIXELS,
221 static struct fb_var_screeninfo __initdata rivafb_default_var = {
231 .activate = FB_ACTIVATE_NOW,
234 .accel_flags = FB_ACCELF_TEXT,
242 .vmode = FB_VMODE_NONINTERLACED
246 static const struct riva_regs reg_template = {
247 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
248 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
249 0x41, 0x01, 0x0F, 0x00, 0x00},
250 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
251 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
252 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
253 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
254 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
255 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
256 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
262 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
269 #ifdef CONFIG_PMAC_BACKLIGHT
271 static int riva_backlight_levels[] = {
290 static int riva_set_backlight_enable(int on, int level, void *data);
291 static int riva_set_backlight_level(int level, void *data);
292 static struct backlight_controller riva_backlight_controller = {
293 riva_set_backlight_enable,
294 riva_set_backlight_level
296 #endif /* CONFIG_PMAC_BACKLIGHT */
298 /* ------------------------------------------------------------------------- *
302 * ------------------------------------------------------------------------- */
304 static inline void CRTCout(struct riva_par *par, unsigned char index,
307 VGA_WR08(par->riva.PCIO, 0x3d4, index);
308 VGA_WR08(par->riva.PCIO, 0x3d5, val);
311 static inline unsigned char CRTCin(struct riva_par *par,
314 VGA_WR08(par->riva.PCIO, 0x3d4, index);
315 return (VGA_RD08(par->riva.PCIO, 0x3d5));
318 static inline void GRAout(struct riva_par *par, unsigned char index,
321 VGA_WR08(par->riva.PVIO, 0x3ce, index);
322 VGA_WR08(par->riva.PVIO, 0x3cf, val);
325 static inline unsigned char GRAin(struct riva_par *par,
328 VGA_WR08(par->riva.PVIO, 0x3ce, index);
329 return (VGA_RD08(par->riva.PVIO, 0x3cf));
332 static inline void SEQout(struct riva_par *par, unsigned char index,
335 VGA_WR08(par->riva.PVIO, 0x3c4, index);
336 VGA_WR08(par->riva.PVIO, 0x3c5, val);
339 static inline unsigned char SEQin(struct riva_par *par,
342 VGA_WR08(par->riva.PVIO, 0x3c4, index);
343 return (VGA_RD08(par->riva.PVIO, 0x3c5));
346 static inline void ATTRout(struct riva_par *par, unsigned char index,
349 VGA_WR08(par->riva.PCIO, 0x3c0, index);
350 VGA_WR08(par->riva.PCIO, 0x3c0, val);
353 static inline unsigned char ATTRin(struct riva_par *par,
356 VGA_WR08(par->riva.PCIO, 0x3c0, index);
357 return (VGA_RD08(par->riva.PCIO, 0x3c1));
360 static inline void MISCout(struct riva_par *par, unsigned char val)
362 VGA_WR08(par->riva.PVIO, 0x3c2, val);
365 static inline unsigned char MISCin(struct riva_par *par)
367 return (VGA_RD08(par->riva.PVIO, 0x3cc));
370 static u8 byte_rev[256] = {
371 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
372 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
373 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
374 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
375 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
376 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
377 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
378 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
379 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
380 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
381 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
382 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
383 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
384 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
385 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
386 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
387 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
388 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
389 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
390 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
391 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
392 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
393 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
394 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
395 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
396 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
397 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
398 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
399 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
400 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
401 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
402 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
405 static inline void reverse_order(u32 *l)
408 *a = byte_rev[*a], a++;
409 *a = byte_rev[*a], a++;
410 *a = byte_rev[*a], a++;
414 /* ------------------------------------------------------------------------- *
418 * ------------------------------------------------------------------------- */
421 * rivafb_load_cursor_image - load cursor image to hardware
422 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
423 * @par: pointer to private data
424 * @w: width of cursor image in pixels
425 * @h: height of cursor image in scanlines
426 * @bg: background color (ARGB1555) - alpha bit determines opacity
427 * @fg: foreground color (ARGB1555)
430 * Loads cursor image based on a monochrome source and mask bitmap. The
431 * image bits determines the color of the pixel, 0 for background, 1 for
432 * foreground. Only the affected region (as determined by @w and @h
433 * parameters) will be updated.
438 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
439 u16 bg, u16 fg, u32 w, u32 h)
443 u32 *data = (u32 *)data8;
444 bg = le16_to_cpu(bg);
445 fg = le16_to_cpu(fg);
447 for (i = 0; i < h; i++) {
451 for (j = 0; j < w/2; j++) {
453 #if defined (__BIG_ENDIAN)
454 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
456 tmp |= (b & (1 << 31)) ? fg : bg;
459 tmp = (b & 1) ? fg : bg;
461 tmp |= (b & 1) ? fg << 16 : bg << 16;
464 writel(tmp, &par->riva.CURSOR[k++]);
466 k += (MAX_CURS - w)/2;
470 /* ------------------------------------------------------------------------- *
472 * general utility functions
474 * ------------------------------------------------------------------------- */
477 * riva_wclut - set CLUT entry
478 * @chip: pointer to RIVA_HW_INST object
479 * @regnum: register number
480 * @red: red component
481 * @green: green component
482 * @blue: blue component
485 * Sets color register @regnum.
490 static void riva_wclut(RIVA_HW_INST *chip,
491 unsigned char regnum, unsigned char red,
492 unsigned char green, unsigned char blue)
494 VGA_WR08(chip->PDIO, 0x3c8, regnum);
495 VGA_WR08(chip->PDIO, 0x3c9, red);
496 VGA_WR08(chip->PDIO, 0x3c9, green);
497 VGA_WR08(chip->PDIO, 0x3c9, blue);
501 * riva_rclut - read fromCLUT register
502 * @chip: pointer to RIVA_HW_INST object
503 * @regnum: register number
504 * @red: red component
505 * @green: green component
506 * @blue: blue component
509 * Reads red, green, and blue from color register @regnum.
514 static void riva_rclut(RIVA_HW_INST *chip,
515 unsigned char regnum, unsigned char *red,
516 unsigned char *green, unsigned char *blue)
519 VGA_WR08(chip->PDIO, 0x3c7, regnum);
520 *red = VGA_RD08(chip->PDIO, 0x3c9);
521 *green = VGA_RD08(chip->PDIO, 0x3c9);
522 *blue = VGA_RD08(chip->PDIO, 0x3c9);
526 * riva_save_state - saves current chip state
527 * @par: pointer to riva_par object containing info for current riva board
528 * @regs: pointer to riva_regs object
531 * Saves current chip state to @regs.
537 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
542 par->riva.LockUnlock(&par->riva, 0);
544 par->riva.UnloadStateExt(&par->riva, ®s->ext);
546 regs->misc_output = MISCin(par);
548 for (i = 0; i < NUM_CRT_REGS; i++)
549 regs->crtc[i] = CRTCin(par, i);
551 for (i = 0; i < NUM_ATC_REGS; i++)
552 regs->attr[i] = ATTRin(par, i);
554 for (i = 0; i < NUM_GRC_REGS; i++)
555 regs->gra[i] = GRAin(par, i);
557 for (i = 0; i < NUM_SEQ_REGS; i++)
558 regs->seq[i] = SEQin(par, i);
563 * riva_load_state - loads current chip state
564 * @par: pointer to riva_par object containing info for current riva board
565 * @regs: pointer to riva_regs object
568 * Loads chip state from @regs.
571 * riva_load_video_mode()
576 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
578 RIVA_HW_STATE *state = ®s->ext;
582 CRTCout(par, 0x11, 0x00);
584 par->riva.LockUnlock(&par->riva, 0);
586 par->riva.LoadStateExt(&par->riva, state);
588 MISCout(par, regs->misc_output);
590 for (i = 0; i < NUM_CRT_REGS; i++) {
596 CRTCout(par, i, regs->crtc[i]);
600 for (i = 0; i < NUM_ATC_REGS; i++)
601 ATTRout(par, i, regs->attr[i]);
603 for (i = 0; i < NUM_GRC_REGS; i++)
604 GRAout(par, i, regs->gra[i]);
606 for (i = 0; i < NUM_SEQ_REGS; i++)
607 SEQout(par, i, regs->seq[i]);
612 * riva_load_video_mode - calculate timings
613 * @info: pointer to fb_info object containing info for current riva board
616 * Calculate some timings and then send em off to riva_load_state().
621 static void riva_load_video_mode(struct fb_info *info)
623 int bpp, width, hDisplaySize, hDisplay, hStart,
624 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
625 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
626 struct riva_par *par = (struct riva_par *) info->par;
627 struct riva_regs newmode;
630 /* time to calculate */
631 rivafb_blank(1, info);
633 bpp = info->var.bits_per_pixel;
634 if (bpp == 16 && info->var.green.length == 5)
636 width = info->var.xres_virtual;
637 hDisplaySize = info->var.xres;
638 hDisplay = (hDisplaySize / 8) - 1;
639 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
640 hEnd = (hDisplaySize + info->var.right_margin +
641 info->var.hsync_len) / 8 - 1;
642 hTotal = (hDisplaySize + info->var.right_margin +
643 info->var.hsync_len + info->var.left_margin) / 8 - 5;
644 hBlankStart = hDisplay;
645 hBlankEnd = hTotal + 4;
647 height = info->var.yres_virtual;
648 vDisplay = info->var.yres - 1;
649 vStart = info->var.yres + info->var.lower_margin - 1;
650 vEnd = info->var.yres + info->var.lower_margin +
651 info->var.vsync_len - 1;
652 vTotal = info->var.yres + info->var.lower_margin +
653 info->var.vsync_len + info->var.upper_margin + 2;
654 vBlankStart = vDisplay;
655 vBlankEnd = vTotal + 1;
656 dotClock = 1000000000 / info->var.pixclock;
658 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
660 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
663 if (par->FlatPanel) {
666 vBlankStart = vStart;
669 hBlankEnd = hTotal + 4;
672 newmode.crtc[0x0] = Set8Bits (hTotal);
673 newmode.crtc[0x1] = Set8Bits (hDisplay);
674 newmode.crtc[0x2] = Set8Bits (hBlankStart);
675 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
676 newmode.crtc[0x4] = Set8Bits (hStart);
677 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
678 | SetBitField (hEnd, 4: 0, 4:0);
679 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
680 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
681 | SetBitField (vDisplay, 8: 8, 1:1)
682 | SetBitField (vStart, 8: 8, 2:2)
683 | SetBitField (vBlankStart, 8: 8, 3:3)
685 | SetBitField (vTotal, 9: 9, 5:5)
686 | SetBitField (vDisplay, 9: 9, 6:6)
687 | SetBitField (vStart, 9: 9, 7:7);
688 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
690 newmode.crtc[0x10] = Set8Bits (vStart);
691 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
693 newmode.crtc[0x12] = Set8Bits (vDisplay);
694 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
695 newmode.crtc[0x15] = Set8Bits (vBlankStart);
696 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
698 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
699 | SetBitField(vBlankStart,10:10,3:3)
700 | SetBitField(vStart,10:10,2:2)
701 | SetBitField(vDisplay,10:10,1:1)
702 | SetBitField(vTotal,10:10,0:0);
703 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
704 | SetBitField(hDisplay,8:8,1:1)
705 | SetBitField(hBlankStart,8:8,2:2)
706 | SetBitField(hStart,8:8,3:3);
707 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
708 | SetBitField(vDisplay,11:11,2:2)
709 | SetBitField(vStart,11:11,4:4)
710 | SetBitField(vBlankStart,11:11,6:6);
712 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
713 int tmp = (hTotal >> 1) & ~1;
714 newmode.ext.interlace = Set8Bits(tmp);
715 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
717 newmode.ext.interlace = 0xff; /* interlace off */
719 if (par->riva.Architecture >= NV_ARCH_10)
720 par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
722 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
723 newmode.misc_output &= ~0x40;
725 newmode.misc_output |= 0x40;
726 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
727 newmode.misc_output &= ~0x80;
729 newmode.misc_output |= 0x80;
731 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
732 hDisplaySize, height, dotClock);
734 newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
735 if (par->FlatPanel == 1) {
736 newmode.ext.pixel |= (1 << 7);
737 newmode.ext.scale |= (1 << 8);
739 if (par->SecondCRTC) {
740 newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
741 newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] | 0x00001000;
742 newmode.ext.crtcOwner = 3;
743 newmode.ext.pllsel |= 0x20000800;
744 newmode.ext.vpll2 = newmode.ext.vpll;
745 } else if (par->riva.twoHeads) {
746 newmode.ext.head = par->riva.PCRTC0[0x00000860/4] | 0x00001000;
747 newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
748 newmode.ext.crtcOwner = 0;
749 newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
751 if (par->FlatPanel == 1) {
752 newmode.ext.pixel |= (1 << 7);
753 newmode.ext.scale |= (1 << 8);
755 newmode.ext.cursorConfig = 0x02000100;
756 par->current_state = newmode;
757 riva_load_state(par, &par->current_state);
758 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
759 rivafb_blank(0, info);
763 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
766 var->xres = var->xres_virtual = modedb->xres;
767 var->yres = modedb->yres;
768 if (var->yres_virtual < var->yres)
769 var->yres_virtual = var->yres;
770 var->xoffset = var->yoffset = 0;
771 var->pixclock = modedb->pixclock;
772 var->left_margin = modedb->left_margin;
773 var->right_margin = modedb->right_margin;
774 var->upper_margin = modedb->upper_margin;
775 var->lower_margin = modedb->lower_margin;
776 var->hsync_len = modedb->hsync_len;
777 var->vsync_len = modedb->vsync_len;
778 var->sync = modedb->sync;
779 var->vmode = modedb->vmode;
784 * rivafb_do_maximize -
785 * @info: pointer to fb_info object containing info for current riva board
794 * -EINVAL on failure, 0 on success
800 static int rivafb_do_maximize(struct fb_info *info,
801 struct fb_var_screeninfo *var,
817 /* use highest possible virtual resolution */
818 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
819 printk(KERN_WARNING PFX
820 "using maximum available virtual resolution\n");
821 for (i = 0; modes[i].xres != -1; i++) {
822 if (modes[i].xres * nom / den * modes[i].yres <
826 if (modes[i].xres == -1) {
828 "could not find a virtual resolution that fits into video memory!!\n");
829 NVTRACE("EXIT - EINVAL error\n");
832 var->xres_virtual = modes[i].xres;
833 var->yres_virtual = modes[i].yres;
836 "virtual resolution set to maximum of %dx%d\n",
837 var->xres_virtual, var->yres_virtual);
838 } else if (var->xres_virtual == -1) {
839 var->xres_virtual = (info->fix.smem_len * den /
840 (nom * var->yres_virtual)) & ~15;
841 printk(KERN_WARNING PFX
842 "setting virtual X resolution to %d\n", var->xres_virtual);
843 } else if (var->yres_virtual == -1) {
844 var->xres_virtual = (var->xres_virtual + 15) & ~15;
845 var->yres_virtual = info->fix.smem_len * den /
846 (nom * var->xres_virtual);
847 printk(KERN_WARNING PFX
848 "setting virtual Y resolution to %d\n", var->yres_virtual);
850 var->xres_virtual = (var->xres_virtual + 15) & ~15;
851 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
853 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
854 var->xres, var->yres, var->bits_per_pixel);
855 NVTRACE("EXIT - EINVAL error\n");
860 if (var->xres_virtual * nom / den >= 8192) {
861 printk(KERN_WARNING PFX
862 "virtual X resolution (%d) is too high, lowering to %d\n",
863 var->xres_virtual, 8192 * den / nom - 16);
864 var->xres_virtual = 8192 * den / nom - 16;
867 if (var->xres_virtual < var->xres) {
869 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
873 if (var->yres_virtual < var->yres) {
875 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
878 if (var->yres_virtual > 0x7fff/nom)
879 var->yres_virtual = 0x7fff/nom;
880 if (var->xres_virtual > 0x7fff/nom)
881 var->xres_virtual = 0x7fff/nom;
887 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
889 RIVA_FIFO_FREE(par->riva, Patt, 4);
890 par->riva.Patt->Color0 = clr0;
891 par->riva.Patt->Color1 = clr1;
892 par->riva.Patt->Monochrome[0] = pat0;
893 par->riva.Patt->Monochrome[1] = pat1;
896 /* acceleration routines */
897 inline void wait_for_idle(struct riva_par *par)
899 while (par->riva.Busy(&par->riva));
903 * Set ROP. Translate X rop into ROP3. Internal routine.
906 riva_set_rop_solid(struct riva_par *par, int rop)
908 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
909 RIVA_FIFO_FREE(par->riva, Rop, 1);
910 par->riva.Rop->Rop3 = rop;
914 void riva_setup_accel(struct fb_info *info)
916 struct riva_par *par = (struct riva_par *) info->par;
918 RIVA_FIFO_FREE(par->riva, Clip, 2);
919 par->riva.Clip->TopLeft = 0x0;
920 par->riva.Clip->WidthHeight = (info->var.xres_virtual & 0xffff) |
921 (info->var.yres_virtual << 16);
922 riva_set_rop_solid(par, 0xcc);
927 * riva_get_cmap_len - query current color map length
928 * @var: standard kernel fb changeable data
931 * Get current color map length.
934 * Length of color map
939 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
941 int rc = 256; /* reasonable default */
943 switch (var->green.length) {
945 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
948 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
951 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
954 /* should not occur */
960 /* ------------------------------------------------------------------------- *
962 * Backlight operations
964 * ------------------------------------------------------------------------- */
966 #ifdef CONFIG_PMAC_BACKLIGHT
967 static int riva_set_backlight_enable(int on, int level, void *data)
969 struct riva_par *par = (struct riva_par *)data;
970 U032 tmp_pcrt, tmp_pmc;
972 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
973 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
974 if(on && (level > BACKLIGHT_OFF)) {
976 tmp_pmc |= (1 << 31); // backlight bit
977 tmp_pmc |= riva_backlight_levels[level-1] << 16; // level
979 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
980 par->riva.PMC[0x10F0/4] = tmp_pmc;
984 static int riva_set_backlight_level(int level, void *data)
986 return riva_set_backlight_enable(1, level, data);
988 #endif /* CONFIG_PMAC_BACKLIGHT */
990 /* ------------------------------------------------------------------------- *
992 * framebuffer operations
994 * ------------------------------------------------------------------------- */
996 static int rivafb_open(struct fb_info *info, int user)
998 struct riva_par *par = (struct riva_par *) info->par;
999 int cnt = atomic_read(&par->ref_count);
1004 memset(&par->state, 0, sizeof(struct vgastate));
1005 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1006 /* save the DAC for Riva128 */
1007 if (par->riva.Architecture == NV_ARCH_03)
1008 par->state.flags |= VGA_SAVE_CMAP;
1009 save_vga(&par->state);
1011 riva_common_setup(par);
1012 RivaGetConfig(&par->riva, par->Chipset);
1013 /* vgaHWunlock() + riva unlock (0x7F) */
1014 CRTCout(par, 0x11, 0xFF);
1015 par->riva.LockUnlock(&par->riva, 0);
1017 riva_save_state(par, &par->initial_state);
1019 atomic_inc(&par->ref_count);
1024 static int rivafb_release(struct fb_info *info, int user)
1026 struct riva_par *par = (struct riva_par *) info->par;
1027 int cnt = atomic_read(&par->ref_count);
1033 par->riva.LockUnlock(&par->riva, 0);
1034 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1035 riva_load_state(par, &par->initial_state);
1037 restore_vga(&par->state);
1039 par->riva.LockUnlock(&par->riva, 1);
1041 atomic_dec(&par->ref_count);
1046 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1048 struct fb_videomode *mode;
1049 struct riva_par *par = (struct riva_par *) info->par;
1050 int nom, den; /* translating from pixels->bytes */
1054 switch (var->bits_per_pixel) {
1056 var->red.offset = var->green.offset = var->blue.offset = 0;
1057 var->red.length = var->green.length = var->blue.length = 8;
1058 var->bits_per_pixel = 8;
1062 var->green.length = 5;
1065 var->bits_per_pixel = 16;
1066 /* The Riva128 supports RGB555 only */
1067 if (par->riva.Architecture == NV_ARCH_03)
1068 var->green.length = 5;
1069 if (var->green.length == 5) {
1070 /* 0rrrrrgg gggbbbbb */
1071 var->red.offset = 10;
1072 var->green.offset = 5;
1073 var->blue.offset = 0;
1074 var->red.length = 5;
1075 var->green.length = 5;
1076 var->blue.length = 5;
1078 /* rrrrrggg gggbbbbb */
1079 var->red.offset = 11;
1080 var->green.offset = 5;
1081 var->blue.offset = 0;
1082 var->red.length = 5;
1083 var->green.length = 6;
1084 var->blue.length = 5;
1090 var->red.length = var->green.length = var->blue.length = 8;
1091 var->bits_per_pixel = 32;
1092 var->red.offset = 16;
1093 var->green.offset = 8;
1094 var->blue.offset = 0;
1100 "mode %dx%dx%d rejected...color depth not supported.\n",
1101 var->xres, var->yres, var->bits_per_pixel);
1102 NVTRACE("EXIT, returning -EINVAL\n");
1107 if (!fb_validate_mode(var, info))
1111 /* calculate modeline if supported by monitor */
1112 if (!mode_valid && info->monspecs.gtf) {
1113 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1118 mode = fb_find_best_mode(var, &info->modelist);
1120 riva_update_var(var, mode);
1125 if (!mode_valid && !list_empty(&info->modelist))
1128 if (var->xres_virtual < var->xres)
1129 var->xres_virtual = var->xres;
1130 if (var->yres_virtual <= var->yres)
1131 var->yres_virtual = -1;
1132 if (rivafb_do_maximize(info, var, nom, den) < 0)
1135 if (var->xoffset < 0)
1137 if (var->yoffset < 0)
1140 /* truncate xoffset and yoffset to maximum if too high */
1141 if (var->xoffset > var->xres_virtual - var->xres)
1142 var->xoffset = var->xres_virtual - var->xres - 1;
1144 if (var->yoffset > var->yres_virtual - var->yres)
1145 var->yoffset = var->yres_virtual - var->yres - 1;
1147 var->red.msb_right =
1148 var->green.msb_right =
1149 var->blue.msb_right =
1150 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1155 static int rivafb_set_par(struct fb_info *info)
1157 struct riva_par *par = (struct riva_par *) info->par;
1160 riva_common_setup(par);
1161 RivaGetConfig(&par->riva, par->Chipset);
1162 /* vgaHWunlock() + riva unlock (0x7F) */
1163 CRTCout(par, 0x11, 0xFF);
1164 par->riva.LockUnlock(&par->riva, 0);
1166 riva_load_video_mode(info);
1167 riva_setup_accel(info);
1169 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1170 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1171 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1172 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1179 * rivafb_pan_display
1180 * @var: standard kernel fb changeable data
1182 * @info: pointer to fb_info object containing info for current riva board
1185 * Pan (or wrap, depending on the `vmode' field) the display using the
1186 * `xoffset' and `yoffset' fields of the `var' structure.
1187 * If the values don't fit, return -EINVAL.
1189 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1191 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1192 struct fb_info *info)
1194 struct riva_par *par = (struct riva_par *)info->par;
1198 if (var->xoffset > (var->xres_virtual - var->xres))
1200 if (var->yoffset > (var->yres_virtual - var->yres))
1203 if (var->vmode & FB_VMODE_YWRAP) {
1204 if (var->yoffset < 0
1205 || var->yoffset >= info->var.yres_virtual
1206 || var->xoffset) return -EINVAL;
1208 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1209 var->yoffset + info->var.yres > info->var.yres_virtual)
1213 base = var->yoffset * info->fix.line_length + var->xoffset;
1215 par->riva.SetStartAddress(&par->riva, base);
1217 info->var.xoffset = var->xoffset;
1218 info->var.yoffset = var->yoffset;
1220 if (var->vmode & FB_VMODE_YWRAP)
1221 info->var.vmode |= FB_VMODE_YWRAP;
1223 info->var.vmode &= ~FB_VMODE_YWRAP;
1228 static int rivafb_blank(int blank, struct fb_info *info)
1230 struct riva_par *par= (struct riva_par *)info->par;
1231 unsigned char tmp, vesa;
1233 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1234 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1239 switch (blank - 1) {
1240 case VESA_NO_BLANKING:
1242 case VESA_VSYNC_SUSPEND:
1245 case VESA_HSYNC_SUSPEND:
1248 case VESA_POWERDOWN:
1253 SEQout(par, 0x01, tmp);
1254 CRTCout(par, 0x1a, vesa);
1256 #ifdef CONFIG_PMAC_BACKLIGHT
1257 if ( par->FlatPanel && _machine == _MACH_Pmac) {
1258 set_backlight_enable(!blank);
1268 * @regno: register index
1269 * @red: red component
1270 * @green: green component
1271 * @blue: blue component
1272 * @transp: transparency
1273 * @info: pointer to fb_info object containing info for current riva board
1276 * Set a single color register. The values supplied have a 16 bit
1280 * Return != 0 for invalid regno.
1283 * fbcmap.c:fb_set_cmap()
1285 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1286 unsigned blue, unsigned transp,
1287 struct fb_info *info)
1289 struct riva_par *par = (struct riva_par *)info->par;
1290 RIVA_HW_INST *chip = &par->riva;
1293 if (regno >= riva_get_cmap_len(&info->var))
1296 if (info->var.grayscale) {
1297 /* gray = 0.30*R + 0.59*G + 0.11*B */
1298 red = green = blue =
1299 (red * 77 + green * 151 + blue * 28) >> 8;
1302 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1303 ((u32 *) info->pseudo_palette)[regno] =
1304 (regno << info->var.red.offset) |
1305 (regno << info->var.green.offset) |
1306 (regno << info->var.blue.offset);
1308 * The Riva128 2D engine requires color information in
1309 * TrueColor format even if framebuffer is in DirectColor
1311 if (par->riva.Architecture == NV_ARCH_03) {
1312 switch (info->var.bits_per_pixel) {
1314 par->palette[regno] = ((red & 0xf800) >> 1) |
1315 ((green & 0xf800) >> 6) |
1316 ((blue & 0xf800) >> 11);
1319 par->palette[regno] = ((red & 0xff00) << 8) |
1320 ((green & 0xff00)) |
1321 ((blue & 0xff00) >> 8);
1327 switch (info->var.bits_per_pixel) {
1329 /* "transparent" stuff is completely ignored. */
1330 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1333 if (info->var.green.length == 5) {
1334 for (i = 0; i < 8; i++) {
1335 riva_wclut(chip, regno*8+i, red >> 8,
1336 green >> 8, blue >> 8);
1342 for (i = 0; i < 8; i++) {
1343 riva_wclut(chip, regno*8+i,
1344 red >> 8, green >> 8,
1348 riva_rclut(chip, regno*4, &r, &g, &b);
1349 for (i = 0; i < 4; i++)
1350 riva_wclut(chip, regno*4+i, r,
1355 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1365 * rivafb_fillrect - hardware accelerated color fill function
1366 * @info: pointer to fb_info structure
1367 * @rect: pointer to fb_fillrect structure
1370 * This function fills up a region of framebuffer memory with a solid
1371 * color with a choice of two different ROP's, copy or invert.
1376 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1378 struct riva_par *par = (struct riva_par *) info->par;
1379 u_int color, rop = 0;
1381 if (info->var.bits_per_pixel == 8)
1382 color = rect->color;
1384 if (par->riva.Architecture != NV_ARCH_03)
1385 color = ((u32 *)info->pseudo_palette)[rect->color];
1387 color = par->palette[rect->color];
1390 switch (rect->rop) {
1400 riva_set_rop_solid(par, rop);
1402 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1403 par->riva.Bitmap->Color1A = color;
1405 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1406 par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
1407 (rect->dx << 16) | rect->dy;
1409 par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
1410 (rect->width << 16) | rect->height;
1412 riva_set_rop_solid(par, 0xcc);
1417 * rivafb_copyarea - hardware accelerated blit function
1418 * @info: pointer to fb_info structure
1419 * @region: pointer to fb_copyarea structure
1422 * This copies an area of pixels from one location to another
1427 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1429 struct riva_par *par = (struct riva_par *) info->par;
1431 RIVA_FIFO_FREE(par->riva, Blt, 3);
1432 par->riva.Blt->TopLeftSrc = (region->sy << 16) | region->sx;
1433 par->riva.Blt->TopLeftDst = (region->dy << 16) | region->dx;
1435 par->riva.Blt->WidthHeight = (region->height << 16) | region->width;
1439 static inline void convert_bgcolor_16(u32 *col)
1441 *col = ((*col & 0x0000F800) << 8)
1442 | ((*col & 0x00007E0) << 5)
1443 | ((*col & 0x0000001F) << 3)
1449 * rivafb_imageblit: hardware accelerated color expand function
1450 * @info: pointer to fb_info structure
1451 * @image: pointer to fb_image structure
1454 * If the source is a monochrome bitmap, the function fills up a a region
1455 * of framebuffer memory with pixels whose color is determined by the bit
1456 * setting of the bitmap, 1 - foreground, 0 - background.
1458 * If the source is not a monochrome bitmap, color expansion is not done.
1459 * In this case, it is channeled to a software function.
1464 static void rivafb_imageblit(struct fb_info *info,
1465 const struct fb_image *image)
1467 struct riva_par *par = (struct riva_par *) info->par;
1468 u32 fgx = 0, bgx = 0, width, tmp;
1469 u8 *cdat = (u8 *) image->data;
1473 if (image->depth != 1) {
1474 cfb_imageblit(info, image);
1478 switch (info->var.bits_per_pixel) {
1480 fgx = image->fg_color;
1481 bgx = image->bg_color;
1485 if (par->riva.Architecture != NV_ARCH_03) {
1486 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1487 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1489 fgx = par->palette[image->fg_color];
1490 bgx = par->palette[image->bg_color];
1492 if (info->var.green.length == 6)
1493 convert_bgcolor_16(&bgx);
1497 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1498 par->riva.Bitmap->ClipE.TopLeft =
1499 (image->dy << 16) | (image->dx & 0xFFFF);
1500 par->riva.Bitmap->ClipE.BottomRight =
1501 (((image->dy + image->height) << 16) |
1502 ((image->dx + image->width) & 0xffff));
1503 par->riva.Bitmap->Color0E = bgx;
1504 par->riva.Bitmap->Color1E = fgx;
1505 par->riva.Bitmap->WidthHeightInE =
1506 (image->height << 16) | ((image->width + 31) & ~31);
1507 par->riva.Bitmap->WidthHeightOutE =
1508 (image->height << 16) | ((image->width + 31) & ~31);
1509 par->riva.Bitmap->PointE =
1510 (image->dy << 16) | (image->dx & 0xFFFF);
1512 d = &par->riva.Bitmap->MonochromeData01E;
1514 width = (image->width + 31)/32;
1515 size = width * image->height;
1516 while (size >= 16) {
1517 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1518 for (i = 0; i < 16; i++) {
1519 tmp = *((u32 *)cdat);
1520 cdat = (u8 *)((u32 *)cdat + 1);
1521 reverse_order(&tmp);
1527 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1528 for (i = 0; i < size; i++) {
1529 tmp = *((u32 *) cdat);
1530 cdat = (u8 *)((u32 *)cdat + 1);
1531 reverse_order(&tmp);
1538 * rivafb_cursor - hardware cursor function
1539 * @info: pointer to info structure
1540 * @cursor: pointer to fbcursor structure
1543 * A cursor function that supports displaying a cursor image via hardware.
1544 * Within the kernel, copy and invert rops are supported. If exported
1545 * to user space, only the copy rop will be supported.
1550 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1552 struct riva_par *par = (struct riva_par *) info->par;
1553 u8 data[MAX_CURS * MAX_CURS/8];
1557 par->riva.ShowHideCursor(&par->riva, 0);
1559 if (cursor->set & FB_CUR_SETPOS) {
1562 info->cursor.image.dx = cursor->image.dx;
1563 info->cursor.image.dy = cursor->image.dy;
1564 yy = cursor->image.dy - info->var.yoffset;
1565 xx = cursor->image.dx - info->var.xoffset;
1569 par->riva.PRAMDAC[0x0000300/4] = temp;
1572 if (cursor->set & FB_CUR_SETSIZE) {
1573 info->cursor.image.height = cursor->image.height;
1574 info->cursor.image.width = cursor->image.width;
1575 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1578 if (cursor->set & FB_CUR_SETCMAP) {
1579 info->cursor.image.bg_color = cursor->image.bg_color;
1580 info->cursor.image.fg_color = cursor->image.fg_color;
1583 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETCUR)) {
1584 u32 bg_idx = info->cursor.image.bg_color;
1585 u32 fg_idx = info->cursor.image.fg_color;
1586 u32 s_pitch = (info->cursor.image.width+7) >> 3;
1587 u32 d_pitch = MAX_CURS/8;
1588 u8 *dat = (u8 *) cursor->image.data;
1589 u8 *msk = (u8 *) info->cursor.mask;
1592 info->cursor.image.data = cursor->image.data;
1593 switch (info->cursor.rop) {
1595 for (i = 0; i < s_pitch * info->cursor.image.height;
1597 src[i] = dat[i] ^ msk[i];
1601 for (i = 0; i < s_pitch * info->cursor.image.height;
1603 src[i] = dat[i] & msk[i];
1607 fb_sysmove_buf_aligned(info, &info->sprite, data, d_pitch, src,
1608 s_pitch, info->cursor.image.height);
1610 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1611 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1612 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1614 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1615 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1616 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1618 par->riva.LockUnlock(&par->riva, 0);
1620 rivafb_load_cursor_image(par, data, bg, fg,
1621 info->cursor.image.width,
1622 info->cursor.image.height);
1624 if (info->cursor.enable)
1625 par->riva.ShowHideCursor(&par->riva, 1);
1629 static int rivafb_sync(struct fb_info *info)
1631 struct riva_par *par = (struct riva_par *)info->par;
1637 /* ------------------------------------------------------------------------- *
1639 * initialization helper functions
1641 * ------------------------------------------------------------------------- */
1643 /* kernel interface */
1644 static struct fb_ops riva_fb_ops = {
1645 .owner = THIS_MODULE,
1646 .fb_open = rivafb_open,
1647 .fb_release = rivafb_release,
1648 .fb_check_var = rivafb_check_var,
1649 .fb_set_par = rivafb_set_par,
1650 .fb_setcolreg = rivafb_setcolreg,
1651 .fb_pan_display = rivafb_pan_display,
1652 .fb_blank = rivafb_blank,
1653 .fb_fillrect = rivafb_fillrect,
1654 .fb_copyarea = rivafb_copyarea,
1655 .fb_imageblit = rivafb_imageblit,
1656 .fb_cursor = rivafb_cursor,
1657 .fb_sync = rivafb_sync,
1660 static int __devinit riva_set_fbinfo(struct fb_info *info)
1662 unsigned int cmap_len;
1663 struct riva_par *par = (struct riva_par *) info->par;
1666 info->flags = FBINFO_DEFAULT
1667 | FBINFO_HWACCEL_XPAN
1668 | FBINFO_HWACCEL_YPAN
1669 | FBINFO_HWACCEL_COPYAREA
1670 | FBINFO_HWACCEL_FILLRECT
1671 | FBINFO_HWACCEL_IMAGEBLIT
1672 | FBINFO_MISC_MODESWITCHLATE;
1673 info->var = rivafb_default_var;
1674 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1675 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1677 info->pseudo_palette = par->pseudo_palette;
1679 cmap_len = riva_get_cmap_len(&info->var);
1680 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1682 info->pixmap.size = 64 * 1024;
1683 info->pixmap.buf_align = 4;
1684 info->pixmap.scan_align = 4;
1685 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1686 info->var.yres_virtual = -1;
1688 return (rivafb_check_var(&info->var, info));
1691 #ifdef CONFIG_PPC_OF
1692 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1694 struct riva_par *par = (struct riva_par *) info->par;
1695 struct device_node *dp;
1696 unsigned char *pedid = NULL;
1697 unsigned char *disptype = NULL;
1698 static char *propnames[] = {
1699 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1703 dp = pci_device_to_OF_node(pd);
1704 for (; dp != NULL; dp = dp->child) {
1705 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1706 if (disptype == NULL)
1708 if (strncmp(disptype, "LCD", 3) != 0)
1710 for (i = 0; propnames[i] != NULL; ++i) {
1711 pedid = (unsigned char *)
1712 get_property(dp, propnames[i], NULL);
1713 if (pedid != NULL) {
1722 #endif /* CONFIG_PPC_OF */
1724 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1725 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1727 struct riva_par *par = (struct riva_par *) info->par;
1731 riva_create_i2c_busses(par);
1732 for (i = par->bus; i >= 1; i--) {
1733 riva_probe_i2c_connector(par, i, &par->EDID);
1735 printk("rivafb: Found EDID Block from BUS %i\n", i);
1740 return (par->EDID) ? 1 : 0;
1742 #endif /* CONFIG_FB_RIVA_I2C */
1744 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1745 struct fb_info *info)
1747 struct fb_monspecs *specs = &info->monspecs;
1748 struct fb_videomode modedb;
1751 /* respect mode options */
1753 fb_find_mode(var, info, mode_option,
1754 specs->modedb, specs->modedb_len,
1756 } else if (specs->modedb != NULL) {
1757 /* get preferred timing */
1758 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1761 for (i = 0; i < specs->modedb_len; i++) {
1762 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1763 modedb = specs->modedb[i];
1768 /* otherwise, get first mode in database */
1769 modedb = specs->modedb[0];
1771 var->bits_per_pixel = 8;
1772 riva_update_var(var, &modedb);
1774 var->accel_flags |= FB_ACCELF_TEXT;
1779 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1782 #ifdef CONFIG_PPC_OF
1783 if (!riva_get_EDID_OF(info, pdev))
1784 printk("rivafb: could not retrieve EDID from OF\n");
1785 #elif CONFIG_FB_RIVA_I2C
1786 if (!riva_get_EDID_i2c(info))
1787 printk("rivafb: could not retrieve EDID from DDC/I2C\n");
1793 static void __devinit riva_get_edidinfo(struct fb_info *info)
1795 struct fb_var_screeninfo *var = &rivafb_default_var;
1796 struct riva_par *par = (struct riva_par *) info->par;
1798 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1799 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1801 riva_update_default_var(var, info);
1803 /* if user specified flatpanel, we respect that */
1804 if (info->monspecs.input & FB_DISP_DDI)
1808 /* ------------------------------------------------------------------------- *
1812 * ------------------------------------------------------------------------- */
1814 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1818 switch (pd->device & 0x0ff0) {
1819 case 0x0100: /* GeForce 256 */
1820 case 0x0110: /* GeForce2 MX */
1821 case 0x0150: /* GeForce2 */
1822 case 0x0170: /* GeForce4 MX */
1823 case 0x0180: /* GeForce4 MX (8x AGP) */
1824 case 0x01A0: /* nForce */
1825 case 0x01F0: /* nForce2 */
1828 case 0x0200: /* GeForce3 */
1829 case 0x0250: /* GeForce4 Ti */
1830 case 0x0280: /* GeForce4 Ti (8x AGP) */
1833 case 0x0300: /* GeForceFX 5800 */
1834 case 0x0310: /* GeForceFX 5600 */
1835 case 0x0320: /* GeForceFX 5200 */
1836 case 0x0330: /* GeForceFX 5900 */
1837 case 0x0340: /* GeForceFX 5700 */
1840 case 0x0020: /* TNT, TNT2 */
1843 case 0x0010: /* Riva128 */
1846 default: /* unknown architecture */
1852 static int __devinit rivafb_probe(struct pci_dev *pd,
1853 const struct pci_device_id *ent)
1855 struct riva_par *default_par;
1856 struct fb_info *info;
1861 info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
1865 default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
1869 memset(info, 0, sizeof(struct fb_info));
1870 memset(default_par, 0, sizeof(struct riva_par));
1871 default_par->pdev = pd;
1873 info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
1874 if (info->pixmap.addr == NULL)
1875 goto err_out_kfree1;
1876 memset(info->pixmap.addr, 0, 64 * 1024);
1878 if (pci_enable_device(pd)) {
1879 printk(KERN_ERR PFX "cannot enable PCI device\n");
1880 goto err_out_enable;
1883 if (pci_request_regions(pd, "rivafb")) {
1884 printk(KERN_ERR PFX "cannot request PCI regions\n");
1885 goto err_out_request;
1888 default_par->riva.Architecture = riva_get_arch(pd);
1890 default_par->Chipset = (pd->vendor << 16) | pd->device;
1891 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1893 #ifdef CONFIG_PCI_NAMES
1894 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1897 if(default_par->riva.Architecture == 0) {
1898 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1899 goto err_out_kfree1;
1901 if(default_par->riva.Architecture == NV_ARCH_10 ||
1902 default_par->riva.Architecture == NV_ARCH_20 ||
1903 default_par->riva.Architecture == NV_ARCH_30) {
1904 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1906 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1909 default_par->FlatPanel = flatpanel;
1911 printk(KERN_INFO PFX "flatpanel support enabled\n");
1912 default_par->forceCRTC = forceCRTC;
1914 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1915 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1918 /* enable IO and mem if not already done */
1921 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1922 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1923 pci_write_config_word(pd, PCI_COMMAND, cmd);
1926 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1927 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1929 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1930 rivafb_fix.mmio_len);
1931 if (!default_par->ctrl_base) {
1932 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1933 goto err_out_free_base0;
1936 info->par = default_par;
1938 switch (default_par->riva.Architecture) {
1940 /* Riva128's PRAMIN is in the "framebuffer" space
1941 * Since these cards were never made with more than 8 megabytes
1942 * we can safely allocate this separately.
1944 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1945 if (!default_par->riva.PRAMIN) {
1946 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1947 goto err_out_free_nv3_pramin;
1949 rivafb_fix.accel = FB_ACCEL_NV3;
1955 default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
1956 default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
1957 rivafb_fix.accel = FB_ACCEL_NV4;
1961 riva_common_setup(default_par);
1963 if (default_par->riva.Architecture == NV_ARCH_03) {
1964 default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
1967 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
1968 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
1969 info->screen_base = ioremap(rivafb_fix.smem_start,
1970 rivafb_fix.smem_len);
1971 if (!info->screen_base) {
1972 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1973 goto err_out_free_base1;
1978 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
1979 rivafb_fix.smem_len,
1980 MTRR_TYPE_WRCOMB, 1);
1981 if (default_par->mtrr.vram < 0) {
1982 printk(KERN_ERR PFX "unable to setup MTRR\n");
1984 default_par->mtrr.vram_valid = 1;
1985 /* let there be speed */
1986 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
1989 #endif /* CONFIG_MTRR */
1991 info->fbops = &riva_fb_ops;
1992 info->fix = rivafb_fix;
1993 riva_get_EDID(info, pd);
1994 riva_get_edidinfo(info);
1996 if (riva_set_fbinfo(info) < 0) {
1997 printk(KERN_ERR PFX "error setting initial video mode\n");
1998 goto err_out_iounmap_fb;
2001 fb_destroy_modedb(info->monspecs.modedb);
2002 info->monspecs.modedb_len = 0;
2003 info->monspecs.modedb = NULL;
2005 if (register_framebuffer(info) < 0) {
2007 "error registering riva framebuffer\n");
2008 goto err_out_iounmap_fb;
2011 pci_set_drvdata(pd, info);
2013 printk(KERN_INFO PFX
2014 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2017 info->fix.smem_len / (1024 * 1024),
2018 info->fix.smem_start);
2019 #ifdef CONFIG_PMAC_BACKLIGHT
2020 if (default_par->FlatPanel && _machine == _MACH_Pmac)
2021 register_backlight_controller(&riva_backlight_controller,
2022 default_par, "mnca");
2028 #ifdef CONFIG_FB_RIVA_I2C
2029 riva_delete_i2c_busses((struct riva_par *) info->par);
2031 iounmap(info->screen_base);
2033 if (default_par->riva.Architecture == NV_ARCH_03)
2034 iounmap((caddr_t)default_par->riva.PRAMIN);
2035 err_out_free_nv3_pramin:
2036 iounmap(default_par->ctrl_base);
2038 pci_release_regions(pd);
2040 pci_disable_device(pd);
2042 kfree(info->pixmap.addr);
2051 static void __exit rivafb_remove(struct pci_dev *pd)
2053 struct fb_info *info = pci_get_drvdata(pd);
2054 struct riva_par *par = (struct riva_par *) info->par;
2060 #ifdef CONFIG_FB_RIVA_I2C
2061 riva_delete_i2c_busses(par);
2066 unregister_framebuffer(info);
2068 if (par->mtrr.vram_valid)
2069 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2070 info->fix.smem_len);
2071 #endif /* CONFIG_MTRR */
2073 iounmap(par->ctrl_base);
2074 iounmap(info->screen_base);
2075 if (par->riva.Architecture == NV_ARCH_03)
2076 iounmap((caddr_t)par->riva.PRAMIN);
2077 pci_release_regions(pd);
2078 pci_disable_device(pd);
2079 kfree(info->pixmap.addr);
2082 pci_set_drvdata(pd, NULL);
2086 /* ------------------------------------------------------------------------- *
2090 * ------------------------------------------------------------------------- */
2093 int __init rivafb_setup(char *options)
2098 if (!options || !*options)
2101 while ((this_opt = strsep(&options, ",")) != NULL) {
2102 if (!strncmp(this_opt, "forceCRTC", 9)) {
2106 if (!*p || !*(++p)) continue;
2107 forceCRTC = *p - '0';
2108 if (forceCRTC < 0 || forceCRTC > 1)
2110 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2113 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2116 } else if (!strncmp(this_opt, "strictmode", 10)) {
2119 mode_option = this_opt;
2124 #endif /* !MODULE */
2126 static struct pci_driver rivafb_driver = {
2128 .id_table = rivafb_pci_tbl,
2129 .probe = rivafb_probe,
2130 .remove = __exit_p(rivafb_remove),
2135 /* ------------------------------------------------------------------------- *
2139 * ------------------------------------------------------------------------- */
2141 int __devinit rivafb_init(void)
2144 char *option = NULL;
2146 if (fb_get_options("rivafb", &option))
2148 rivafb_setup(option);
2150 if (pci_register_driver(&rivafb_driver) > 0)
2152 pci_unregister_driver(&rivafb_driver);
2157 module_init(rivafb_init);
2160 static void __exit rivafb_exit(void)
2162 pci_unregister_driver(&rivafb_driver);
2165 module_exit(rivafb_exit);
2167 MODULE_PARM(flatpanel, "i");
2168 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2169 MODULE_PARM(forceCRTC, "i");
2170 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2173 MODULE_PARM(nomtrr, "i");
2174 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2176 MODULE_PARM(strictmode, "i");
2177 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2180 MODULE_AUTHOR("Ani Joshi, maintainer");
2181 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2182 MODULE_LICENSE("GPL");