2 * linux/drivers/video/sa1100fb.c
4 * Copyright (C) 1999 Eric A. Thomas
5 * Based on acornfb.c Copyright (C) Russell King.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
11 * StrongARM 1100 LCD Controller Frame Buffer Driver
13 * Please direct your questions and comments on this driver to the following
16 * linux-arm-kernel@lists.arm.linux.org.uk
18 * Clean patches should be sent to the ARM Linux Patch System. Please see the
19 * following web page for more information:
21 * http://www.arm.linux.org.uk/developer/patches/info.shtml
26 * - With the Neponset plugged into an Assabet, LCD powerdown
27 * doesn't work (LCD stays powered up). Therefore we shouldn't
29 * - We don't limit the CPU clock rate nor the mode selection
30 * according to the available SDRAM bandwidth.
33 * - Linear grayscale palettes and the kernel.
34 * Such code does not belong in the kernel. The kernel frame buffer
35 * drivers do not expect a linear colourmap, but a colourmap based on
36 * the VT100 standard mapping.
38 * If your _userspace_ requires a linear colourmap, then the setup of
39 * such a colourmap belongs _in userspace_, not in the kernel. Code
40 * to set the colourmap correctly from user space has been sent to
41 * David Neuer. It's around 8 lines of C code, plus another 4 to
42 * detect if we are using grayscale.
44 * - The following must never be specified in a panel definition:
45 * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
47 * - The following should be specified:
48 * either LCCR0_Color or LCCR0_Mono
49 * either LCCR0_Sngl or LCCR0_Dual
50 * either LCCR0_Act or LCCR0_Pas
51 * either LCCR3_OutEnH or LCCD3_OutEnL
52 * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
53 * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
57 * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
58 * resolutions are working, but only the 8bpp mode is supported.
59 * Changes need to be made to the palette encode and decode routines
60 * to support 4 and 16 bpp modes.
61 * Driver is not designed to be a module. The FrameBuffer is statically
62 * allocated since dynamic allocation of a 300k buffer cannot be
66 * - FrameBuffer memory is now allocated at run-time when the
67 * driver is initialized.
69 * 2000/04/10: Nicolas Pitre <nico@cam.org>
70 * - Big cleanup for dynamic selection of machine type at run time.
72 * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
73 * - Support for Bitsy aka Compaq iPAQ H3600 added.
75 * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
76 * Jeff Sutherland <jsutherland@accelent.com>
77 * - Resolved an issue caused by a change made to the Assabet's PLD
78 * earlier this year which broke the framebuffer driver for newer
79 * Phase 4 Assabets. Some other parameters were changed to optimize
80 * for the Sharp display.
82 * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
83 * - XP860 support added
85 * 2000/08/19: Mark Huang <mhuang@livetoy.com>
86 * - Allows standard options to be passed on the kernel command line
87 * for most common passive displays.
90 * - s/save_flags_cli/local_irq_save/
91 * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
93 * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
94 * - Updated LART stuff. Fixed some minor bugs.
96 * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
97 * - Pangolin support added
99 * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
100 * - Huw Webpanel support added
102 * 2000/11/23: Eric Peng <ericpeng@coventive.com>
105 * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
106 * Cliff Brake <cbrake@accelent.com>
107 * - Added PM callback
109 * 2001/05/26: <rmk@arm.linux.org.uk>
110 * - Fix 16bpp so that (a) we use the right colours rather than some
111 * totally random colour depending on what was in page 0, and (b)
112 * we don't de-reference a NULL pointer.
113 * - remove duplicated implementation of consistent_alloc()
114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial
118 * - remove allow_modeset (acornfb idea does not belong here)
120 * 2001/05/28: <rmk@arm.linux.org.uk>
121 * - massive cleanup - move machine dependent data into structures
122 * - I've left various #warnings in - if you see one, and know
123 * the hardware concerned, please get in contact with me.
125 * 2001/05/31: <rmk@arm.linux.org.uk>
126 * - Fix LCCR1 HSW value, fix all machine type specifications to
127 * keep values in line. (Please check your machine type specs)
129 * 2001/06/10: <rmk@arm.linux.org.uk>
130 * - Fiddle with the LCD controller from task context only; mainly
131 * so that we can run with interrupts on, and sleep.
132 * - Convert #warnings into #errors. No pain, no gain. ;)
134 * 2001/06/14: <rmk@arm.linux.org.uk>
135 * - Make the palette BPS value for 12bpp come out correctly.
136 * - Take notice of "greyscale" on any colour depth.
137 * - Make truecolor visuals use the RGB channel encoding information.
139 * 2001/07/02: <rmk@arm.linux.org.uk>
140 * - Fix colourmap problems.
142 * 2001/07/13: <abraham@2d3d.co.za>
143 * - Added support for the ICP LCD-Kit01 on LART. This LCD is
144 * manufactured by Prime View, model no V16C6448AB
146 * 2001/07/23: <rmk@arm.linux.org.uk>
147 * - Hand merge version from handhelds.org CVS tree. See patch
148 * notes for 595/1 for more information.
149 * - Drop 12bpp (it's 16bpp with different colour register mappings).
150 * - This hardware can not do direct colour. Therefore we don't
153 * 2001/07/27: <rmk@arm.linux.org.uk>
154 * - Halve YRES on dual scan LCDs.
156 * 2001/08/22: <rmk@arm.linux.org.uk>
157 * - Add b/w iPAQ pixclock value.
159 * 2001/10/12: <rmk@arm.linux.org.uk>
160 * - Add patch 681/1 and clean up stork definitions.
163 #include <linux/config.h>
164 #include <linux/module.h>
165 #include <linux/kernel.h>
166 #include <linux/sched.h>
167 #include <linux/errno.h>
168 #include <linux/string.h>
169 #include <linux/interrupt.h>
170 #include <linux/slab.h>
171 #include <linux/fb.h>
172 #include <linux/delay.h>
173 #include <linux/init.h>
174 #include <linux/ioport.h>
175 #include <linux/cpufreq.h>
176 #include <linux/device.h>
177 #include <linux/dma-mapping.h>
179 #include <asm/hardware.h>
182 #include <asm/mach-types.h>
183 #include <asm/uaccess.h>
184 #include <asm/arch/assabet.h>
185 #include <asm/arch/shannon.h>
192 * Complain if VAR is out of range.
196 #undef ASSABET_PAL_VIDEO
198 #include "sa1100fb.h"
200 extern void (*sa1100fb_backlight_power)(int on);
201 extern void (*sa1100fb_lcd_power)(int on);
204 * IMHO this looks wrong. In 8BPP, length should be 8.
206 static struct sa1100fb_rgb rgb_8 = {
207 .red = { .offset = 0, .length = 4, },
208 .green = { .offset = 0, .length = 4, },
209 .blue = { .offset = 0, .length = 4, },
210 .transp = { .offset = 0, .length = 0, },
213 static struct sa1100fb_rgb def_rgb_16 = {
214 .red = { .offset = 11, .length = 5, },
215 .green = { .offset = 5, .length = 6, },
216 .blue = { .offset = 0, .length = 5, },
217 .transp = { .offset = 0, .length = 0, },
220 #ifdef CONFIG_SA1100_ASSABET
221 #ifndef ASSABET_PAL_VIDEO
223 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
224 * takes an RGB666 signal, but we provide it with an RGB565 signal
225 * instead (def_rgb_16).
227 static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
228 .pixclock = 171521, .bpp = 16,
229 .xres = 320, .yres = 240,
231 .hsync_len = 5, .vsync_len = 1,
232 .left_margin = 61, .upper_margin = 3,
233 .right_margin = 9, .lower_margin = 0,
235 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
237 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
238 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
241 static struct sa1100fb_mach_info pal_info __initdata = {
242 .pixclock = 67797, .bpp = 16,
243 .xres = 640, .yres = 512,
245 .hsync_len = 64, .vsync_len = 6,
246 .left_margin = 125, .upper_margin = 70,
247 .right_margin = 115, .lower_margin = 36,
249 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
250 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
255 #ifdef CONFIG_SA1100_H3800
256 static struct sa1100fb_mach_info h3800_info __initdata = {
257 .pixclock = 174757, .bpp = 16,
258 .xres = 320, .yres = 240,
260 .hsync_len = 3, .vsync_len = 3,
261 .left_margin = 12, .upper_margin = 10,
262 .right_margin = 17, .lower_margin = 1,
266 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
267 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
271 #ifdef CONFIG_SA1100_H3600
272 static struct sa1100fb_mach_info h3600_info __initdata = {
273 .pixclock = 174757, .bpp = 16,
274 .xres = 320, .yres = 240,
276 .hsync_len = 3, .vsync_len = 3,
277 .left_margin = 12, .upper_margin = 10,
278 .right_margin = 17, .lower_margin = 1,
282 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
283 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
286 static struct sa1100fb_rgb h3600_rgb_16 = {
287 .red = { .offset = 12, .length = 4, },
288 .green = { .offset = 7, .length = 4, },
289 .blue = { .offset = 1, .length = 4, },
290 .transp = { .offset = 0, .length = 0, },
294 #ifdef CONFIG_SA1100_H3100
295 static struct sa1100fb_mach_info h3100_info __initdata = {
296 .pixclock = 406977, .bpp = 4,
297 .xres = 320, .yres = 240,
299 .hsync_len = 26, .vsync_len = 41,
300 .left_margin = 4, .upper_margin = 0,
301 .right_margin = 4, .lower_margin = 0,
303 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
307 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
308 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
312 #ifdef CONFIG_SA1100_BRUTUS
313 static struct sa1100fb_mach_info brutus_info __initdata = {
314 .pixclock = 0, .bpp = 8,
315 .xres = 320, .yres = 240,
317 .hsync_len = 3, .vsync_len = 1,
318 .left_margin = 41, .upper_margin = 0,
319 .right_margin = 101, .lower_margin = 0,
321 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
323 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
324 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
329 #ifdef CONFIG_SA1100_FREEBIRD
330 #warning Please check this carefully
331 static struct sa1100fb_mach_info freebird_info __initdata = {
332 .pixclock = 171521, .bpp = 16,
333 .xres = 240, .yres = 320,
335 .hsync_len = 3, .vsync_len = 2,
336 .left_margin = 2, .upper_margin = 0,
337 .right_margin = 2, .lower_margin = 0,
339 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
341 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
342 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(2),
345 static struct sa1100fb_rgb freebird_rgb_16 = {
346 .red = { .offset = 8, .length = 4, },
347 .green = { .offset = 4, .length = 4, },
348 .blue = { .offset = 0, .length = 4, },
349 .transp = { .offset = 12, .length = 4, },
353 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
354 static struct sa1100fb_mach_info graphicsclient_info __initdata = {
355 .pixclock = 53500, .bpp = 8,
356 .xres = 640, .yres = 480,
358 .hsync_len = 9, .vsync_len = 9,
359 .left_margin = 54, .upper_margin = 24,
360 .right_margin = 54, .lower_margin = 32,
362 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
363 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
367 #ifdef CONFIG_SA1100_HUW_WEBPANEL
368 static struct sa1100fb_mach_info huw_webpanel_info __initdata = {
369 .pixclock = 0, .bpp = 8,
370 .xres = 640, .yres = 480,
372 .hsync_len = 3, .vsync_len = 1,
373 .left_margin = 41, .upper_margin = 0,
374 .right_margin = 101, .lower_margin = 0,
376 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
378 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
379 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) | 8,
382 * FIXME: please get rid of the '| 8' in preference to an
383 * LCCR3_PixClkDiv() version. --rmk
389 static struct sa1100fb_mach_info lart_grey_info __initdata = {
390 .pixclock = 150000, .bpp = 4,
391 .xres = 320, .yres = 240,
393 .hsync_len = 1, .vsync_len = 1,
394 .left_margin = 4, .upper_margin = 0,
395 .right_margin = 2, .lower_margin = 0,
398 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
400 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
401 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
404 #ifdef LART_COLOR_LCD
405 static struct sa1100fb_mach_info lart_color_info __initdata = {
406 .pixclock = 150000, .bpp = 16,
407 .xres = 320, .yres = 240,
409 .hsync_len = 2, .vsync_len = 3,
410 .left_margin = 69, .upper_margin = 14,
411 .right_margin = 8, .lower_margin = 4,
413 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
414 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
417 #ifdef LART_VIDEO_OUT
418 static struct sa1100fb_mach_info lart_video_info __initdata = {
419 .pixclock = 39721, .bpp = 16,
420 .xres = 640, .yres = 480,
422 .hsync_len = 95, .vsync_len = 2,
423 .left_margin = 40, .upper_margin = 32,
424 .right_margin = 24, .lower_margin = 11,
426 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
428 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
429 .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
433 #ifdef LART_KIT01_LCD
434 static struct sa1100fb_mach_info lart_kit01_info __initdata = {
435 .pixclock = 63291, .bpp = 16,
436 .xres = 640, .yres = 480,
438 .hsync_len = 64, .vsync_len = 3,
439 .left_margin = 122, .upper_margin = 45,
440 .right_margin = 10, .lower_margin = 10,
442 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
443 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
447 #ifdef CONFIG_SA1100_SHANNON
448 static struct sa1100fb_mach_info shannon_info __initdata = {
449 .pixclock = 152500, .bpp = 8,
450 .xres = 640, .yres = 480,
452 .hsync_len = 4, .vsync_len = 3,
453 .left_margin = 2, .upper_margin = 0,
454 .right_margin = 1, .lower_margin = 0,
456 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
458 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
459 .lccr3 = LCCR3_ACBsDiv(512),
463 #ifdef CONFIG_SA1100_OMNIMETER
464 static struct sa1100fb_mach_info omnimeter_info __initdata = {
465 .pixclock = 0, .bpp = 4,
466 .xres = 480, .yres = 320,
468 .hsync_len = 1, .vsync_len = 1,
469 .left_margin = 10, .upper_margin = 0,
470 .right_margin = 10, .lower_margin = 0,
473 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
475 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_8PixMono,
476 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(255) |
478 #error FIXME: fix pixclock, ACBsDiv
480 * FIXME: I think ACBsDiv is wrong above - should it be 512 (disabled)?
486 #ifdef CONFIG_SA1100_PANGOLIN
487 static struct sa1100fb_mach_info pangolin_info __initdata = {
488 .pixclock = 341521, .bpp = 16,
489 .xres = 800, .yres = 600,
491 .hsync_len = 64, .vsync_len = 7,
492 .left_margin = 160, .upper_margin = 7,
493 .right_margin = 24, .lower_margin = 1,
495 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
497 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
498 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsCntOff,
502 #ifdef CONFIG_SA1100_STORK
503 #if STORK_TFT /* ie the NEC TFT */
505 * pixclock is ps per clock. say 72Hz, 800x600 clocks => (1/72)/(800*600)
507 * NB likely to be increased to ease bus timings wrt pcmcia interface
509 static struct sa1100fb_mach_info stork_tft_info __initdata = {
510 .pixclock = 28935, .bpp = 16,
511 .xres = 640, .yres = 480,
513 .hsync_len = 64, .vsync_len = 2,
514 .left_margin = 48, .upper_margin = 12,
515 .right_margin = 48, .lower_margin = 31,
517 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
518 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsCntOff,
521 static struct sa1100fb_rgb stork_tft_rgb_16 = {
522 .red = { .offset = 11, .length = 5, },
523 .green = { .offset = 5, .length = 6, },
524 .blue = { .offset = 0, .length = 5, },
525 .transp = { .offset = 0, .length = 0, },
528 #else /* Kyocera DSTN */
530 static struct sa1100fb_mach_info stork_dstn_info __initdata = {
531 .pixclock = 0, .bpp = 16,
532 .xres = 640, .yres = 480,
534 .hsync_len = 2, .vsync_len = 2,
535 .left_margin = 2, .upper_margin = 0,
536 .right_margin = 2, .lower_margin = 0,
538 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT ,
540 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
543 0x18 /* ought to be 0x14 but DMA isn't up to that as yet */
546 static struct sa1100fb_rgb stork_dstn_rgb_16 = {
547 .red = { .offset = 8, .length = 4, },
548 .green = { .offset = 4, .length = 4, },
549 .blue = { .offset = 0, .length = 4, },
550 .transp = { .offset = 0, .length = 0, },
555 #ifdef CONFIG_SA1100_PT_SYSTEM3
557 * 648 x 480 x 8bpp x 75Hz Dual Panel Color STN Display
559 * pixclock = 1/( 640*3/8*240 ), [pixclock]=1e-12s=ps
560 * 3 due to r,g,b lines
561 * 8 due to 8 bit data bus
562 * 640 due to 640 pixels per line
563 * 240 = 480/2 due to dual panel display
564 * =>4.32Mhz => 231481E-12s
566 static struct sa1100fb_mach_info system3_info __initdata = {
567 .pixclock = 231481, .bpp = 8,
568 .xres = 640, .yres = 480,
570 .hsync_len = 2, .vsync_len = 2,
571 .left_margin = 2, .upper_margin = 0,
572 .right_margin = 2, .lower_margin = 0,
574 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
576 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
577 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
581 #ifdef CONFIG_SA1100_XP860
582 static struct sa1100fb_mach_info xp860_info __initdata = {
583 .pixclock = 0, .bpp = 8,
584 .xres = 1024, .yres = 768,
586 .hsync_len = 3, .vsync_len = 3,
587 .left_margin = 3, .upper_margin = 2,
588 .right_margin = 2, .lower_margin = 1,
590 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
591 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_PixClkDiv(6),
597 static struct sa1100fb_mach_info * __init
598 sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
600 struct sa1100fb_mach_info *inf = NULL;
604 * default {11,5}, { 5,6}, { 0,5}, { 0,0}
605 * h3600 {12,4}, { 7,4}, { 1,4}, { 0,0}
606 * freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
608 #ifdef CONFIG_SA1100_ASSABET
609 if (machine_is_assabet()) {
610 #ifndef ASSABET_PAL_VIDEO
611 inf = &lq039q2ds54_info;
617 #ifdef CONFIG_SA1100_H3100
618 if (machine_is_h3100()) {
622 #ifdef CONFIG_SA1100_H3600
623 if (machine_is_h3600()) {
625 fbi->rgb[RGB_16] = &h3600_rgb_16;
628 #ifdef CONFIG_SA1100_H3800
629 if (machine_is_h3800()) {
633 #ifdef CONFIG_SA1100_BRUTUS
634 if (machine_is_brutus()) {
638 #ifdef CONFIG_SA1100_FREEBIRD
639 if (machine_is_freebird()) {
640 inf = &freebird_info;
641 fbi->rgb[RGB_16] = &freebird_rgb16;
644 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
645 if (machine_is_graphicsclient()) {
646 inf = &graphicsclient_info;
649 #ifdef CONFIG_SA1100_HUW_WEBPANEL
650 if (machine_is_huw_webpanel()) {
651 inf = &huw_webpanel_info;
654 #ifdef CONFIG_SA1100_LART
655 if (machine_is_lart()) {
657 inf = &lart_grey_info;
659 #ifdef LART_COLOR_LCD
660 inf = &lart_color_info;
662 #ifdef LART_VIDEO_OUT
663 inf = &lart_video_info;
665 #ifdef LART_KIT01_LCD
666 inf = &lart_kit01_info;
670 #ifdef CONFIG_SA1100_OMNIMETER
671 if (machine_is_omnimeter()) {
672 inf = &omnimeter_info;
675 #ifdef CONFIG_SA1100_PANGOLIN
676 if (machine_is_pangolin()) {
677 inf = &pangolin_info;
680 #ifdef CONFIG_SA1100_PT_SYSTEM3
681 if (machine_is_pt_system3()) {
685 #ifdef CONFIG_SA1100_SHANNON
686 if (machine_is_shannon()) {
690 #ifdef CONFIG_SA1100_STORK
691 if (machine_is_stork()) {
693 inf = &stork_tft_info;
694 fbi->rgb[RGB_16] = &stork_tft_rgb_16;
696 inf = &stork_dstn_info;
697 fbi->rgb[RGB_16] = &stork_dstn_rgb_16;
701 #ifdef CONFIG_SA1100_XP860
702 if (machine_is_xp860()) {
709 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
710 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
712 static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
716 local_irq_save(flags);
718 * We need to handle two requests being made at the same time.
719 * There are two important cases:
720 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
721 * We must perform the unblanking, which will do our REENABLE for us.
722 * 2. When we are blanking, but immediately unblank before we have
723 * blanked. We do the "REENABLE" thing here as well, just to be sure.
725 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
727 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
730 if (state != (u_int)-1) {
731 fbi->task_state = state;
732 schedule_work(&fbi->task);
734 local_irq_restore(flags);
737 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
740 chan >>= 16 - bf->length;
741 return chan << bf->offset;
745 * Convert bits-per-pixel to a hardware palette PBS value.
747 static inline u_int palette_pbs(struct fb_var_screeninfo *var)
750 switch (var->bits_per_pixel) {
751 case 4: ret = 0 << 12; break;
752 case 8: ret = 1 << 12; break;
753 case 16: ret = 2 << 12; break;
759 sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
760 u_int trans, struct fb_info *info)
762 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
765 if (regno < fbi->palette_size) {
766 val = ((red >> 4) & 0xf00);
767 val |= ((green >> 8) & 0x0f0);
768 val |= ((blue >> 12) & 0x00f);
771 val |= palette_pbs(&fbi->fb.var);
773 fbi->palette_cpu[regno] = val;
780 sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
781 u_int trans, struct fb_info *info)
783 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
788 * If inverse mode was selected, invert all the colours
789 * rather than the register number. The register number
790 * is what you poke into the framebuffer to produce the
791 * colour you requested.
793 if (fbi->cmap_inverse) {
795 green = 0xffff - green;
796 blue = 0xffff - blue;
800 * If greyscale is true, then we convert the RGB value
801 * to greyscale no mater what visual we are using.
803 if (fbi->fb.var.grayscale)
804 red = green = blue = (19595 * red + 38470 * green +
807 switch (fbi->fb.fix.visual) {
808 case FB_VISUAL_TRUECOLOR:
810 * 12 or 16-bit True Colour. We encode the RGB value
811 * according to the RGB bitfield information.
814 u32 *pal = fbi->fb.pseudo_palette;
816 val = chan_to_field(red, &fbi->fb.var.red);
817 val |= chan_to_field(green, &fbi->fb.var.green);
818 val |= chan_to_field(blue, &fbi->fb.var.blue);
825 case FB_VISUAL_STATIC_PSEUDOCOLOR:
826 case FB_VISUAL_PSEUDOCOLOR:
827 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
835 * sa1100fb_display_dma_period()
836 * Calculate the minimum period (in picoseconds) between two DMA
837 * requests for the LCD controller. If we hit this, it means we're
838 * doing nothing but LCD DMA.
840 static unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
843 * Period = pixclock * bits_per_byte * bytes_per_transfer
844 * / memory_bits_per_pixel;
846 return var->pixclock * 8 * 16 / var->bits_per_pixel;
850 * sa1100fb_check_var():
851 * Round up in the following order: bits_per_pixel, xres,
852 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
853 * bitfields, horizontal timing, vertical timing.
856 sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
858 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
861 if (var->xres < MIN_XRES)
862 var->xres = MIN_XRES;
863 if (var->yres < MIN_YRES)
864 var->yres = MIN_YRES;
865 if (var->xres > fbi->max_xres)
866 var->xres = fbi->max_xres;
867 if (var->yres > fbi->max_yres)
868 var->yres = fbi->max_yres;
869 var->xres_virtual = max(var->xres_virtual, var->xres);
870 var->yres_virtual = max(var->yres_virtual, var->yres);
872 DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
873 switch (var->bits_per_pixel) {
888 * Copy the RGB parameters for this display
889 * from the machine specific parameters.
891 var->red = fbi->rgb[rgbidx]->red;
892 var->green = fbi->rgb[rgbidx]->green;
893 var->blue = fbi->rgb[rgbidx]->blue;
894 var->transp = fbi->rgb[rgbidx]->transp;
896 DPRINTK("RGBT length = %d:%d:%d:%d\n",
897 var->red.length, var->green.length, var->blue.length,
900 DPRINTK("RGBT offset = %d:%d:%d:%d\n",
901 var->red.offset, var->green.offset, var->blue.offset,
904 #ifdef CONFIG_CPU_FREQ
905 printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
906 sa1100fb_display_dma_period(var),
907 cpufreq_get(smp_processor_id()));
913 static inline void sa1100fb_set_truecolor(u_int is_true_color)
915 if (machine_is_assabet()) {
916 #if 1 // phase 4 or newer Assabet's
918 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
920 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
924 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
926 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
932 * sa1100fb_set_par():
933 * Set the user defined part of the display for the specified console
935 static int sa1100fb_set_par(struct fb_info *info)
937 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
938 struct fb_var_screeninfo *var = &info->var;
939 unsigned long palette_mem_size;
941 DPRINTK("set_par\n");
943 if (var->bits_per_pixel == 16)
944 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
945 else if (!fbi->cmap_static)
946 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
949 * Some people have weird ideas about wanting static
950 * pseudocolor maps. I suspect their user space
951 * applications are broken.
953 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
956 fbi->fb.fix.line_length = var->xres_virtual *
957 var->bits_per_pixel / 8;
958 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
960 palette_mem_size = fbi->palette_size * sizeof(u16);
962 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
964 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
965 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
968 * Set (any) board control register to handle new color depth
970 sa1100fb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
972 #ifdef CONFIG_SA1100_OMNIMETER
973 #error Do we have to do this here? We already do it at init time.
974 if (machine_is_omnimeter())
975 SetLCDContrast(DefaultLCDContrast);
978 sa1100fb_activate_var(var, fbi);
985 sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
986 struct fb_info *info)
988 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
991 * Make sure the user isn't doing something stupid.
993 if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->cmap_static))
996 return gen_set_cmap(cmap, kspc, con, info);
1001 * Formal definition of the VESA spec:
1003 * This refers to the state of the display when it is in full operation
1005 * This defines an optional operating state of minimal power reduction with
1006 * the shortest recovery time
1008 * This refers to a level of power management in which substantial power
1009 * reduction is achieved by the display. The display can have a longer
1010 * recovery time from this state than from the Stand-by state
1012 * This indicates that the display is consuming the lowest level of power
1013 * and is non-operational. Recovery from this state may optionally require
1014 * the user to manually power on the monitor
1016 * Now, the fbdev driver adds an additional state, (blank), where they
1017 * turn off the video (maybe by colormap tricks), but don't mess with the
1018 * video itself: think of it semantically between on and Stand-By.
1020 * So here's what we should do in our fbdev blank routine:
1022 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
1023 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
1024 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
1025 * VESA_POWERDOWN (mode 3) Video off, front/back light off
1027 * This will match the matrox implementation.
1031 * Blank the display by setting all palette values to zero. Note, the
1032 * 12 and 16 bpp modes don't really use the palette, so this will not
1033 * blank the display in all modes.
1035 static int sa1100fb_blank(int blank, struct fb_info *info)
1037 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
1040 DPRINTK("sa1100fb_blank: blank=%d\n", blank);
1043 case VESA_POWERDOWN:
1044 case VESA_VSYNC_SUSPEND:
1045 case VESA_HSYNC_SUSPEND:
1046 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
1047 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
1048 for (i = 0; i < fbi->palette_size; i++)
1049 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
1050 sa1100fb_schedule_work(fbi, C_DISABLE);
1053 case VESA_NO_BLANKING:
1054 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
1055 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
1056 fb_set_cmap(&fbi->fb.cmap, 1, info);
1057 sa1100fb_schedule_work(fbi, C_ENABLE);
1062 static struct fb_ops sa1100fb_ops = {
1063 .owner = THIS_MODULE,
1064 .fb_check_var = sa1100fb_check_var,
1065 .fb_set_par = sa1100fb_set_par,
1066 // .fb_set_cmap = sa1100fb_set_cmap,
1067 .fb_setcolreg = sa1100fb_setcolreg,
1068 .fb_fillrect = cfb_fillrect,
1069 .fb_copyarea = cfb_copyarea,
1070 .fb_imageblit = cfb_imageblit,
1071 .fb_blank = sa1100fb_blank,
1072 .fb_cursor = soft_cursor,
1076 * Calculate the PCD value from the clock rate (in picoseconds).
1077 * We take account of the PPCR clock setting.
1079 static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
1081 unsigned int pcd = cpuclock / 100;
1086 return pcd + 1; /* make up for integer math truncations */
1090 * sa1100fb_activate_var():
1091 * Configures LCD Controller based on entries in var parameter. Settings are
1092 * only written to the controller if changes were made.
1094 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
1096 struct sa1100fb_lcd_reg new_regs;
1097 u_int half_screen_size, yres, pcd;
1100 DPRINTK("Configuring SA1100 LCD\n");
1102 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
1103 var->xres, var->hsync_len,
1104 var->left_margin, var->right_margin);
1105 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
1106 var->yres, var->vsync_len,
1107 var->upper_margin, var->lower_margin);
1110 if (var->xres < 16 || var->xres > 1024)
1111 printk(KERN_ERR "%s: invalid xres %d\n",
1112 fbi->fb.fix.id, var->xres);
1113 if (var->hsync_len < 1 || var->hsync_len > 64)
1114 printk(KERN_ERR "%s: invalid hsync_len %d\n",
1115 fbi->fb.fix.id, var->hsync_len);
1116 if (var->left_margin < 1 || var->left_margin > 255)
1117 printk(KERN_ERR "%s: invalid left_margin %d\n",
1118 fbi->fb.fix.id, var->left_margin);
1119 if (var->right_margin < 1 || var->right_margin > 255)
1120 printk(KERN_ERR "%s: invalid right_margin %d\n",
1121 fbi->fb.fix.id, var->right_margin);
1122 if (var->yres < 1 || var->yres > 1024)
1123 printk(KERN_ERR "%s: invalid yres %d\n",
1124 fbi->fb.fix.id, var->yres);
1125 if (var->vsync_len < 1 || var->vsync_len > 64)
1126 printk(KERN_ERR "%s: invalid vsync_len %d\n",
1127 fbi->fb.fix.id, var->vsync_len);
1128 if (var->upper_margin < 0 || var->upper_margin > 255)
1129 printk(KERN_ERR "%s: invalid upper_margin %d\n",
1130 fbi->fb.fix.id, var->upper_margin);
1131 if (var->lower_margin < 0 || var->lower_margin > 255)
1132 printk(KERN_ERR "%s: invalid lower_margin %d\n",
1133 fbi->fb.fix.id, var->lower_margin);
1136 new_regs.lccr0 = fbi->lccr0 |
1137 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
1138 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
1141 LCCR1_DisWdth(var->xres) +
1142 LCCR1_HorSnchWdth(var->hsync_len) +
1143 LCCR1_BegLnDel(var->left_margin) +
1144 LCCR1_EndLnDel(var->right_margin);
1147 * If we have a dual scan LCD, then we need to halve
1148 * the YRES parameter.
1151 if (fbi->lccr0 & LCCR0_Dual)
1155 LCCR2_DisHght(yres) +
1156 LCCR2_VrtSnchWdth(var->vsync_len) +
1157 LCCR2_BegFrmDel(var->upper_margin) +
1158 LCCR2_EndFrmDel(var->lower_margin);
1160 pcd = get_pcd(var->pixclock, cpufreq_get(0));
1161 new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 |
1162 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
1163 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1165 DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0);
1166 DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1);
1167 DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2);
1168 DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3);
1170 half_screen_size = var->bits_per_pixel;
1171 half_screen_size = half_screen_size * var->xres * var->yres / 16;
1173 /* Update shadow copy atomically */
1174 local_irq_save(flags);
1175 fbi->dbar1 = fbi->palette_dma;
1176 fbi->dbar2 = fbi->screen_dma + half_screen_size;
1178 fbi->reg_lccr0 = new_regs.lccr0;
1179 fbi->reg_lccr1 = new_regs.lccr1;
1180 fbi->reg_lccr2 = new_regs.lccr2;
1181 fbi->reg_lccr3 = new_regs.lccr3;
1182 local_irq_restore(flags);
1185 * Only update the registers if the controller is enabled
1186 * and something has changed.
1188 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
1189 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
1190 (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
1191 sa1100fb_schedule_work(fbi, C_REENABLE);
1197 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1198 * Do not call them directly; set_ctrlr_state does the correct serialisation
1199 * to ensure that things happen in the right way 100% of time time.
1202 static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
1204 DPRINTK("backlight o%s\n", on ? "n" : "ff");
1206 if (sa1100fb_backlight_power)
1207 sa1100fb_backlight_power(on);
1210 static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
1212 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
1214 if (sa1100fb_lcd_power)
1215 sa1100fb_lcd_power(on);
1218 static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
1223 * Enable GPIO<9:2> for LCD use if:
1224 * 1. Active display, or
1225 * 2. Color Dual Passive display
1227 * see table 11.8 on page 11-27 in the SA1100 manual
1230 * SA1110 spec update nr. 25 says we can and should
1231 * clear LDD15 to 12 for 4 or 8bpp modes with active
1234 if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
1235 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
1236 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
1238 if (fbi->fb.var.bits_per_pixel > 8 ||
1239 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
1240 mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
1250 static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
1252 DPRINTK("Enabling LCD controller\n");
1255 * Make sure the mode bits are present in the first palette entry
1257 fbi->palette_cpu[0] &= 0xcfff;
1258 fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
1260 /* Sequence from 11.7.10 */
1261 LCCR3 = fbi->reg_lccr3;
1262 LCCR2 = fbi->reg_lccr2;
1263 LCCR1 = fbi->reg_lccr1;
1264 LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
1269 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
1270 #error Where is GPIO24 set as an output? Can we fit this in somewhere else?
1271 if (machine_is_graphicsclient()) {
1272 // From ADS doc again...same as disable
1273 set_current_state(TASK_UNINTERRUPTIBLE);
1274 schedule_timeout(20 * HZ / 1000);
1275 GPSR |= GPIO_GPIO24;
1279 if (machine_is_shannon()) {
1280 GPDR |= SHANNON_GPIO_DISP_EN;
1281 GPSR |= SHANNON_GPIO_DISP_EN;
1284 DPRINTK("DBAR1 = 0x%08x\n", DBAR1);
1285 DPRINTK("DBAR2 = 0x%08x\n", DBAR2);
1286 DPRINTK("LCCR0 = 0x%08x\n", LCCR0);
1287 DPRINTK("LCCR1 = 0x%08x\n", LCCR1);
1288 DPRINTK("LCCR2 = 0x%08x\n", LCCR2);
1289 DPRINTK("LCCR3 = 0x%08x\n", LCCR3);
1292 static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
1294 DECLARE_WAITQUEUE(wait, current);
1296 DPRINTK("Disabling LCD controller\n");
1298 #ifdef CONFIG_SA1100_GRAPHICSCLIENT
1299 #error Where is GPIO24 set as an output? Can we fit this in somewhere else?
1300 if (machine_is_graphicsclient()) {
1302 * From ADS internal document:
1303 * GPIO24 should be LOW at least 10msec prior to disabling
1304 * the LCD interface.
1306 * We'll wait 20msec.
1308 GPCR |= GPIO_GPIO24;
1309 set_current_state(TASK_UNINTERRUPTIBLE);
1310 schedule_timeout(20 * HZ / 1000);
1313 #ifdef CONFIG_SA1100_HUW_WEBPANEL
1314 #error Move me into __sa1100fb_lcd_power and/or __sa1100fb_backlight_power
1315 if (machine_is_huw_webpanel()) {
1316 // don't forget to set the control lines to zero (?)
1317 DPRINTK("ShutDown HuW LCD controller\n");
1318 BCR_clear(BCR_TFT_ENA + BCR_CCFL_POW + BCR_PWM_BACKLIGHT);
1322 if (machine_is_shannon()) {
1323 GPCR |= SHANNON_GPIO_DISP_EN;
1326 add_wait_queue(&fbi->ctrlr_wait, &wait);
1327 set_current_state(TASK_UNINTERRUPTIBLE);
1329 LCSR = 0xffffffff; /* Clear LCD Status Register */
1330 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
1331 LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */
1333 schedule_timeout(20 * HZ / 1000);
1334 remove_wait_queue(&fbi->ctrlr_wait, &wait);
1338 * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
1340 static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
1342 struct sa1100fb_info *fbi = dev_id;
1343 unsigned int lcsr = LCSR;
1345 if (lcsr & LCSR_LDD) {
1347 wake_up(&fbi->ctrlr_wait);
1355 * This function must be called from task context only, since it will
1356 * sleep when disabling the LCD controller, or if we get two contending
1357 * processes trying to alter state.
1359 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
1363 down(&fbi->ctrlr_sem);
1365 old_state = fbi->state;
1368 * Hack around fbcon initialisation.
1370 if (old_state == C_STARTUP && state == C_REENABLE)
1374 case C_DISABLE_CLKCHANGE:
1376 * Disable controller for clock change. If the
1377 * controller is already disabled, then do nothing.
1379 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1381 sa1100fb_disable_controller(fbi);
1388 * Disable controller
1390 if (old_state != C_DISABLE) {
1393 __sa1100fb_backlight_power(fbi, 0);
1394 if (old_state != C_DISABLE_CLKCHANGE)
1395 sa1100fb_disable_controller(fbi);
1396 __sa1100fb_lcd_power(fbi, 0);
1400 case C_ENABLE_CLKCHANGE:
1402 * Enable the controller after clock change. Only
1403 * do this if we were disabled for the clock change.
1405 if (old_state == C_DISABLE_CLKCHANGE) {
1406 fbi->state = C_ENABLE;
1407 sa1100fb_enable_controller(fbi);
1413 * Re-enable the controller only if it was already
1414 * enabled. This is so we reprogram the control
1417 if (old_state == C_ENABLE) {
1418 sa1100fb_disable_controller(fbi);
1419 sa1100fb_setup_gpio(fbi);
1420 sa1100fb_enable_controller(fbi);
1426 * Re-enable the controller after PM. This is not
1427 * perfect - think about the case where we were doing
1428 * a clock change, and we suspended half-way through.
1430 if (old_state != C_DISABLE_PM)
1436 * Power up the LCD screen, enable controller, and
1437 * turn on the backlight.
1439 if (old_state != C_ENABLE) {
1440 fbi->state = C_ENABLE;
1441 sa1100fb_setup_gpio(fbi);
1442 __sa1100fb_lcd_power(fbi, 1);
1443 sa1100fb_enable_controller(fbi);
1444 __sa1100fb_backlight_power(fbi, 1);
1448 up(&fbi->ctrlr_sem);
1452 * Our LCD controller task (which is called when we blank or unblank)
1455 static void sa1100fb_task(void *dummy)
1457 struct sa1100fb_info *fbi = dummy;
1458 u_int state = xchg(&fbi->task_state, -1);
1460 set_ctrlr_state(fbi, state);
1463 #ifdef CONFIG_CPU_FREQ
1465 * Calculate the minimum DMA period over all displays that we own.
1466 * This, together with the SDRAM bandwidth defines the slowest CPU
1467 * frequency that can be selected.
1469 static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
1472 unsigned int min_period = (unsigned int)-1;
1475 for (i = 0; i < MAX_NR_CONSOLES; i++) {
1476 struct display *disp = &fb_display[i];
1477 unsigned int period;
1480 * Do we own this display?
1482 if (disp->fb_info != &fbi->fb)
1486 * Ok, calculate its DMA period
1488 period = sa1100fb_display_dma_period(&disp->var);
1489 if (period < min_period)
1490 min_period = period;
1496 * FIXME: we need to verify _all_ consoles.
1498 return sa1100fb_display_dma_period(&fbi->fb.var);
1503 * CPU clock speed change handler. We need to adjust the LCD timing
1504 * parameters when the CPU clock is adjusted by the power management
1508 sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
1511 struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
1512 struct cpufreq_freqs *f = data;
1516 case CPUFREQ_PRECHANGE:
1517 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1520 case CPUFREQ_POSTCHANGE:
1521 pcd = get_pcd(fbi->fb.var.pixclock, f->new);
1522 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1523 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1530 sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
1533 struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
1534 struct cpufreq_policy *policy = data;
1537 case CPUFREQ_ADJUST:
1538 case CPUFREQ_INCOMPATIBLE:
1539 printk(KERN_DEBUG "min dma period: %d ps, "
1540 "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
1542 /* todo: fill in min/max values */
1544 case CPUFREQ_NOTIFY:
1546 /* todo: panic if min/max values aren't fulfilled
1547 * [can't really happen unless there's a bug in the
1548 * CPU policy verififcation process *
1558 * Power management hooks. Note that we won't be called from IRQ context,
1559 * unlike the blank functions above, so we may sleep.
1561 static int sa1100fb_suspend(struct device *dev, u32 state, u32 level)
1563 struct sa1100fb_info *fbi = dev_get_drvdata(dev);
1565 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
1566 set_ctrlr_state(fbi, C_DISABLE_PM);
1570 static int sa1100fb_resume(struct device *dev, u32 level)
1572 struct sa1100fb_info *fbi = dev_get_drvdata(dev);
1574 if (level == RESUME_ENABLE)
1575 set_ctrlr_state(fbi, C_ENABLE_PM);
1579 #define sa1100fb_suspend NULL
1580 #define sa1100fb_resume NULL
1584 * sa1100fb_map_video_memory():
1585 * Allocates the DRAM memory for the frame buffer. This buffer is
1586 * remapped into a non-cached, non-buffered, memory region to
1587 * allow palette and pixel writes to occur without flushing the
1588 * cache. Once this area is remapped, all virtual memory
1589 * access to the video memory should occur at the new region.
1591 static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
1594 * We reserve one page for the palette, plus the size
1595 * of the framebuffer.
1597 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1598 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1599 &fbi->map_dma, GFP_KERNEL);
1602 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1603 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1605 * FIXME: this is actually the wrong thing to place in
1606 * smem_start. But fbdev suffers from the problem that
1607 * it needs an API which doesn't exist (in this case,
1608 * dma_writecombine_mmap)
1610 fbi->fb.fix.smem_start = fbi->screen_dma;
1613 return fbi->map_cpu ? 0 : -ENOMEM;
1616 /* Fake monspecs to fill in fbinfo structure */
1617 static struct fb_monspecs monspecs __initdata = {
1625 static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev)
1627 struct sa1100fb_mach_info *inf;
1628 struct sa1100fb_info *fbi;
1630 fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
1635 memset(fbi, 0, sizeof(struct sa1100fb_info));
1638 strcpy(fbi->fb.fix.id, SA1100_NAME);
1640 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1641 fbi->fb.fix.type_aux = 0;
1642 fbi->fb.fix.xpanstep = 0;
1643 fbi->fb.fix.ypanstep = 0;
1644 fbi->fb.fix.ywrapstep = 0;
1645 fbi->fb.fix.accel = FB_ACCEL_NONE;
1647 fbi->fb.var.nonstd = 0;
1648 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1649 fbi->fb.var.height = -1;
1650 fbi->fb.var.width = -1;
1651 fbi->fb.var.accel_flags = 0;
1652 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1654 fbi->fb.fbops = &sa1100fb_ops;
1655 fbi->fb.flags = FBINFO_FLAG_DEFAULT;
1656 fbi->fb.monspecs = monspecs;
1657 fbi->fb.currcon = -1;
1658 fbi->fb.pseudo_palette = (fbi + 1);
1660 fbi->rgb[RGB_8] = &rgb_8;
1661 fbi->rgb[RGB_16] = &def_rgb_16;
1663 inf = sa1100fb_get_machine_info(fbi);
1666 * People just don't seem to get this. We don't support
1667 * anything but correct entries now, so panic if someone
1668 * does something stupid.
1670 if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
1672 panic("sa1100fb error: invalid LCCR3 fields set or zero "
1675 fbi->max_xres = inf->xres;
1676 fbi->fb.var.xres = inf->xres;
1677 fbi->fb.var.xres_virtual = inf->xres;
1678 fbi->max_yres = inf->yres;
1679 fbi->fb.var.yres = inf->yres;
1680 fbi->fb.var.yres_virtual = inf->yres;
1681 fbi->max_bpp = inf->bpp;
1682 fbi->fb.var.bits_per_pixel = inf->bpp;
1683 fbi->fb.var.pixclock = inf->pixclock;
1684 fbi->fb.var.hsync_len = inf->hsync_len;
1685 fbi->fb.var.left_margin = inf->left_margin;
1686 fbi->fb.var.right_margin = inf->right_margin;
1687 fbi->fb.var.vsync_len = inf->vsync_len;
1688 fbi->fb.var.upper_margin = inf->upper_margin;
1689 fbi->fb.var.lower_margin = inf->lower_margin;
1690 fbi->fb.var.sync = inf->sync;
1691 fbi->fb.var.grayscale = inf->cmap_greyscale;
1692 fbi->cmap_inverse = inf->cmap_inverse;
1693 fbi->cmap_static = inf->cmap_static;
1694 fbi->lccr0 = inf->lccr0;
1695 fbi->lccr3 = inf->lccr3;
1696 fbi->state = C_STARTUP;
1697 fbi->task_state = (u_char)-1;
1698 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1701 init_waitqueue_head(&fbi->ctrlr_wait);
1702 INIT_WORK(&fbi->task, sa1100fb_task, fbi);
1703 init_MUTEX(&fbi->ctrlr_sem);
1708 static int __init sa1100fb_probe(struct device *dev)
1710 struct sa1100fb_info *fbi;
1713 if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
1716 fbi = sa1100fb_init_fbinfo(dev);
1721 /* Initialize video memory */
1722 ret = sa1100fb_map_video_memory(fbi);
1726 ret = request_irq(IRQ_LCD, sa1100fb_handle_irq, SA_INTERRUPT,
1729 printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
1733 #ifdef ASSABET_PAL_VIDEO
1734 if (machine_is_assabet())
1735 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
1738 #ifdef CONFIG_SA1100_FREEBIRD
1739 #error Please move this into __sa1100fb_lcd_power
1740 if (machine_is_freebird()) {
1741 BCR_set(BCR_FREEBIRD_LCD_DISP);
1743 BCR_set(BCR_FREEBIRD_LCD_PWR);
1749 * This makes sure that our colour bitfield
1750 * descriptors are correctly initialised.
1752 sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
1754 dev_set_drvdata(dev, fbi);
1756 ret = register_framebuffer(&fbi->fb);
1760 #ifdef CONFIG_CPU_FREQ
1761 fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
1762 fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
1763 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1764 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1767 /* This driver cannot be unloaded at the moment */
1773 dev_set_drvdata(dev, NULL);
1776 release_mem_region(0xb0100000, 0x10000);
1780 static struct device_driver sa1100fb_driver = {
1781 .name = "sa11x0-fb",
1782 .bus = &platform_bus_type,
1783 .probe = sa1100fb_probe,
1784 .suspend = sa1100fb_suspend,
1785 .resume = sa1100fb_resume,
1788 int __init sa1100fb_init(void)
1790 return driver_register(&sa1100fb_driver);
1793 int __init sa1100fb_setup(char *options)
1798 if (!options || !*options)
1801 while ((this_opt = strsep(&options, ",")) != NULL) {
1803 if (!strncmp(this_opt, "bpp:", 4))
1804 current_par.max_bpp =
1805 simple_strtoul(this_opt + 4, NULL, 0);
1807 if (!strncmp(this_opt, "lccr0:", 6))
1809 simple_strtoul(this_opt + 6, NULL, 0);
1810 if (!strncmp(this_opt, "lccr1:", 6)) {
1812 simple_strtoul(this_opt + 6, NULL, 0);
1813 current_par.max_xres =
1814 (lcd_shadow.lccr1 & 0x3ff) + 16;
1816 if (!strncmp(this_opt, "lccr2:", 6)) {
1818 simple_strtoul(this_opt + 6, NULL, 0);
1819 current_par.max_yres =
1821 lccr0 & LCCR0_SDS) ? ((lcd_shadow.
1824 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
1826 if (!strncmp(this_opt, "lccr3:", 6))
1828 simple_strtoul(this_opt + 6, NULL, 0);
1834 MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
1835 MODULE_LICENSE("GPL");