2 * PCI Backend - Configuration space overlay for power management
4 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
8 #include "conf_space.h"
9 #include "conf_space_capability.h"
11 static int pm_caps_read(struct pci_dev *dev, int offset, u16 *value,
17 err = pci_read_config_word(dev, offset, &real_value);
21 *value = real_value & ~PCI_PM_CAP_PME_MASK;
27 /* PM_OK_BITS specifies the bits that the driver domain is allowed to change.
28 * Can't allow driver domain to enable PMEs - they're shared */
29 #define PM_OK_BITS (PCI_PM_CTRL_PME_STATUS|PCI_PM_CTRL_DATA_SEL_MASK)
31 static int pm_ctrl_write(struct pci_dev *dev, int offset, u16 new_value,
36 pci_power_t new_state;
38 /* Handle setting power state separately */
39 new_state = (pci_power_t)(new_value & PCI_PM_CTRL_STATE_MASK);
41 err = pci_read_config_word(dev, offset, &cur_value);
45 new_value &= PM_OK_BITS;
46 if ((cur_value & PM_OK_BITS) != new_value) {
47 new_value = (cur_value & ~PM_OK_BITS) | new_value;
48 err = pci_write_config_word(dev, offset, new_value);
53 /* Let pci core handle the power management change */
54 dev_dbg(&dev->dev, "set power state to %x\n", new_state);
55 err = pci_set_power_state(dev, new_state);
57 err = PCIBIOS_SET_FAILED;
63 /* Ensure PMEs are disabled */
64 static void *pm_ctrl_init(struct pci_dev *dev, int offset)
69 err = pci_read_config_word(dev, offset, &value);
73 if (value & PCI_PM_CTRL_PME_ENABLE) {
74 value &= ~PCI_PM_CTRL_PME_ENABLE;
75 err = pci_write_config_word(dev, offset, value);
82 static struct config_field caplist_pm[] = {
86 .u.w.read = pm_caps_read,
89 .offset = PCI_PM_CTRL,
92 .u.w.read = pciback_read_config_word,
93 .u.w.write = pm_ctrl_write,
96 .offset = PCI_PM_PPB_EXTENSIONS,
98 .u.b.read = pciback_read_config_byte,
101 .offset = PCI_PM_DATA_REGISTER,
103 .u.b.read = pciback_read_config_byte,
110 struct pciback_config_capability pciback_config_capability_pm = {
111 .capability = PCI_CAP_ID_PM,
112 .fields = caplist_pm,