2 * linux/include/asm-arm/arch-omap/hardware.h
4 * Hardware definitions for TI OMAP processors and boards
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
36 #define __ASM_ARCH_OMAP_HARDWARE_H
38 #include <asm/sizes.h>
39 #include <linux/config.h>
41 #include <asm/types.h>
43 #include <asm/mach-types.h>
46 * ----------------------------------------------------------------------------
48 * ----------------------------------------------------------------------------
50 #define IO_PHYS 0xFFFB0000
51 #define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
52 #define IO_VIRT (IO_PHYS - IO_OFFSET)
53 #define IO_SIZE 0x40000
54 #define IO_ADDRESS(x) ((x) - IO_OFFSET)
58 #define io_p2v(x) ((x) - IO_OFFSET)
59 #define io_v2p(x) ((x) + IO_OFFSET)
63 /* 16 bit uses LDRH/STRH, base +/- offset_8 */
64 typedef struct { volatile u16 offset[256]; } __regbase16;
65 #define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
66 ->offset[((vaddr)&0xff)>>1]
67 #define __REG16(paddr) __REGV16(io_p2v(paddr))
69 /* 8/32 bit uses LDR/STR, base +/- offset_12 */
70 typedef struct { volatile u8 offset[4096]; } __regbase8;
71 #define __REGV8(vaddr) ((__regbase8 *)((paddr)&~4095)) \
72 ->offset[((paddr)&4095)>>0]
73 #define __REG8(paddr) __REGV8(io_p2v(paddr))
75 typedef struct { volatile u32 offset[4096]; } __regbase32;
76 #define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
77 ->offset[((vaddr)&4095)>>2]
78 #define __REG32(paddr) __REGV32(io_p2v(paddr))
82 #define __REG8(paddr) io_p2v(paddr)
83 #define __REG16(paddr) io_p2v(paddr)
84 #define __REG32(paddr) io_p2v(paddr)
89 * ---------------------------------------------------------------------------
90 * Common definitions for all OMAP processors
91 * NOTE: Put all processor or board specific parts to the special header
93 * ---------------------------------------------------------------------------
97 * ----------------------------------------------------------------------------
99 * ----------------------------------------------------------------------------
101 #define CLKGEN_RESET_BASE (0xfffece00)
102 #define ARM_CKCTL (CLKGEN_RESET_BASE + 0x0)
103 #define ARM_IDLECT1 (CLKGEN_RESET_BASE + 0x4)
104 #define ARM_IDLECT2 (CLKGEN_RESET_BASE + 0x8)
105 #define ARM_EWUPCT (CLKGEN_RESET_BASE + 0xC)
106 #define ARM_RSTCT1 (CLKGEN_RESET_BASE + 0x10)
107 #define ARM_RSTCT2 (CLKGEN_RESET_BASE + 0x14)
108 #define ARM_SYSST (CLKGEN_RESET_BASE + 0x18)
114 #define SETARM_IDLE_SHIFT
116 /* DPLL control registers */
117 #define DPLL_CTL_REG (0xfffecf00)
118 #define CK_DPLL1 (0xfffecf00)
121 #define ULPD_REG_BASE (0xfffe0800)
122 #define ULPD_IT_STATUS_REG (ULPD_REG_BASE + 0x14)
123 #define ULPD_CLOCK_CTRL_REG (ULPD_REG_BASE + 0x30)
124 #define ULPD_SOFT_REQ_REG (ULPD_REG_BASE + 0x34)
125 #define ULPD_DPLL_CTRL_REG (ULPD_REG_BASE + 0x3c)
126 #define ULPD_STATUS_REQ_REG (ULPD_REG_BASE + 0x40)
127 #define ULPD_APLL_CTRL_REG (ULPD_REG_BASE + 0x4c)
128 #define ULPD_POWER_CTRL_REG (ULPD_REG_BASE + 0x50)
129 #define ULPD_CAM_CLK_CTRL_REG (ULPD_REG_BASE + 0x7c)
132 * ---------------------------------------------------------------------------
134 * ---------------------------------------------------------------------------
136 #define OMAP_32kHz_TIMER_BASE 0xfffb9000
138 /* 32k Timer Registers */
139 #define TIMER32k_CR 0x08
140 #define TIMER32k_TVR 0x00
141 #define TIMER32k_TCR 0x04
143 /* 32k Timer Control Register definition */
144 #define TIMER32k_TSS (1<<0)
145 #define TIMER32k_TRB (1<<1)
146 #define TIMER32k_INT (1<<2)
147 #define TIMER32k_ARL (1<<3)
149 /* MPU Timer base addresses */
150 #define OMAP_MPUTIMER_BASE 0xfffec500
151 #define OMAP_MPUTIMER_OFF 0x00000100
153 #define OMAP_TIMER1_BASE 0xfffec500
154 #define OMAP_TIMER2_BASE 0xfffec600
155 #define OMAP_TIMER3_BASE 0xfffec700
156 #define OMAP_WATCHDOG_BASE 0xfffec800
158 /* MPU Timer Registers */
163 /* CNTL_TIMER register bits */
164 #define MPUTIM_FREE (1<<6)
165 #define MPUTIM_CLOCK_ENABLE (1<<5)
166 #define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
167 #define MPUTIM_PTV_BIT 2
168 #define MPUTIM_AR (1<<1)
169 #define MPUTIM_ST (1<<0)
172 * ---------------------------------------------------------------------------
174 * ---------------------------------------------------------------------------
176 #define OMAP_IH1_BASE 0xfffecb00
177 #define OMAP_IH2_BASE 0xfffe0000
179 #define OMAP_MASK 0x4
183 #define IRQ_SIR_IRQ 0x10
184 #define IRQ_SIR_FIQ 0x14
185 #define IRQ_CONTROL_REG 0x18
187 #define IRQ_ILR0 0x1c
189 /* OMAP-1610 specific interrupt handler registers */
190 #define OMAP_IH2_SECT1 (OMAP_IH2_BASE)
191 #define OMAP_IH2_SECT2 (OMAP_IH2_BASE + 0x100)
192 #define OMAP_IH2_SECT3 (OMAP_IH2_BASE + 0x200)
193 #define OMAP_IH2_SECT4 (OMAP_IH2_BASE + 0x300)
196 * ---------------------------------------------------------------------------
197 * Traffic controller memory interface
198 * ---------------------------------------------------------------------------
200 #define TCMIF_BASE 0xfffecc00
201 #define IMIF_PRIO (TCMIF_BASE + 0x00)
202 #define EMIFS_PRIO_REG (TCMIF_BASE + 0x04)
203 #define EMIFF_PRIO_REG (TCMIF_BASE + 0x08)
204 #define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c)
205 #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
206 #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
207 #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
208 #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
209 #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
210 #define EMIFF_MRS (TCMIF_BASE + 0x24)
211 #define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
212 #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
213 #define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
214 #define TC_ENDIANISM (TCMIF_BASE + 0x34)
215 #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
216 #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
219 * ----------------------------------------------------------------------------
220 * System control registers
221 * ----------------------------------------------------------------------------
223 #define MOD_CONF_CTRL_0 0xfffe1080
224 #define MOD_CONF_CTRL_1 0xfffe1110
227 * ----------------------------------------------------------------------------
228 * Pin multiplexing registers
229 * ----------------------------------------------------------------------------
231 #define FUNC_MUX_CTRL_0 0xfffe1000
232 #define FUNC_MUX_CTRL_1 0xfffe1004
233 #define FUNC_MUX_CTRL_2 0xfffe1008
234 #define COMP_MODE_CTRL_0 0xfffe100c
235 #define FUNC_MUX_CTRL_3 0xfffe1010
236 #define FUNC_MUX_CTRL_4 0xfffe1014
237 #define FUNC_MUX_CTRL_5 0xfffe1018
238 #define FUNC_MUX_CTRL_6 0xfffe101C
239 #define FUNC_MUX_CTRL_7 0xfffe1020
240 #define FUNC_MUX_CTRL_8 0xfffe1024
241 #define FUNC_MUX_CTRL_9 0xfffe1028
242 #define FUNC_MUX_CTRL_A 0xfffe102C
243 #define FUNC_MUX_CTRL_B 0xfffe1030
244 #define FUNC_MUX_CTRL_C 0xfffe1034
245 #define FUNC_MUX_CTRL_D 0xfffe1038
246 #define PULL_DWN_CTRL_0 0xfffe1040
247 #define PULL_DWN_CTRL_1 0xfffe1044
248 #define PULL_DWN_CTRL_2 0xfffe1048
249 #define PULL_DWN_CTRL_3 0xfffe104c
251 /* OMAP-1610 specific multiplexing registers */
252 #define FUNC_MUX_CTRL_E 0xfffe1090
253 #define FUNC_MUX_CTRL_F 0xfffe1094
254 #define FUNC_MUX_CTRL_10 0xfffe1098
255 #define FUNC_MUX_CTRL_11 0xfffe109c
256 #define FUNC_MUX_CTRL_12 0xfffe10a0
257 #define PU_PD_SEL_0 0xfffe10b4
258 #define PU_PD_SEL_1 0xfffe10b8
259 #define PU_PD_SEL_2 0xfffe10bc
260 #define PU_PD_SEL_3 0xfffe10c0
261 #define PU_PD_SEL_4 0xfffe10c4
264 * ---------------------------------------------------------------------------
266 * ---------------------------------------------------------------------------
268 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
269 #define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8)
270 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
271 #define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8)
274 * ----------------------------------------------------------------------------
275 * DSP control registers
276 * ----------------------------------------------------------------------------
278 /* MPUI Interface Registers */
279 #define MPUI_CTRL_REG (0xfffec900)
280 #define MPUI_DEBUG_ADDR (0xfffec904)
281 #define MPUI_DEBUG_DATA (0xfffec908)
282 #define MPUI_DEBUG_FLAG (0xfffec90c)
283 #define MPUI_STATUS_REG (0xfffec910)
284 #define MPUI_DSP_STATUS_REG (0xfffec914)
285 #define MPUI_DSP_BOOT_CONFIG (0xfffec918)
286 #define MPUI_DSP_API_CONFIG (0xfffec91c)
289 #ifndef __ASSEMBLER__
292 * ---------------------------------------------------------------------------
293 * Processor differentiation
294 * ---------------------------------------------------------------------------
296 #define OMAP_ID_REG __REG32(0xfffed404)
298 #ifdef CONFIG_ARCH_OMAP730
300 #define cpu_is_omap730() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB55F)
302 #define cpu_is_omap730() 0
305 #ifdef CONFIG_ARCH_OMAP1510
306 #include "omap1510.h"
307 #define cpu_is_omap1510() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB470)
309 #define cpu_is_omap1510() 0
312 #ifdef CONFIG_ARCH_OMAP1610
313 #include "omap1610.h"
314 #define cpu_is_omap1710() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB5F7)
315 /* Detect 1710 as 1610 for now */
316 #define cpu_is_omap1610() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB576 || \
319 #define cpu_is_omap1610() 0
320 #define cpu_is_omap1710() 0
323 #ifdef CONFIG_ARCH_OMAP5912
324 #include "omap5912.h"
325 #define cpu_is_omap5912() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB58C)
327 #define cpu_is_omap5912() 0
331 * ---------------------------------------------------------------------------
332 * Board differentiation
333 * ---------------------------------------------------------------------------
336 #ifdef CONFIG_MACH_OMAP_INNOVATOR
337 #include "board-innovator.h"
340 #ifdef CONFIG_MACH_OMAP_H2
341 #include "board-h2.h"
344 #ifdef CONFIG_MACH_OMAP_PERSEUS2
345 #include "board-perseus2.h"
348 #ifdef CONFIG_MACH_OMAP_H3
349 #include "board-h3.h"
350 #error "Support for H3 board not yet implemented."
353 #ifdef CONFIG_MACH_OMAP_H4
354 #include "board-h4.h"
355 #error "Support for H4 board not yet implemented."
358 #ifdef CONFIG_MACH_OMAP_OSK
359 #include "board-osk.h"
362 #endif /* !__ASSEMBLER__ */
364 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */