2 * linux/include/asm-arm/arch-pxa/idp.h
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
10 * 2001-09-13: Cliff Brake <cbrake@accelent.com>
15 #include <linux/config.h>
18 * Note: this file must be safe to include in assembly files
21 /* comment out following if you have a rev01 board */
22 #define PXA_IDP_REV02 1
25 //Use this as well for 0017-x004 and greater pcb's:
26 #define PXA_IDP_REV04 1
28 #define IDP_FLASH_PHYS (PXA_CS0_PHYS)
29 #define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
30 #define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
31 #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
32 #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
33 #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
34 #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
41 #define IDP_IDE_BASE (0xf0000000)
42 #define IDP_IDE_SIZE (1*1024*1024)
43 #define IDE_REG_STRIDE 4
45 #define IDP_ETH_BASE (IDP_IDE_BASE + IDP_IDE_SIZE)
46 #define IDP_ETH_SIZE (1*1024*1024)
47 #define ETH_BASE IDP_ETH_BASE //smc9194 driver compatibility issue
49 #define IDP_COREVOLT_BASE (IDP_ETH_BASE + IDP_ETH_SIZE)
50 #define IDP_COREVOLT_SIZE (1*1024*1024)
52 #define IDP_CPLD_BASE (IDP_COREVOLT_BASE + IDP_COREVOLT_SIZE)
53 #define IDP_CPLD_SIZE (1*1024*1024)
55 #if (IDP_CPLD_BASE + IDP_CPLD_SIZE) > 0xfc000000
56 #error Your custom IO space is getting a bit large !!
59 #define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_BASE)
60 #define CPLD_V2P(x) ((x) - IDP_CPLD_BASE + IDP_CPLD_PHYS)
63 # define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
65 # define __CPLD_REG(x) CPLD_P2V(x)
68 /* board level registers in the CPLD: (offsets from CPLD_BASE) */
70 #define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
71 #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
72 #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
73 #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
74 #define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
75 #define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
76 #define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
77 #define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
78 #define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
79 #define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
80 #define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
81 #define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
82 #define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
83 #define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
85 #define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
86 #define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
87 #define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
88 #define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
90 /* FPGA register virtual addresses */
92 #define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
93 #define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
94 #define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
95 #define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
96 #define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
97 #define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
98 #define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
99 #define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
100 #define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
101 #define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
102 #define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
103 #define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
104 #define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
105 #define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
107 #define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
108 #define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
109 #define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
110 #define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
114 * Bit masks for various registers
117 // IDP_CPLD_PCCARD_PWR
118 #define PCC0_PWR0 (1 << 0)
119 #define PCC0_PWR1 (1 << 1)
120 #define PCC0_PWR2 (1 << 2)
121 #define PCC0_PWR3 (1 << 3)
122 #define PCC1_PWR0 (1 << 4)
123 #define PCC1_PWR1 (1 << 5)
124 #define PCC1_PWR2 (1 << 6)
125 #define PCC1_PWR3 (1 << 7)
127 // IDP_CPLD_PCCARD_EN
128 #define PCC0_RESET (1 << 6)
129 #define PCC1_RESET (1 << 7)
130 #define PCC0_ENABLE (1 << 0)
131 #define PCC1_ENABLE (1 << 1)
133 // IDP_CPLD_PCCARDx_STATUS
134 #define _PCC_WRPROT (1 << 7) // 7-4 read as low true
135 #define _PCC_RESET (1 << 6)
136 #define _PCC_IRQ (1 << 5)
137 #define _PCC_INPACK (1 << 4)
138 #define PCC_BVD2 (1 << 3)
139 #define PCC_BVD1 (1 << 2)
140 #define PCC_VS2 (1 << 1)
141 #define PCC_VS1 (1 << 0)
143 #define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
146 * Macros for LCD Driver
151 #define FB_BACKLIGHT_ON() (IDP_CPLD_LCD |= (1<<1))
152 #define FB_BACKLIGHT_OFF() (IDP_CPLD_LCD &= ~(1<<1))
154 #define FB_PWR_ON() (IDP_CPLD_LCD |= (1<< 0))
155 #define FB_PWR_OFF() (IDP_CPLD_LCD &= ~(1<<0))
157 #define FB_VLCD_ON() (IDP_CPLD_LCD |= (1<<2))
158 #define FB_VLCD_OFF() (IDP_CPLD_LCD &= ~(1<<2))
162 /* A listing of interrupts used by external hardware devices */
165 #define TOUCH_PANEL_IRQ IRQ_GPIO(5)
166 #define IDE_IRQ IRQ_GPIO(21)
168 #define TOUCH_PANEL_IRQ IRQ_GPIO(21)
169 #define IDE_IRQ IRQ_GPIO(5)
172 #define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING
174 #define ETHERNET_IRQ IRQ_GPIO(4)
175 #define ETHERNET_IRQ_EDGE IRQT_RISING
177 #define IDE_IRQ_EDGE IRQT_RISING
179 #define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
180 #define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE
182 #define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
183 #define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE
185 #define PCMCIA_S0_RDYINT IRQ_GPIO(19)
186 #define PCMCIA_S1_RDYINT IRQ_GPIO(22)
190 * Macros for LED Driver
194 #define IDP_HB_LED (1<<5)
195 #define IDP_BUSY_LED (1<<6)
197 #define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
199 #define IDP_WRITE_LEDS(value) (IDP_CPLD_LED_CONTROL = (IDP_CPLD_LED_CONTROL & (~(IDP_LEDS_MASK)) | value))
202 * macros for MTD driver
205 #define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
206 #define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
209 * macros for matrix keyboard driver
212 #define KEYBD_MATRIX_NUMBER_INPUTS 7
213 #define KEYBD_MATRIX_NUMBER_OUTPUTS 14
215 #define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
216 #define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
218 #define KEYBD_MATRIX_SETTLING_TIME_US 100
219 #define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
221 #define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
223 IDP_CPLD_KB_COL_LOW = outputs;\
224 IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
227 #define KEYBD_MATRIX_GET_INPUTS(inputs) \
229 inputs = (IDP_CPLD_KB_ROW & 0x7f);\
235 * following is for rev01 boards only
238 #define IDP_FLASH_PHYS (PXA_CS0_PHYS)
239 #define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
240 #define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
241 #define IDP_CTRL_PORT_PHYS (PXA_CS5_PHYS + 0x02C00000)
242 #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
243 #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
244 #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
245 #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
252 #define IDP_CTRL_PORT_BASE (0xf0000000)
253 #define IDP_CTRL_PORT_SIZE (1*1024*1024)
255 #define IDP_IDE_BASE (IDP_CTRL_PORT_BASE + IDP_CTRL_PORT_SIZE)
256 #define IDP_IDE_SIZE (1*1024*1024)
258 #define IDP_ETH_BASE (IDP_IDE_BASE + IDP_IDE_SIZE)
259 #define IDP_ETH_SIZE (1*1024*1024)
261 #define IDP_COREVOLT_BASE (IDP_ETH_BASE + IDP_ETH_SIZE)
262 #define IDP_COREVOLT_SIZE (1*1024*1024)
264 #define IDP_CPLD_BASE (IDP_COREVOLT_BASE + IDP_COREVOLT_SIZE)
265 #define IDP_CPLD_SIZE (1*1024*1024)
267 #if (IDP_CPLD_BASE + IDP_CPLD_SIZE) > 0xfc000000
268 #error Your custom IO space is getting a bit large !!
271 #define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_BASE)
272 #define CPLD_V2P(x) ((x) - IDP_CPLD_BASE + IDP_CPLD_PHYS)
275 # define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
277 # define __CPLD_REG(x) CPLD_P2V(x)
280 /* board level registers in the CPLD: (offsets from CPLD_BASE) */
282 #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x00)
283 #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
284 #define _IDP_CPLD_CIR (IDP_CPLD_PHYS + 0x08)
285 #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
286 #define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
287 #define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
288 #define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
289 #define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
290 #define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
291 #define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
292 #define _IDP_CPLD_MISC (IDP_CPLD_PHYS + 0x28)
293 #define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x2C)
294 #define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x30)
296 /* FPGA register virtual addresses */
297 #define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) /* write only */
298 #define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) /* write only */
299 #define IDP_CPLD_CIR __CPLD_REG(_IDP_CPLD_CIR) /* write only */
300 #define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) /* write only */
301 #define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) /* write only */
302 #define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) /* write only */
303 #define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) /* write only */
304 #define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) /* write only */
305 #define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) /* write only */
306 #define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) /* write only */
307 #define IDP_CPLD_MISC __CPLD_REG(_IDP_CPLD_MISC) /* read only */
308 #define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) /* read only */
309 #define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) /* read only */
314 /* shadow registers for write only registers */
315 extern unsigned int idp_cpld_led_control_shadow;
316 extern unsigned int idp_cpld_periph_pwr_shadow;
317 extern unsigned int idp_cpld_cir_shadow;
318 extern unsigned int idp_cpld_kb_col_high_shadow;
319 extern unsigned int idp_cpld_kb_col_low_shadow;
320 extern unsigned int idp_cpld_pccard_en_shadow;
321 extern unsigned int idp_cpld_gpioh_dir_shadow;
322 extern unsigned int idp_cpld_gpioh_value_shadow;
323 extern unsigned int idp_cpld_gpiol_dir_shadow;
324 extern unsigned int idp_cpld_gpiol_value_shadow;
326 extern unsigned int idp_control_port_shadow;
329 * macros to write to write only register
331 * none of these macros are protected from
332 * multiple drivers using them in interrupt context.
335 #define WRITE_IDP_CPLD_LED_CONTROL(value, mask) \
337 idp_cpld_led_control_shadow = (((value & mask) | (idp_cpld_led_control_shadow & ~mask)));\
338 IDP_CPLD_LED_CONTROL = idp_cpld_led_control_shadow;\
340 #define WRITE_IDP_CPLD_PERIPH_PWR(value, mask) \
342 idp_cpld_periph_pwr_shadow = ((value & mask) | (idp_cpld_periph_pwr_shadow & ~mask));\
343 IDP_CPLD_PERIPH_PWR = idp_cpld_periph_pwr_shadow;\
345 #define WRITE_IDP_CPLD_CIR(value, mask) \
347 idp_cpld_cir_shadow = ((value & mask) | (idp_cpld_cir_shadow & ~mask));\
348 IDP_CPLD_CIR = idp_cpld_cir_shadow;\
350 #define WRITE_IDP_CPLD_KB_COL_HIGH(value, mask) \
352 idp_cpld_kb_col_high_shadow = ((value & mask) | (idp_cpld_kb_col_high_shadow & ~mask));\
353 IDP_CPLD_KB_COL_HIGH = idp_cpld_kb_col_high_shadow;\
355 #define WRITE_IDP_CPLD_KB_COL_LOW(value, mask) \
357 idp_cpld_kb_col_low_shadow = ((value & mask) | (idp_cpld_kb_col_low_shadow & ~mask));\
358 IDP_CPLD_KB_COL_LOW = idp_cpld_kb_col_low_shadow;\
360 #define WRITE_IDP_CPLD_PCCARD_EN(value, mask) \
362 idp_cpld_ = ((value & mask) | (idp_cpld_led_control_shadow & ~mask));\
363 IDP_CPLD_LED_CONTROL = idp_cpld_led_control_shadow;\
365 #define WRITE_IDP_CPLD_GPIOH_DIR(value, mask) \
367 idp_cpld_gpioh_dir_shadow = ((value & mask) | (idp_cpld_gpioh_dir_shadow & ~mask));\
368 IDP_CPLD_GPIOH_DIR = idp_cpld_gpioh_dir_shadow;\
370 #define WRITE_IDP_CPLD_GPIOH_VALUE(value, mask) \
372 idp_cpld_gpioh_value_shadow = ((value & mask) | (idp_cpld_gpioh_value_shadow & ~mask));\
373 IDP_CPLD_GPIOH_VALUE = idp_cpld_gpioh_value_shadow;\
375 #define WRITE_IDP_CPLD_GPIOL_DIR(value, mask) \
377 idp_cpld_gpiol_dir_shadow = ((value & mask) | (idp_cpld_gpiol_dir_shadow & ~mask));\
378 IDP_CPLD_GPIOL_DIR = idp_cpld_gpiol_dir_shadow;\
380 #define WRITE_IDP_CPLD_GPIOL_VALUE(value, mask) \
382 idp_cpld_gpiol_value_shadow = ((value & mask) | (idp_cpld_gpiol_value_shadow & ~mask));\
383 IDP_CPLD_GPIOL_VALUE = idp_cpld_gpiol_value_shadow;\
386 #define WRITE_IDP_CONTROL_PORT(value, mask) \
388 idp_control_port_shadow = ((value & mask) | (idp_control_port_shadow & ~mask));\
389 (*((volatile unsigned long *)IDP_CTRL_PORT_BASE)) = idp_control_port_shadow;\
394 /* A listing of interrupts used by external hardware devices */
396 #define TOUCH_PANEL_IRQ IRQ_GPIO(21)
397 #define TOUCH_PANEL_IRQ_EGDE IRQT_FALLING
399 #define ETHERNET_IRQ IRQ_GPIO(4)
400 #define ETHERNET_IRQ_EDGE IRQT_RISING
403 * Bit masks for various registers
408 #define IDP_CONTROL_PORT_PCSLOT0_0 (1 << 0)
409 #define IDP_CONTROL_PORT_PCSLOT0_1 (1 << 1)
410 #define IDP_CONTROL_PORT_PCSLOT0_2 (1 << 2)
411 #define IDP_CONTROL_PORT_PCSLOT0_3 (1 << 3)
412 #define IDP_CONTROL_PORT_PCSLOT1_1 (1 << 4)
413 #define IDP_CONTROL_PORT_PCSLOT1_2 (1 << 5)
414 #define IDP_CONTROL_PORT_PCSLOT1_3 (1 << 6)
415 #define IDP_CONTROL_PORT_PCSLOT1_4 (1 << 7)
416 #define IDP_CONTROL_PORT_SERIAL1_EN (1 << 9)
417 #define IDP_CONTROL_PORT_SERIAL2_EN (1 << 10)
418 #define IDP_CONTROL_PORT_SERIAL3_EN (1 << 11)
419 #define IDP_CONTROL_PORT_IRDA_FIR (1 << 12)
420 #define IDP_CONTROL_PORT_IRDA_M0 (1 << 13)
421 #define IDP_CONTROL_PORT_IRDA_M1 (1 << 14)
422 #define IDP_CONTROL_PORT_I2S_PWR (1 << 15)
423 #define IDP_CONTROL_PORT_FLASH_WP (1 << 19)
424 #define IDP_CONTROL_PORT_MILL_EN (1 << 20)
425 #define IDP_CONTROL_PORT_LCD_PWR (1 << 21)
426 #define IDP_CONTROL_PORT_LCD_BKLEN (1 << 22)
427 #define IDP_CONTROL_PORT_LCD_ENAVLCD (1 << 23)
430 * Macros for LCD Driver
435 #define FB_BACKLIGHT_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_BKLEN, IDP_CONTROL_PORT_LCD_BKLEN)
436 #define FB_BACKLIGHT_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_BKLEN)
438 #define FB_PWR_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_PWR, IDP_CONTROL_PORT_LCD_PWR)
439 #define FB_PWR_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_PWR)
441 #define FB_VLCD_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_ENAVLCD, IDP_CONTROL_PORT_LCD_ENAVLCD)
442 #define FB_VLCD_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_ENAVLCD)
448 * Macros for LED Driver
452 #define IDP_HB_LED 0x1
453 #define IDP_BUSY_LED 0x2
455 #define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
457 #define IDP_WRITE_LEDS(value) WRITE_IDP_CPLD_LED_CONTROL(value, IDP_LEDS_MASK)
460 * macros for MTD driver
463 #define FLASH_WRITE_PROTECT_DISABLE() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_FLASH_WP)
464 #define FLASH_WRITE_PROTECT_ENABLE() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_FLASH_WP, IDP_CONTROL_PORT_FLASH_WP)