1 /* linux/include/asm/hardware/s3c2410/
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * S3C2410 GPIO register definitions
13 * 19-06-2003 BJD Created file
14 * 23-06-2003 BJD Updated GSTATUS registers
15 * 12-03-2004 BJD Updated include protection
19 #ifndef __ASM_ARCH_REGS_GPIO_H
20 #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
22 /* configure GPIO ports A..G */
24 #define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO)
26 /* port A - 22bits, zero in bit X makes pin X output
27 * 1 makes port special function, this is default
29 #define S3C2410_GPACON S3C2410_GPIOREG(0x00)
30 #define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
32 /* 0x08 and 0x0c are reserved */
34 /* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
35 * 00 = input, 01 = output, 10=special function, 11=reserved
36 * bit 0,1 = pin 0, 2,3= pin 1...
38 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
41 #define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
42 #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
43 #define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
45 /* no i/o pin in port b can have value 3! */
47 #define S3C2410_GPB0_INP (0x00 << 0)
48 #define S3C2410_GPB0_OUTP (0x01 << 0)
49 #define S3C2410_GPB0_TOUT0 (0x02 << 0)
51 #define S3C2410_GPB1_INP (0x00 << 2)
52 #define S3C2410_GPB1_OUTP (0x01 << 2)
53 #define S3C2410_GPB1_TOUT1 (0x02 << 2)
55 #define S3C2410_GPB2_INP (0x00 << 4)
56 #define S3C2410_GPB2_OUTP (0x01 << 4)
57 #define S3C2410_GPB2_TOUT2 (0x02 << 4)
59 #define S3C2410_GPB3_INP (0x00 << 6)
60 #define S3C2410_GPB3_OUTP (0x01 << 6)
61 #define S3C2410_GPB3_TOUT3 (0x02 << 6)
63 #define S3C2410_GPB4_INP (0x00 << 8)
64 #define S3C2410_GPB4_OUTP (0x01 << 8)
65 #define S3C2410_GPB4_TCLK0 (0x02 << 8)
66 #define S3C2410_GPB4_MASK (0x03 << 8)
68 #define S3C2410_GPB5_INP (0x00 << 10)
69 #define S3C2410_GPB5_OUTP (0x01 << 10)
70 #define S3C2410_GPB5_nXBACK (0x02 << 10)
72 #define S3C2410_GPB6_INP (0x00 << 12)
73 #define S3C2410_GPB6_OUTP (0x01 << 12)
74 #define S3C2410_GPB6_nXBREQ (0x02 << 12)
76 #define S3C2410_GPB7_INP (0x00 << 14)
77 #define S3C2410_GPB7_OUTP (0x01 << 14)
78 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
80 #define S3C2410_GPB8_INP (0x00 << 16)
81 #define S3C2410_GPB8_OUTP (0x01 << 16)
82 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
84 #define S3C2410_GPB9_INP (0x00 << 18)
85 #define S3C2410_GPB9_OUTP (0x01 << 18)
86 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
88 #define S3C2410_GPB10_INP (0x00 << 18)
89 #define S3C2410_GPB10_OUTP (0x01 << 18)
90 #define S3C2410_GPB10_nXDRE0 (0x02 << 18)
92 /* Port C consits of 16 GPIO/Special function
94 * almost identical setup to port b, but the special functions are mostly
95 * to do with the video system's sync/etc.
98 #define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
99 #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
100 #define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
102 #define S3C2410_GPC0_INP (0x00 << 0)
103 #define S3C2410_GPC0_OUTP (0x01 << 0)
104 #define S3C2410_GPC0_LEND (0x02 << 0)
106 #define S3C2410_GPC1_INP (0x00 << 2)
107 #define S3C2410_GPC1_OUTP (0x01 << 2)
108 #define S3C2410_GPC1_VCLK (0x02 << 2)
110 #define S3C2410_GPC2_INP (0x00 << 4)
111 #define S3C2410_GPC2_OUTP (0x01 << 4)
112 #define S3C2410_GPC2_VLINE (0x02 << 4)
114 #define S3C2410_GPC3_INP (0x00 << 6)
115 #define S3C2410_GPC3_OUTP (0x01 << 6)
116 #define S3C2410_GPC3_VFRAME (0x02 << 6)
118 #define S3C2410_GPC4_INP (0x00 << 8)
119 #define S3C2410_GPC4_OUTP (0x01 << 8)
120 #define S3C2410_GPC4_VM (0x02 << 8)
122 #define S3C2410_GPC5_INP (0x00 << 10)
123 #define S3C2410_GPC5_OUTP (0x01 << 10)
124 #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
126 #define S3C2410_GPC6_INP (0x00 << 12)
127 #define S3C2410_GPC6_OUTP (0x01 << 12)
128 #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
130 #define S3C2410_GPC7_INP (0x00 << 14)
131 #define S3C2410_GPC7_OUTP (0x01 << 14)
132 #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
134 #define S3C2410_GPC8_INP (0x00 << 16)
135 #define S3C2410_GPC8_OUTP (0x01 << 16)
136 #define S3C2410_GPC8_VD0 (0x02 << 16)
138 #define S3C2410_GPC9_INP (0x00 << 18)
139 #define S3C2410_GPC9_OUTP (0x01 << 18)
140 #define S3C2410_GPC9_VD1 (0x02 << 18)
142 #define S3C2410_GPC10_INP (0x00 << 20)
143 #define S3C2410_GPC10_OUTP (0x01 << 20)
144 #define S3C2410_GPC10_VD2 (0x02 << 20)
146 #define S3C2410_GPC11_INP (0x00 << 22)
147 #define S3C2410_GPC11_OUTP (0x01 << 22)
148 #define S3C2410_GPC11_VD3 (0x02 << 22)
150 #define S3C2410_GPC12_INP (0x00 << 24)
151 #define S3C2410_GPC12_OUTP (0x01 << 24)
152 #define S3C2410_GPC12_VD4 (0x02 << 24)
154 #define S3C2410_GPC13_INP (0x00 << 26)
155 #define S3C2410_GPC13_OUTP (0x01 << 26)
156 #define S3C2410_GPC13_VD5 (0x02 << 26)
158 #define S3C2410_GPC14_INP (0x00 << 28)
159 #define S3C2410_GPC14_OUTP (0x01 << 28)
160 #define S3C2410_GPC14_VD6 (0x02 << 28)
162 #define S3C2410_GPC15_INP (0x00 << 30)
163 #define S3C2410_GPC15_OUTP (0x01 << 30)
164 #define S3C2410_GPC15_VD7 (0x02 << 30)
166 /* Port D consists of 16 GPIO/Special function
168 * almost identical setup to port b, but the special functions are mostly
169 * to do with the video system's data.
172 #define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
173 #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
174 #define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
176 #define S3C2410_GPD0_INP (0x00 << 0)
177 #define S3C2410_GPD0_OUTP (0x01 << 0)
178 #define S3C2410_GPD0_VD8 (0x02 << 0)
180 #define S3C2410_GPD1_INP (0x00 << 2)
181 #define S3C2410_GPD1_OUTP (0x01 << 2)
182 #define S3C2410_GPD1_VD9 (0x02 << 2)
184 #define S3C2410_GPD2_INP (0x00 << 4)
185 #define S3C2410_GPD2_OUTP (0x01 << 4)
186 #define S3C2410_GPD2_VD10 (0x02 << 4)
188 #define S3C2410_GPD3_INP (0x00 << 6)
189 #define S3C2410_GPD3_OUTP (0x01 << 6)
190 #define S3C2410_GPD3_VD11 (0x02 << 6)
192 #define S3C2410_GPD4_INP (0x00 << 8)
193 #define S3C2410_GPD4_OUTP (0x01 << 8)
194 #define S3C2410_GPD4_VD12 (0x02 << 8)
196 #define S3C2410_GPD5_INP (0x00 << 10)
197 #define S3C2410_GPD5_OUTP (0x01 << 10)
198 #define S3C2410_GPD5_VD13 (0x02 << 10)
200 #define S3C2410_GPD6_INP (0x00 << 12)
201 #define S3C2410_GPD6_OUTP (0x01 << 12)
202 #define S3C2410_GPD6_VD14 (0x02 << 12)
204 #define S3C2410_GPD7_INP (0x00 << 14)
205 #define S3C2410_GPD7_OUTP (0x01 << 14)
206 #define S3C2410_GPD7_VD15 (0x02 << 14)
208 #define S3C2410_GPD8_INP (0x00 << 16)
209 #define S3C2410_GPD8_OUTP (0x01 << 16)
210 #define S3C2410_GPD8_VD16 (0x02 << 16)
212 #define S3C2410_GPD9_INP (0x00 << 18)
213 #define S3C2410_GPD9_OUTP (0x01 << 18)
214 #define S3C2410_GPD9_VD17 (0x02 << 18)
216 #define S3C2410_GPD10_INP (0x00 << 20)
217 #define S3C2410_GPD10_OUTP (0x01 << 20)
218 #define S3C2410_GPD10_VD18 (0x02 << 20)
220 #define S3C2410_GPD11_INP (0x00 << 22)
221 #define S3C2410_GPD11_OUTP (0x01 << 22)
222 #define S3C2410_GPD11_VD19 (0x02 << 22)
224 #define S3C2410_GPD12_INP (0x00 << 24)
225 #define S3C2410_GPD12_OUTP (0x01 << 24)
226 #define S3C2410_GPD12_VD20 (0x02 << 24)
228 #define S3C2410_GPD13_INP (0x00 << 26)
229 #define S3C2410_GPD13_OUTP (0x01 << 26)
230 #define S3C2410_GPD13_VD21 (0x02 << 26)
232 #define S3C2410_GPD14_INP (0x00 << 28)
233 #define S3C2410_GPD14_OUTP (0x01 << 28)
234 #define S3C2410_GPD14_VD22 (0x02 << 28)
236 #define S3C2410_GPD15_INP (0x00 << 30)
237 #define S3C2410_GPD15_OUTP (0x01 << 30)
238 #define S3C2410_GPD15_VD23 (0x02 << 30)
240 /* Port E consists of 16 GPIO/Special function
242 * again, the same as port B, but dealing with I2S, SDI, and
243 * more miscellaneous functions
246 #define S3C2410_GPECON S3C2410_GPIOREG(0x40)
247 #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
248 #define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
250 #define S3C2410_GPE0_INP (0x00 << 0)
251 #define S3C2410_GPE0_OUTP (0x01 << 0)
252 #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
253 #define S3C2410_GPE0_MASK (0x03 << 0)
255 #define S3C2410_GPE1_INP (0x00 << 2)
256 #define S3C2410_GPE1_OUTP (0x01 << 2)
257 #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
258 #define S3C2410_GPE1_MASK (0x03 << 2)
260 #define S3C2410_GPE2_INP (0x00 << 4)
261 #define S3C2410_GPE2_OUTP (0x01 << 4)
262 #define S3C2410_GPE2_CDCLK (0x02 << 4)
264 #define S3C2410_GPE3_INP (0x00 << 6)
265 #define S3C2410_GPE3_OUTP (0x01 << 6)
266 #define S3C2410_GPE3_I2SSDI (0x02 << 6)
267 #define S3C2410_GPE3_MASK (0x03 << 6)
269 #define S3C2410_GPE4_INP (0x00 << 8)
270 #define S3C2410_GPE4_OUTP (0x01 << 8)
271 #define S3C2410_GPE4_I2SSDO (0x02 << 8)
272 #define S3C2410_GPE4_MASK (0x03 << 8)
274 #define S3C2410_GPE5_INP (0x00 << 10)
275 #define S3C2410_GPE5_OUTP (0x01 << 10)
276 #define S3C2410_GPE5_SDCLK (0x02 << 10)
278 #define S3C2410_GPE6_INP (0x00 << 12)
279 #define S3C2410_GPE6_OUTP (0x01 << 12)
280 #define S3C2410_GPE6_SDCLK (0x02 << 12)
282 #define S3C2410_GPE7_INP (0x00 << 14)
283 #define S3C2410_GPE7_OUTP (0x01 << 14)
284 #define S3C2410_GPE7_SDCMD (0x02 << 14)
286 #define S3C2410_GPE8_INP (0x00 << 16)
287 #define S3C2410_GPE8_OUTP (0x01 << 16)
288 #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
290 #define S3C2410_GPE9_INP (0x00 << 18)
291 #define S3C2410_GPE9_OUTP (0x01 << 18)
292 #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
294 #define S3C2410_GPE10_INP (0x00 << 20)
295 #define S3C2410_GPE10_OUTP (0x01 << 20)
296 #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
298 #define S3C2410_GPE11_INP (0x00 << 22)
299 #define S3C2410_GPE11_OUTP (0x01 << 22)
300 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
302 #define S3C2410_GPE12_INP (0x00 << 24)
303 #define S3C2410_GPE12_OUTP (0x01 << 24)
304 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
306 #define S3C2410_GPE13_INP (0x00 << 26)
307 #define S3C2410_GPE13_OUTP (0x01 << 26)
308 #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
310 #define S3C2410_GPE14_INP (0x00 << 28)
311 #define S3C2410_GPE14_OUTP (0x01 << 28)
312 #define S3C2410_GPE14_IICSCL (0x02 << 28)
313 #define S3C2410_GPE14_MASK (0x03 << 28)
315 #define S3C2410_GPE15_INP (0x00 << 30)
316 #define S3C2410_GPE15_OUTP (0x01 << 30)
317 #define S3C2410_GPE15_IICSDA (0x02 << 30)
318 #define S3C2410_GPE15_MASK (0x03 << 30)
320 #define S3C2410_GPE_PUPDIS(x) (1<<(x))
322 /* Port F consists of 8 GPIO/Special function
324 * GPIO / interrupt inputs
326 * GPFCON has 2 bits for each of the input pins on port F
327 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
329 * pull up works like all other ports.
332 #define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
333 #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
334 #define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
337 #define S3C2410_GPF0_INP (0x00 << 0)
338 #define S3C2410_GPF0_OUTP (0x01 << 0)
339 #define S3C2410_GPF0_EINT0 (0x02 << 0)
341 #define S3C2410_GPF1_INP (0x00 << 2)
342 #define S3C2410_GPF1_OUTP (0x01 << 2)
343 #define S3C2410_GPF1_EINT1 (0x02 << 2)
345 #define S3C2410_GPF2_INP (0x00 << 4)
346 #define S3C2410_GPF2_OUTP (0x01 << 4)
347 #define S3C2410_GPF2_EINT2 (0x02 << 4)
349 #define S3C2410_GPF3_INP (0x00 << 6)
350 #define S3C2410_GPF3_OUTP (0x01 << 6)
351 #define S3C2410_GPF3_EINT3 (0x02 << 6)
353 #define S3C2410_GPF4_INP (0x00 << 8)
354 #define S3C2410_GPF4_OUTP (0x01 << 8)
355 #define S3C2410_GPF4_EINT4 (0x02 << 8)
357 #define S3C2410_GPF5_INP (0x00 << 10)
358 #define S3C2410_GPF5_OUTP (0x01 << 10)
359 #define S3C2410_GPF5_EINT5 (0x02 << 10)
361 #define S3C2410_GPF6_INP (0x00 << 12)
362 #define S3C2410_GPF6_OUTP (0x01 << 12)
363 #define S3C2410_GPF6_EINT6 (0x02 << 12)
365 #define S3C2410_GPF7_INP (0x00 << 14)
366 #define S3C2410_GPF7_OUTP (0x01 << 14)
367 #define S3C2410_GPF7_EINT7 (0x02 << 14)
369 /* Port G consists of 8 GPIO/IRQ/Special function
371 * GPGCON has 2 bits for each of the input pins on port F
372 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
374 * pull up works like all other ports.
377 #define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
378 #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
379 #define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
381 #define S3C2410_GPG0_INP (0x00 << 0)
382 #define S3C2410_GPG0_OUTP (0x01 << 0)
383 #define S3C2410_GPG0_EINT8 (0x02 << 0)
385 #define S3C2410_GPG1_INP (0x00 << 2)
386 #define S3C2410_GPG1_OUTP (0x01 << 2)
387 #define S3C2410_GPG1_EINT9 (0x02 << 2)
389 #define S3C2410_GPG2_INP (0x00 << 4)
390 #define S3C2410_GPG2_OUTP (0x01 << 4)
391 #define S3C2410_GPG2_EINT10 (0x02 << 4)
393 #define S3C2410_GPG3_INP (0x00 << 6)
394 #define S3C2410_GPG3_OUTP (0x01 << 6)
395 #define S3C2410_GPG3_EINT11 (0x02 << 6)
397 #define S3C2410_GPG4_INP (0x00 << 8)
398 #define S3C2410_GPG4_OUTP (0x01 << 8)
399 #define S3C2410_GPG4_EINT12 (0x02 << 8)
400 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
402 #define S3C2410_GPG5_INP (0x00 << 10)
403 #define S3C2410_GPG5_OUTP (0x01 << 10)
404 #define S3C2410_GPG5_EINT13 (0x02 << 10)
405 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
407 #define S3C2410_GPG6_INP (0x00 << 12)
408 #define S3C2410_GPG6_OUTP (0x01 << 12)
409 #define S3C2410_GPG6_EINT14 (0x02 << 12)
410 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
412 #define S3C2410_GPG7_INP (0x00 << 14)
413 #define S3C2410_GPG7_OUTP (0x01 << 14)
414 #define S3C2410_GPG7_EINT15 (0x02 << 14)
415 #define S3C2410_GPG7_SPICLK1 (0x03 << 14)
417 #define S3C2410_GPG8_INP (0x00 << 16)
418 #define S3C2410_GPG8_OUTP (0x01 << 16)
419 #define S3C2410_GPG8_EINT16 (0x02 << 16)
421 #define S3C2410_GPG9_INP (0x00 << 18)
422 #define S3C2410_GPG9_OUTP (0x01 << 18)
423 #define S3C2410_GPG9_EINT17 (0x02 << 18)
425 #define S3C2410_GPG10_INP (0x00 << 20)
426 #define S3C2410_GPG10_OUTP (0x01 << 20)
427 #define S3C2410_GPG10_EINT18 (0x02 << 20)
429 #define S3C2410_GPG11_INP (0x00 << 22)
430 #define S3C2410_GPG11_OUTP (0x01 << 22)
431 #define S3C2410_GPG11_EINT19 (0x02 << 22)
432 #define S3C2410_GPG11_TCLK1 (0x03 << 22)
434 #define S3C2410_GPG12_INP (0x00 << 24)
435 #define S3C2410_GPG12_OUTP (0x01 << 24)
436 #define S3C2410_GPG12_EINT18 (0x02 << 24)
437 #define S3C2410_GPG12_XMON (0x03 << 24)
439 #define S3C2410_GPG13_INP (0x00 << 26)
440 #define S3C2410_GPG13_OUTP (0x01 << 26)
441 #define S3C2410_GPG13_EINT18 (0x02 << 26)
442 #define S3C2410_GPG13_nXPON (0x03 << 26)
444 #define S3C2410_GPG14_INP (0x00 << 28)
445 #define S3C2410_GPG14_OUTP (0x01 << 28)
446 #define S3C2410_GPG14_EINT18 (0x02 << 28)
447 #define S3C2410_GPG14_YMON (0x03 << 28)
449 #define S3C2410_GPG15_INP (0x00 << 30)
450 #define S3C2410_GPG15_OUTP (0x01 << 30)
451 #define S3C2410_GPG15_EINT18 (0x02 << 30)
452 #define S3C2410_GPG15_nYPON (0x03 << 30)
455 #define S3C2410_GPG_PUPDIS(x) (1<<(x))
457 /* Port H consists of11 GPIO/serial/Misc pins
459 * GPGCON has 2 bits for each of the input pins on port F
460 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
462 * pull up works like all other ports.
465 #define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
466 #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
467 #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
469 #define S3C2410_GPH0_INP (0x00 << 0)
470 #define S3C2410_GPH0_OUTP (0x01 << 0)
471 #define S3C2410_GPH0_nCTS0 (0x02 << 0)
473 #define S3C2410_GPH1_INP (0x00 << 2)
474 #define S3C2410_GPH1_OUTP (0x01 << 2)
475 #define S3C2410_GPH1_nRTS0 (0x02 << 2)
477 #define S3C2410_GPH2_INP (0x00 << 4)
478 #define S3C2410_GPH2_OUTP (0x01 << 4)
479 #define S3C2410_GPH2_TXD0 (0x02 << 4)
481 #define S3C2410_GPH3_INP (0x00 << 6)
482 #define S3C2410_GPH3_OUTP (0x01 << 6)
483 #define S3C2410_GPH3_RXD0 (0x02 << 6)
485 #define S3C2410_GPH4_INP (0x00 << 8)
486 #define S3C2410_GPH4_OUTP (0x01 << 8)
487 #define S3C2410_GPH4_TXD1 (0x02 << 8)
489 #define S3C2410_GPH5_INP (0x00 << 10)
490 #define S3C2410_GPH5_OUTP (0x01 << 10)
491 #define S3C2410_GPH5_RXD1 (0x02 << 10)
493 #define S3C2410_GPH6_INP (0x00 << 12)
494 #define S3C2410_GPH6_OUTP (0x01 << 12)
495 #define S3C2410_GPH6_TXD2 (0x02 << 12)
496 #define S3C2410_GPH6_nRTS1 (0x03 << 12)
498 #define S3C2410_GPH7_INP (0x00 << 14)
499 #define S3C2410_GPH7_OUTP (0x01 << 14)
500 #define S3C2410_GPH7_RXD2 (0x02 << 14)
501 #define S3C2410_GPH7_nCTS1 (0x03 << 14)
503 #define S3C2410_GPH8_INP (0x00 << 16)
504 #define S3C2410_GPH8_OUTP (0x01 << 16)
505 #define S3C2410_GPH8_UCLK (0x02 << 16)
507 #define S3C2410_GPH9_INP (0x00 << 18)
508 #define S3C2410_GPH9_OUTP (0x01 << 18)
509 #define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
511 #define S3C2410_GPH10_INP (0x00 << 20)
512 #define S3C2410_GPH10_OUTP (0x01 << 20)
513 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
515 /* miscellaneous control */
517 #define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
518 #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
520 /* see clock.h for dclk definitions */
522 /* pullup control on databus */
523 #define S3C2410_MISCCR_SPUCR_HEN (0)
524 #define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
525 #define S3C2410_MISCCR_SPUCR_LEN (0)
526 #define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
528 #define S3C2410_MISCCR_USBDEV (0)
529 #define S3C2410_MISCCR_USBHOST (1<<3)
531 #define S3C2410_MISCCR_CLK0_MPLL (0<<4)
532 #define S3C2410_MISCCR_CLK0_UPLL (1<<4)
533 #define S3C2410_MISCCR_CLK0_FCLK (2<<4)
534 #define S3C2410_MISCCR_CLK0_HCLK (3<<4)
535 #define S3C2410_MISCCR_CLK0_PCLK (4<<4)
536 #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
538 #define S3C2410_MISCCR_CLK1_MPLL (0<<8)
539 #define S3C2410_MISCCR_CLK1_UPLL (1<<8)
540 #define S3C2410_MISCCR_CLK1_FCLK (2<<8)
541 #define S3C2410_MISCCR_CLK1_HCLK (3<<8)
542 #define S3C2410_MISCCR_CLK1_PCLK (4<<8)
543 #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
545 #define S3C2410_MISCCR_USBSUSPND0 (1<<12)
546 #define S3C2410_MISCCR_USBSUSPND1 (1<<13)
548 #define S3C2410_MISCCR_nRSTCON (1<<16)
550 /* external interrupt control... */
551 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
552 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
553 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
555 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
557 * Samsung datasheet p9-25
560 #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
561 #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
562 #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
564 /* values for S3C2410_EXTINT0/1/2 */
565 #define S3C2410_EXTINT_LOWLEV (0x00)
566 #define S3C2410_EXTINT_HILEV (0x01)
567 #define S3C2410_EXTINT_FALLEDGE (0x02)
568 #define S3C2410_EXTINT_RISEEDGE (0x04)
569 #define S3C2410_EXTINT_BOTHEDGE (0x06)
571 /* interrupt filtering conrrol for EINT16..EINT23 */
572 #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
573 #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
574 #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
575 #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
577 /* mask: 0=enable, 1=disable
578 * 1 bit EINT, 4=EINT4, 23=EINT23
579 * EINT0,1,2,3 are not handled here.
581 #define S3C2410_EINTMASK S3C2410_GPIOREG(0xA4)
582 #define S3C2410_EINTPEND S3C2410_GPIOREG(0xA8)
584 /* GSTATUS have miscellaneous information in them
588 #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
589 #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
590 #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
591 #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
592 #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
594 #define S3C2410_GSTATUS0_nWAIT (1<<3)
595 #define S3C2410_GSTATUS0_NCON (1<<2)
596 #define S3C2410_GSTATUS0_RnB (1<<1)
597 #define S3C2410_GSTATUS0_nBATTFLT (1<<0)
599 #define S3C2410_GSTATUS2_WTRESET (1<<2)
600 #define S3C2410_GSTATUs2_OFFRESET (1<<1)
601 #define S3C2410_GSTATUS2_PONRESET (1<<0)
603 #endif /* __ASM_ARCH_REGS_GPIO_H */