2 * linux/include/asm-arm/arch-sa1100/collie.h
4 * This file contains the hardware specific definitions for Assabet
5 * Only include this file from SA1100-specific files.
8 * 04-06-2001 Lineo Japan, Inc.
9 * 04-16-2001 SHARP Corporation
10 * 07-07-2002 Chris Larson <clarson@digi.com>
13 #ifndef __ASM_ARCH_COLLIE_H
14 #define __ASM_ARCH_COLLIE_H
16 #include <linux/config.h>
18 #define CF_BUF_CTRL_BASE 0xF0800000
19 #define COLLIE_SCP_REG(adr) (*(volatile unsigned short*)(CF_BUF_CTRL_BASE+(adr)))
20 #define COLLIE_SCP_MCR 0x00
21 #define COLLIE_SCP_CDR 0x04
22 #define COLLIE_SCP_CSR 0x08
23 #define COLLIE_SCP_CPR 0x0C
24 #define COLLIE_SCP_CCR 0x10
25 #define COLLIE_SCP_IRR 0x14
26 #define COLLIE_SCP_IRM 0x14
27 #define COLLIE_SCP_IMR 0x18
28 #define COLLIE_SCP_ISR 0x1C
29 #define COLLIE_SCP_GPCR 0x20
30 #define COLLIE_SCP_GPWR 0x24
31 #define COLLIE_SCP_GPRR 0x28
32 #define COLLIE_SCP_REG_MCR COLLIE_SCP_REG(COLLIE_SCP_MCR)
33 #define COLLIE_SCP_REG_CDR COLLIE_SCP_REG(COLLIE_SCP_CDR)
34 #define COLLIE_SCP_REG_CSR COLLIE_SCP_REG(COLLIE_SCP_CSR)
35 #define COLLIE_SCP_REG_CPR COLLIE_SCP_REG(COLLIE_SCP_CPR)
36 #define COLLIE_SCP_REG_CCR COLLIE_SCP_REG(COLLIE_SCP_CCR)
37 #define COLLIE_SCP_REG_IRR COLLIE_SCP_REG(COLLIE_SCP_IRR)
38 #define COLLIE_SCP_REG_IRM COLLIE_SCP_REG(COLLIE_SCP_IRM)
39 #define COLLIE_SCP_REG_IMR COLLIE_SCP_REG(COLLIE_SCP_IMR)
40 #define COLLIE_SCP_REG_ISR COLLIE_SCP_REG(COLLIE_SCP_ISR)
41 #define COLLIE_SCP_REG_GPCR COLLIE_SCP_REG(COLLIE_SCP_GPCR)
42 #define COLLIE_SCP_REG_GPWR COLLIE_SCP_REG(COLLIE_SCP_GPWR)
43 #define COLLIE_SCP_REG_GPRR COLLIE_SCP_REG(COLLIE_SCP_GPRR)
45 #define COLLIE_SCP_GPCR_PA19 ( 1 << 9 )
46 #define COLLIE_SCP_GPCR_PA18 ( 1 << 8 )
47 #define COLLIE_SCP_GPCR_PA17 ( 1 << 7 )
48 #define COLLIE_SCP_GPCR_PA16 ( 1 << 6 )
49 #define COLLIE_SCP_GPCR_PA15 ( 1 << 5 )
50 #define COLLIE_SCP_GPCR_PA14 ( 1 << 4 )
51 #define COLLIE_SCP_GPCR_PA13 ( 1 << 3 )
52 #define COLLIE_SCP_GPCR_PA12 ( 1 << 2 )
53 #define COLLIE_SCP_GPCR_PA11 ( 1 << 1 )
55 #define COLLIE_SCP_CHARGE_ON COLLIE_SCP_GPCR_PA11
56 #define COLLIE_SCP_DIAG_BOOT1 COLLIE_SCP_GPCR_PA12
57 #define COLLIE_SCP_DIAG_BOOT2 COLLIE_SCP_GPCR_PA13
58 #define COLLIE_SCP_MUTE_L COLLIE_SCP_GPCR_PA14
59 #define COLLIE_SCP_MUTE_R COLLIE_SCP_GPCR_PA15
60 #define COLLIE_SCP_5VON COLLIE_SCP_GPCR_PA16
61 #define COLLIE_SCP_AMP_ON COLLIE_SCP_GPCR_PA17
62 #define COLLIE_SCP_VPEN COLLIE_SCP_GPCR_PA18
63 #define COLLIE_SCP_LB_VOL_CHG COLLIE_SCP_GPCR_PA19
65 #define COLLIE_SCP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
66 COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \
67 COLLIE_SCP_LB_VOL_CHG )
68 #define COLLIE_SCP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \
69 COLLIE_SCP_CHARGE_ON )
71 /* GPIOs for which the generic definition doesn't say much */
73 #define COLLIE_GPIO_ON_KEY GPIO_GPIO (0)
74 #define COLLIE_GPIO_AC_IN GPIO_GPIO (1)
75 #define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14)
76 #define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15)
77 #define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16)
78 #define COLLIE_GPIO_CO GPIO_GPIO (20)
79 #define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21)
80 #define COLLIE_GPIO_CF_CD GPIO_GPIO (22)
81 #define COLLIE_GPIO_UCB1x00_IRQ GPIO_GPIO (23)
82 #define COLLIE_GPIO_WAKEUP GPIO_GPIO (24)
83 #define COLLIE_GPIO_GA_INT GPIO_GPIO (25)
84 #define COLLIE_GPIO_MAIN_BAT_LOW GPIO_GPIO (26)
88 #define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0
89 #define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1
90 #define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14
91 #define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15
92 #define COLLIE_IRQ_GPIO_CO IRQ_GPIO20
93 #define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22
94 #define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23
95 #define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24
96 #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25
97 #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26
99 #define COLLIE_LCM_IRQ_GPIO_RTS IRQ_LOCOMO_GPIO0
100 #define COLLIE_LCM_IRQ_GPIO_CTS IRQ_LOCOMO_GPIO1
101 #define COLLIE_LCM_IRQ_GPIO_DSR IRQ_LOCOMO_GPIO2
102 #define COLLIE_LCM_IRQ_GPIO_DTR IRQ_LOCOMO_GPIO3
103 #define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13
104 #define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14
107 * Flash Memory mappings
111 #define FLASH_MEM_BASE 0xe8ffc000
112 #define FLASH_DATA(adr) (*(volatile unsigned int*)(FLASH_MEM_BASE+(adr)))
113 #define FLASH_DATA_F(adr) (*(volatile float32 *)(FLASH_MEM_BASE+(adr)))
114 #define FLASH_MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a )
117 #define FLASH_COMADJ_MAJIC FLASH_MAGIC_CHG('C','M','A','D')
118 #define FLASH_COMADJ_MAGIC_ADR 0x00
119 #define FLASH_COMADJ_DATA_ADR 0x04
122 #define FLASH_TOUCH_MAJIC FLASH_MAGIC_CHG('T','U','C','H')
123 #define FLASH_TOUCH_MAGIC_ADR 0x1C
124 #define FLASH_TOUCH_XP_DATA_ADR 0x20
125 #define FLASH_TOUCH_YP_DATA_ADR 0x24
126 #define FLASH_TOUCH_XD_DATA_ADR 0x28
127 #define FLASH_TOUCH_YD_DATA_ADR 0x2C
130 #define FLASH_AD_MAJIC FLASH_MAGIC_CHG('B','V','A','D')
131 #define FLASH_AD_MAGIC_ADR 0x30
132 #define FLASH_AD_DATA_ADR 0x34
134 /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
135 #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 /* GPIO0=Version */
136 #define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 /* GPIO1=TBL_CHK */
137 #define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 /* GPIO2=VPNE_ON */
138 #define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3 /* GPIO3=IR_ON */
139 #define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 /* GPIO4=AMP_ON */
140 #define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 /* GPIO5=Version */
141 #define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 /* GPIO5=fs 8k LPF */
142 #define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 /* GPIO6=BUZZER BIAS */
143 #define COLLIE_TC35143_GPIO_MBAT_ON UCB_IO_7 /* GPIO7=MBAT_ON */
144 #define COLLIE_TC35143_GPIO_BBAT_ON UCB_IO_8 /* GPIO8=BBAT_ON */
145 #define COLLIE_TC35143_GPIO_TMP_ON UCB_IO_9 /* GPIO9=TMP_ON */
146 #define COLLIE_TC35143_GPIO_IN ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 )
147 #define COLLIE_TC35143_GPIO_OUT ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \
148 UCB_IO_7 | UCB_IO_8 | UCB_IO_9 )