include/asm-ia64/sn/shub_mmr.h

   1 /*
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
   8  */
   9
  10 #ifndef _ASM_IA64_SN_SHUB_MMR_H
  11 #define _ASM_IA64_SN_SHUB_MMR_H
  12
  13 /* ==================================================================== */
  14 /*                        Register "SH_IPI_INT"                         */
  15 /*               SHub Inter-Processor Interrupt Registers               */
  16 /* ==================================================================== */
  17 #define SH_IPI_INT                               0x0000000110000380UL
  18 #define SH_IPI_INT_MASK                          0x8ff3ffffffefffffUL
  19 #define SH_IPI_INT_INIT                          0x0000000000000000UL
  20
  21 /*   SH_IPI_INT_TYPE                                                    */
  22 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  23 #define SH_IPI_INT_TYPE_SHFT                     0
  24 #define SH_IPI_INT_TYPE_MASK                     0x0000000000000007UL
  25
  26 /*   SH_IPI_INT_AGT                                                     */
  27 /*   Description:  Agent, must be 0 for SHub                            */
  28 #define SH_IPI_INT_AGT_SHFT                      3
  29 #define SH_IPI_INT_AGT_MASK                      0x0000000000000008UL
  30
  31 /*   SH_IPI_INT_PID                                                     */
  32 /*   Description:  Processor ID, same setting as on targeted McKinley  */
  33 #define SH_IPI_INT_PID_SHFT                      4
  34 #define SH_IPI_INT_PID_MASK                      0x00000000000ffff0UL
  35
  36 /*   SH_IPI_INT_BASE                                                    */
  37 /*   Description:  Optional interrupt vector area, 2MB aligned          */
  38 #define SH_IPI_INT_BASE_SHFT                     21
  39 #define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000UL
  40
  41 /*   SH_IPI_INT_IDX                                                     */
  42 /*   Description:  Targeted McKinley interrupt vector                   */
  43 #define SH_IPI_INT_IDX_SHFT                      52
  44 #define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000UL
  45
  46 /*   SH_IPI_INT_SEND                                                    */
  47 /*   Description:  Send Interrupt Message to PI, This generates a puls  */
  48 #define SH_IPI_INT_SEND_SHFT                     63
  49 #define SH_IPI_INT_SEND_MASK                     0x8000000000000000UL
  50
  51 /* ==================================================================== */
  52 /*                     Register "SH_EVENT_OCCURRED"                     */
  53 /*                    SHub Interrupt Event Occurred                     */
  54 /* ==================================================================== */
  55 #define SH_EVENT_OCCURRED                        0x0000000110010000UL
  56 #define SH_EVENT_OCCURRED_ALIAS                  0x0000000110010008UL
  57
  58 /* ==================================================================== */
  59 /*                     Register "SH_PI_CAM_CONTROL"                     */
  60 /*                      CRB CAM MMR Access Control                      */
  61 /* ==================================================================== */
  62 #ifndef __ASSEMBLY__
  63 #define SH_PI_CAM_CONTROL                        0x0000000120050300UL
  64 #else
  65 #define SH_PI_CAM_CONTROL                        0x0000000120050300
  66 #endif
  67
  68 /* ==================================================================== */
  69 /*                        Register "SH_SHUB_ID"                         */
  70 /*                            SHub ID Number                            */
  71 /* ==================================================================== */
  72 #define SH_SHUB_ID                               0x0000000110060580UL
  73 #define SH_SHUB_ID_REVISION_SHFT                 28
  74 #define SH_SHUB_ID_REVISION_MASK                 0x00000000f0000000
  75
  76 /* ==================================================================== */
  77 /*                         Register "SH_PTC_0"                          */
  78 /*       Puge Translation Cache Message Configuration Information       */
  79 /* ==================================================================== */
  80 #define SH_PTC_0                                 0x00000001101a0000UL
  81 #define SH_PTC_1                                 0x00000001101a0080UL
  82
  83 /* ==================================================================== */
  84 /*                          Register "SH_RTC"                           */
  85 /*                           Real-time Clock                            */
  86 /* ==================================================================== */
  87 #define SH_RTC                                   0x00000001101c0000UL
  88 #define SH_RTC_MASK                              0x007fffffffffffffUL
  89
  90 /* ==================================================================== */
  91 /*                 Register "SH_MEMORY_WRITE_STATUS_0|1"                */
  92 /*                    Memory Write Status for CPU 0 & 1                 */
  93 /* ==================================================================== */
  94 #define SH_MEMORY_WRITE_STATUS_0                 0x0000000120070000UL
  95 #define SH_MEMORY_WRITE_STATUS_1                 0x0000000120070080UL
  96
  97 /* ==================================================================== */
  98 /*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
  99 /*                      PIO Write Status for CPU 0 & 1                  */
 100 /* ==================================================================== */
 101 #ifndef __ASSEMBLY__
 102 #define SH_PIO_WRITE_STATUS_0                    0x0000000120070200UL
 103 #define SH_PIO_WRITE_STATUS_1                    0x0000000120070280UL
 104
 105 /*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
 106 /*   Description:  Deadlock response detected                           */
 107 #define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1
 108 #define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002
 109
 110 /*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
 111 /*   Description:  Count of currently pending PIO writes                */
 112 #define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56
 113 #define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000UL
 114 #else
 115 #define SH_PIO_WRITE_STATUS_0                    0x0000000120070200
 116 #define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56
 117 #define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1
 118 #endif
 119
 120 /* ==================================================================== */
 121 /*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
 122 /* ==================================================================== */
 123 #ifndef __ASSEMBLY__
 124 #define SH_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208UL
 125 #else
 126 #define SH_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
 127 #endif
 128
 129 /* ==================================================================== */
 130 /*                     Register "SH_EVENT_OCCURRED"                     */
 131 /*                    SHub Interrupt Event Occurred                     */
 132 /* ==================================================================== */
 133 /*   SH_EVENT_OCCURRED_UART_INT                                         */
 134 /*   Description:  Pending Junk Bus UART Interrupt                      */
 135 #define SH_EVENT_OCCURRED_UART_INT_SHFT          20
 136 #define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
 137
 138 /*   SH_EVENT_OCCURRED_IPI_INT                                          */
 139 /*   Description:  Pending IPI Interrupt                                */
 140 #define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
 141 #define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
 142
 143 /*   SH_EVENT_OCCURRED_II_INT0                                          */
 144 /*   Description:  Pending II 0 Interrupt                               */
 145 #define SH_EVENT_OCCURRED_II_INT0_SHFT           29
 146 #define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
 147
 148 /*   SH_EVENT_OCCURRED_II_INT1                                          */
 149 /*   Description:  Pending II 1 Interrupt                               */
 150 #define SH_EVENT_OCCURRED_II_INT1_SHFT           30
 151 #define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
 152
 153 /* ==================================================================== */
 154 /*                         Register "SH_PTC_0"                          */
 155 /*       Puge Translation Cache Message Configuration Information       */
 156 /* ==================================================================== */
 157 #define SH_PTC_0                                 0x00000001101a0000UL
 158 #define SH_PTC_0_MASK                            0x80000000fffffffd
 159 #define SH_PTC_0_INIT                            0x0000000000000000
 160
 161 /*   SH_PTC_0_A                                                         */
 162 /*   Description:  Type                                                 */
 163 #define SH_PTC_0_A_SHFT                          0
 164 #define SH_PTC_0_A_MASK                          0x0000000000000001
 165
 166 /*   SH_PTC_0_PS                                                        */
 167 /*   Description:  Page Size                                            */
 168 #define SH_PTC_0_PS_SHFT                         2
 169 #define SH_PTC_0_PS_MASK                         0x00000000000000fc
 170
 171 /*   SH_PTC_0_RID                                                       */
 172 /*   Description:  Region ID                                            */
 173 #define SH_PTC_0_RID_SHFT                        8
 174 #define SH_PTC_0_RID_MASK                        0x00000000ffffff00
 175
 176 /*   SH_PTC_0_START                                                     */
 177 /*   Description:  Start                                                */
 178 #define SH_PTC_0_START_SHFT                      63
 179 #define SH_PTC_0_START_MASK                      0x8000000000000000
 180
 181 /* ==================================================================== */
 182 /*                         Register "SH_PTC_1"                          */
 183 /*       Puge Translation Cache Message Configuration Information       */
 184 /* ==================================================================== */
 185 #define SH_PTC_1                                 0x00000001101a0080UL
 186 #define SH_PTC_1_MASK                            0x9ffffffffffff000
 187 #define SH_PTC_1_INIT                            0x0000000000000000
 188
 189 /*   SH_PTC_1_VPN                                                       */
 190 /*   Description:  Virtual page number                                  */
 191 #define SH_PTC_1_VPN_SHFT                        12
 192 #define SH_PTC_1_VPN_MASK                        0x1ffffffffffff000
 193
 194 /*   SH_PTC_1_START                                                     */
 195 /*   Description:  PTC_1 Start                                          */
 196 #define SH_PTC_1_START_SHFT                      63
 197 #define SH_PTC_1_START_MASK                      0x8000000000000000
 198
 199 /*
 200  * Register definitions
 201  */
 202
 203 /* ==================================================================== */
 204 /*                    Register "SH_RTC1_INT_CONFIG"                     */
 205 /*                SHub RTC 1 Interrupt Config Registers                 */
 206 /* ==================================================================== */
 207
 208 #define SH_RTC1_INT_CONFIG                       0x0000000110001480
 209 #define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 210 #define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
 211
 212 /*   SH_RTC1_INT_CONFIG_TYPE                                            */
 213 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 214 #define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
 215 #define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
 216
 217 /*   SH_RTC1_INT_CONFIG_AGT                                             */
 218 /*   Description:  Agent, must be 0 for SHub                            */
 219 #define SH_RTC1_INT_CONFIG_AGT_SHFT              3
 220 #define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
 221
 222 /*   SH_RTC1_INT_CONFIG_PID                                             */
 223 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 224 #define SH_RTC1_INT_CONFIG_PID_SHFT              4
 225 #define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
 226
 227 /*   SH_RTC1_INT_CONFIG_BASE                                            */
 228 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 229 #define SH_RTC1_INT_CONFIG_BASE_SHFT             21
 230 #define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 231
 232 /*   SH_RTC1_INT_CONFIG_IDX                                             */
 233 /*   Description:  Targeted McKinley interrupt vector                   */
 234 #define SH_RTC1_INT_CONFIG_IDX_SHFT              52
 235 #define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 236
 237 /* ==================================================================== */
 238 /*                    Register "SH_RTC1_INT_ENABLE"                     */
 239 /*                SHub RTC 1 Interrupt Enable Registers                 */
 240 /* ==================================================================== */
 241
 242 #define SH_RTC1_INT_ENABLE                       0x0000000110001500
 243 #define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
 244 #define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
 245
 246 /*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
 247 /*   Description:  Enable RTC 1 Interrupt                               */
 248 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
 249 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
 250
 251 /* ==================================================================== */
 252 /*                    Register "SH_RTC2_INT_CONFIG"                     */
 253 /*                SHub RTC 2 Interrupt Config Registers                 */
 254 /* ==================================================================== */
 255
 256 #define SH_RTC2_INT_CONFIG                       0x0000000110001580
 257 #define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 258 #define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
 259
 260 /*   SH_RTC2_INT_CONFIG_TYPE                                            */
 261 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 262 #define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
 263 #define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
 264
 265 /*   SH_RTC2_INT_CONFIG_AGT                                             */
 266 /*   Description:  Agent, must be 0 for SHub                            */
 267 #define SH_RTC2_INT_CONFIG_AGT_SHFT              3
 268 #define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
 269
 270 /*   SH_RTC2_INT_CONFIG_PID                                             */
 271 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 272 #define SH_RTC2_INT_CONFIG_PID_SHFT              4
 273 #define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
 274
 275 /*   SH_RTC2_INT_CONFIG_BASE                                            */
 276 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 277 #define SH_RTC2_INT_CONFIG_BASE_SHFT             21
 278 #define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 279
 280 /*   SH_RTC2_INT_CONFIG_IDX                                             */
 281 /*   Description:  Targeted McKinley interrupt vector                   */
 282 #define SH_RTC2_INT_CONFIG_IDX_SHFT              52
 283 #define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 284
 285 /* ==================================================================== */
 286 /*                    Register "SH_RTC2_INT_ENABLE"                     */
 287 /*                SHub RTC 2 Interrupt Enable Registers                 */
 288 /* ==================================================================== */
 289
 290 #define SH_RTC2_INT_ENABLE                       0x0000000110001600
 291 #define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
 292 #define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
 293
 294 /*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
 295 /*   Description:  Enable RTC 2 Interrupt                               */
 296 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
 297 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
 298
 299 /* ==================================================================== */
 300 /*                    Register "SH_RTC3_INT_CONFIG"                     */
 301 /*                SHub RTC 3 Interrupt Config Registers                 */
 302 /* ==================================================================== */
 303
 304 #define SH_RTC3_INT_CONFIG                       0x0000000110001680
 305 #define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 306 #define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
 307
 308 /*   SH_RTC3_INT_CONFIG_TYPE                                            */
 309 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 310 #define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
 311 #define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
 312
 313 /*   SH_RTC3_INT_CONFIG_AGT                                             */
 314 /*   Description:  Agent, must be 0 for SHub                            */
 315 #define SH_RTC3_INT_CONFIG_AGT_SHFT              3
 316 #define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
 317
 318 /*   SH_RTC3_INT_CONFIG_PID                                             */
 319 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 320 #define SH_RTC3_INT_CONFIG_PID_SHFT              4
 321 #define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
 322
 323 /*   SH_RTC3_INT_CONFIG_BASE                                            */
 324 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 325 #define SH_RTC3_INT_CONFIG_BASE_SHFT             21
 326 #define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 327
 328 /*   SH_RTC3_INT_CONFIG_IDX                                             */
 329 /*   Description:  Targeted McKinley interrupt vector                   */
 330 #define SH_RTC3_INT_CONFIG_IDX_SHFT              52
 331 #define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 332
 333 /* ==================================================================== */
 334 /*                    Register "SH_RTC3_INT_ENABLE"                     */
 335 /*                SHub RTC 3 Interrupt Enable Registers                 */
 336 /* ==================================================================== */
 337
 338 #define SH_RTC3_INT_ENABLE                       0x0000000110001700
 339 #define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
 340 #define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
 341
 342 /*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
 343 /*   Description:  Enable RTC 3 Interrupt                               */
 344 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
 345 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
 346
 347 /*   SH_EVENT_OCCURRED_RTC1_INT                                         */
 348 /*   Description:  Pending RTC 1 Interrupt                              */
 349 #define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
 350 #define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
 351
 352 /*   SH_EVENT_OCCURRED_RTC2_INT                                         */
 353 /*   Description:  Pending RTC 2 Interrupt                              */
 354 #define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
 355 #define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
 356
 357 /*   SH_EVENT_OCCURRED_RTC3_INT                                         */
 358 /*   Description:  Pending RTC 3 Interrupt                              */
 359 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
 360 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 361
 362 /* ==================================================================== */
 363 /*                        Register "SH_INT_CMPB"                        */
 364 /*                  RTC Compare Value for Processor B                   */
 365 /* ==================================================================== */
 366
 367 #define SH_INT_CMPB                              0x00000001101b0080
 368 #define SH_INT_CMPB_MASK                         0x007fffffffffffff
 369 #define SH_INT_CMPB_INIT                         0x0000000000000000
 370
 371 /*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
 372 /*   Description:  Real Time Clock Compare                              */
 373 #define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
 374 #define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
 375
 376 /* ==================================================================== */
 377 /*                        Register "SH_INT_CMPC"                        */
 378 /*                  RTC Compare Value for Processor C                   */
 379 /* ==================================================================== */
 380
 381 #define SH_INT_CMPC                              0x00000001101b0100
 382 #define SH_INT_CMPC_MASK                         0x007fffffffffffff
 383 #define SH_INT_CMPC_INIT                         0x0000000000000000
 384
 385 /*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
 386 /*   Description:  Real Time Clock Compare                              */
 387 #define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
 388 #define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
 389
 390 /* ==================================================================== */
 391 /*                        Register "SH_INT_CMPD"                        */
 392 /*                  RTC Compare Value for Processor D                   */
 393 /* ==================================================================== */
 394
 395 #define SH_INT_CMPD                              0x00000001101b0180
 396 #define SH_INT_CMPD_MASK                         0x007fffffffffffff
 397 #define SH_INT_CMPD_INIT                         0x0000000000000000
 398
 399 /*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
 400 /*   Description:  Real Time Clock Compare                              */
 401 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 402 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 403
 404 #endif /* _ASM_IA64_SN_SHUB_MMR_H */