2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Ralf Baechle
8 #ifndef __ASM_CPU_FEATURES_H
9 #define __ASM_CPU_FEATURES_H
12 #include <asm/cpu-info.h>
13 #include <cpu-feature-overrides.h>
16 * SMP assumption: Options of CPU 0 are a superset of all processors.
17 * This is true for all known MIPS systems.
20 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
23 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
26 #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
29 #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
32 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
34 #ifndef cpu_has_counter
35 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
38 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
40 #ifndef cpu_has_mips16
41 #define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
44 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
47 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
49 #ifndef cpu_has_cache_cdex_p
50 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
52 #ifndef cpu_has_cache_cdex_s
53 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
55 #ifndef cpu_has_prefetch
56 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
58 #ifndef cpu_has_mcheck
59 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
62 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
65 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
67 #ifndef cpu_has_vtag_icache
68 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
70 #ifndef cpu_has_dc_aliases
71 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
73 #ifndef cpu_has_ic_fills_f_dc
74 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
78 * Certain CPUs may throw bizarre exceptions if not the whole cacheline
79 * contains valid instructions. For these we ensure proper alignment of
80 * signal trampolines and pad them to the size of a full cache lines with
81 * nops. This is also used in structure definitions so can't be a test macro
84 #ifndef PLAT_TRAMPOLINE_STUFF_LINE
85 #define PLAT_TRAMPOLINE_STUFF_LINE 0UL
89 # ifndef cpu_has_nofpuex
90 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
92 # ifndef cpu_has_64bits
93 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
95 # ifndef cpu_has_64bit_zero_reg
96 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
98 # ifndef cpu_has_64bit_gp_regs
99 # define cpu_has_64bit_gp_regs 0
101 # ifndef cpu_has_64bit_addresses
102 # define cpu_has_64bit_addresses 0
107 # ifndef cpu_has_nofpuex
108 # define cpu_has_nofpuex 0
110 # ifndef cpu_has_64bits
111 # define cpu_has_64bits 1
113 # ifndef cpu_has_64bit_zero_reg
114 # define cpu_has_64bit_zero_reg 1
116 # ifndef cpu_has_64bit_gp_regs
117 # define cpu_has_64bit_gp_regs 1
119 # ifndef cpu_has_64bit_addresses
120 # define cpu_has_64bit_addresses 1
124 #ifndef cpu_has_subset_pcaches
125 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
128 #ifndef cpu_dcache_line_size
129 #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
131 #ifndef cpu_icache_line_size
132 #define cpu_icache_line_size() current_cpu_data.icache.linesz
134 #ifndef cpu_scache_line_size
135 #define cpu_scache_line_size() current_cpu_data.scache.linesz
138 #endif /* __ASM_CPU_FEATURES_H */