2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
13 #include <linux/config.h>
14 #include <linux/compiler.h>
15 #include <linux/types.h>
17 #include <asm/addrspace.h>
19 #include <asm/cpu-features.h>
21 #include <asm/pgtable-bits.h>
22 #include <asm/processor.h>
23 #include <asm/byteorder.h>
24 #include <mangle-port.h>
27 * Slowdown I/O port space accesses for antique hardware.
29 #undef CONF_SLOWDOWN_IO
32 * Sane hardware offers swapping of I/O space accesses in hardware; less
33 * sane hardware forces software to fiddle with this ...
35 #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
37 #define __ioswab8(x) (x)
39 #ifdef CONFIG_SGI_IP22
41 * IP22 seems braindead enough to swap 16bits values in hardware, but
42 * not 32bits. Go figure... Can't tell without documentation.
44 #define __ioswab16(x) (x)
46 #define __ioswab16(x) swab16(x)
48 #define __ioswab32(x) swab32(x)
49 #define __ioswab64(x) swab64(x)
53 #define __ioswab8(x) (x)
54 #define __ioswab16(x) (x)
55 #define __ioswab32(x) (x)
56 #define __ioswab64(x) (x)
60 #define IO_SPACE_LIMIT 0xffff
63 * On MIPS I/O ports are memory mapped, so we access them using normal
64 * load/store instructions. mips_io_port_base is the virtual address to
65 * which all ports are being mapped. For sake of efficiency some code
66 * assumes that this is an address that can be loaded with a single lui
67 * instruction, so the lower 16 bits must be zero. Should be true on
68 * on any sane architecture; generic code does not use this assumption.
70 extern const unsigned long mips_io_port_base;
72 #define set_io_port_base(base) \
73 do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
76 * Thanks to James van Artsdalen for a better timing-fix than
77 * the two short jumps: using outb's to a nonexistent port seems
78 * to guarantee better timings even on fast machines.
80 * On the other hand, I'd like to be sure of a non-existent port:
81 * I feel a bit unsafe about using 0x80 (should be safe, though)
87 #define __SLOW_DOWN_IO \
88 __asm__ __volatile__( \
90 : : "r" (mips_io_port_base));
92 #ifdef CONF_SLOWDOWN_IO
94 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
96 #define SLOW_DOWN_IO __SLOW_DOWN_IO
103 * virt_to_phys - map virtual addresses to physical
104 * @address: address to remap
106 * The returned physical address is the physical (CPU) mapping for
107 * the memory address given. It is only valid to use this function on
108 * addresses directly mapped or allocated via kmalloc.
110 * This function does not give bus mappings for DMA transfers. In
111 * almost all conceivable cases a device driver should not be using
114 static inline unsigned long virt_to_phys(volatile void * address)
116 return (unsigned long)address - PAGE_OFFSET;
120 * phys_to_virt - map physical address to virtual
121 * @address: address to remap
123 * The returned virtual address is a current CPU mapping for
124 * the memory address given. It is only valid to use this function on
125 * addresses that have a kernel mapping
127 * This function does not handle bus mappings for DMA transfers. In
128 * almost all conceivable cases a device driver should not be using
131 static inline void * phys_to_virt(unsigned long address)
133 return (void *)(address + PAGE_OFFSET);
137 * ISA I/O bus memory addresses are 1:1 with the physical address.
139 static inline unsigned long isa_virt_to_bus(volatile void * address)
141 return (unsigned long)address - PAGE_OFFSET;
144 static inline void * isa_bus_to_virt(unsigned long address)
146 return (void *)(address + PAGE_OFFSET);
149 #define isa_page_to_bus page_to_phys
152 * However PCI ones are not necessarily 1:1 and therefore these interfaces
153 * are forbidden in portable PCI drivers.
155 * Allow them for x86 for legacy drivers, though.
157 #define virt_to_bus virt_to_phys
158 #define bus_to_virt phys_to_virt
161 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
162 * for the processor. This implies the assumption that there is only
163 * one of these busses.
165 extern unsigned long isa_slot_offset;
168 * Change "struct page" to physical address.
170 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
172 extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
173 extern void __iounmap(volatile void __iomem *addr);
175 static inline void * __ioremap_mode(phys_t offset, unsigned long size,
178 if (cpu_has_64bit_addresses) {
179 u64 base = UNCAC_BASE;
182 * R10000 supports a 2 bit uncached attribute therefore
183 * UNCAC_BASE may not equal IO_BASE.
185 if (flags == _CACHE_UNCACHED)
186 base = (u64) IO_BASE;
187 return (void *) (unsigned long) (base + offset);
190 return __ioremap(offset, size, flags);
194 * ioremap - map bus memory into CPU space
195 * @offset: bus address of the memory
196 * @size: size of the resource to map
198 * ioremap performs a platform specific sequence of operations to
199 * make bus memory CPU accessible via the readb/readw/readl/writeb/
200 * writew/writel functions and the other mmio helpers. The returned
201 * address is not guaranteed to be usable directly as a virtual
204 #define ioremap(offset, size) \
205 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
208 * ioremap_nocache - map bus memory into CPU space
209 * @offset: bus address of the memory
210 * @size: size of the resource to map
212 * ioremap_nocache performs a platform specific sequence of operations to
213 * make bus memory CPU accessible via the readb/readw/readl/writeb/
214 * writew/writel functions and the other mmio helpers. The returned
215 * address is not guaranteed to be usable directly as a virtual
218 * This version of ioremap ensures that the memory is marked uncachable
219 * on the CPU as well as honouring existing caching rules from things like
220 * the PCI bus. Note that there are other caches and buffers on many
221 * busses. In paticular driver authors should read up on PCI writes
223 * It's useful if some control registers are in such an area and
224 * write combining or read caching is not desirable:
226 #define ioremap_nocache(offset, size) \
227 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
230 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
231 * requests a cachable mapping, ioremap_uncached_accelerated requests a
232 * mapping using the uncached accelerated mode which isn't supported on
235 #define ioremap_cacheable_cow(offset, size) \
236 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
237 #define ioremap_uncached_accelerated(offset, size) \
238 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
240 static inline void iounmap(volatile void __iomem *addr)
248 #define __raw_readb(addr) \
249 (*(volatile unsigned char *) __swizzle_addr_b((unsigned long)(addr)))
250 #define __raw_readw(addr) \
251 (*(volatile unsigned short *) __swizzle_addr_w((unsigned long)(addr)))
252 #define __raw_readl(addr) \
253 (*(volatile unsigned int *) __swizzle_addr_l((unsigned long)(addr)))
255 #define ____raw_readq(addr) \
259 __asm__ __volatile__ ( \
260 " .set mips3 # ____raw_readq \n" \
262 " dsra32 %M0, %L0, 0 \n" \
263 " sll %L0, %L0, 0 \n" \
266 : "r" (__swizzle_addr_q((unsigned long)(addr)))); \
269 #define __raw_readq(addr) \
271 unsigned long __flags; \
274 local_irq_save(__flags); \
275 __res = ____raw_readq(addr); \
276 local_irq_restore(__flags); \
281 #define ____raw_readq(addr) \
282 (*(volatile unsigned long *)__swizzle_addr_q((unsigned long)(addr)))
283 #define __raw_readq(addr) ____raw_readq(addr)
286 #define readb(addr) __ioswab8(__raw_readb(addr))
287 #define readw(addr) __ioswab16(__raw_readw(addr))
288 #define readl(addr) __ioswab32(__raw_readl(addr))
289 #define readq(addr) __ioswab64(__raw_readq(addr))
290 #define readb_relaxed(addr) readb(addr)
291 #define readw_relaxed(addr) readw(addr)
292 #define readl_relaxed(addr) readl(addr)
293 #define readq_relaxed(addr) readq(addr)
295 #define __raw_writeb(b,addr) \
297 ((*(volatile unsigned char *)__swizzle_addr_b((unsigned long)(addr))) = (b)); \
300 #define __raw_writew(w,addr) \
302 ((*(volatile unsigned short *)__swizzle_addr_w((unsigned long)(addr))) = (w)); \
305 #define __raw_writel(l,addr) \
307 ((*(volatile unsigned int *)__swizzle_addr_l((unsigned long)(addr))) = (l)); \
311 #define ____raw_writeq(val,addr) \
315 __asm__ __volatile__ ( \
317 " dsll32 %L0, %L0, 0 # ____raw_writeq\n" \
318 " dsrl32 %L0, %L0, 0 \n" \
319 " dsll32 %M0, %M0, 0 \n" \
320 " or %L0, %L0, %M0 \n" \
324 : "0" ((unsigned long long)val), \
325 "r" (__swizzle_addr_q((unsigned long)(addr)))); \
328 #define __raw_writeq(val,addr) \
330 unsigned long __flags; \
332 local_irq_save(__flags); \
333 ____raw_writeq(val, addr); \
334 local_irq_restore(__flags); \
338 #define ____raw_writeq(q,addr) \
340 *(volatile unsigned long *)__swizzle_addr_q((unsigned long)(addr)) = (q); \
343 #define __raw_writeq(q,addr) ____raw_writeq(q, addr)
346 #define writeb(b,addr) __raw_writeb(__ioswab8(b),(addr))
347 #define writew(w,addr) __raw_writew(__ioswab16(w),(addr))
348 #define writel(l,addr) __raw_writel(__ioswab32(l),(addr))
349 #define writeq(q,addr) __raw_writeq(__ioswab64(q),(addr))
351 /* Depends on MIPS II instruction set */
352 #define mmiowb() asm volatile ("sync" ::: "memory")
354 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
355 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
356 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
359 * ISA space is 'always mapped' on currently supported MIPS systems, no need
360 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
361 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
362 * are physical addresses. The following constant pointer can be
363 * used as the IO-area pointer (it can be iounmapped as well, so the
364 * analogy with PCI is quite large):
366 #define __ISA_IO_base ((char *)(isa_slot_offset))
368 #define isa_readb(a) readb(__ISA_IO_base + (a))
369 #define isa_readw(a) readw(__ISA_IO_base + (a))
370 #define isa_readl(a) readl(__ISA_IO_base + (a))
371 #define isa_readq(a) readq(__ISA_IO_base + (a))
372 #define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
373 #define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
374 #define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
375 #define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
376 #define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
377 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
378 #define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
381 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
382 * just copy it. The net code will then do the checksum later.
384 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
385 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
388 * check_signature - find BIOS signatures
389 * @io_addr: mmio address to check
390 * @signature: signature block
391 * @length: length of signature
393 * Perform a signature comparison with the mmio address io_addr. This
394 * address should have been obtained by ioremap.
395 * Returns 1 on a match.
397 static inline int check_signature(unsigned long io_addr,
398 const unsigned char *signature, int length)
402 if (readb(io_addr) != *signature)
413 static inline void __outb(unsigned char val, unsigned long port)
415 port = __swizzle_addr_b(port);
417 *(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val);
420 static inline void __outw(unsigned short val, unsigned long port)
422 port = __swizzle_addr_w(port);
424 *(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val);
427 static inline void __outl(unsigned int val, unsigned long port)
429 port = __swizzle_addr_l(port);
431 *(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val);
434 static inline void __outb_p(unsigned char val, unsigned long port)
436 port = __swizzle_addr_b(port);
438 *(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val);
442 static inline void __outw_p(unsigned short val, unsigned long port)
444 port = __swizzle_addr_w(port);
446 *(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val);
450 static inline void __outl_p(unsigned int val, unsigned long port)
452 port = __swizzle_addr_l(port);
454 *(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val);
458 #define outb(val, port) __outb(val, port)
459 #define outw(val, port) __outw(val, port)
460 #define outl(val, port) __outl(val, port)
461 #define outb_p(val, port) __outb_p(val, port)
462 #define outw_p(val, port) __outw_p(val, port)
463 #define outl_p(val, port) __outl_p(val, port)
465 static inline unsigned char __inb(unsigned long port)
467 port = __swizzle_addr_b(port);
469 return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
472 static inline unsigned short __inw(unsigned long port)
474 port = __swizzle_addr_w(port);
476 return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
479 static inline unsigned int __inl(unsigned long port)
481 port = __swizzle_addr_l(port);
483 return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
486 static inline unsigned char __inb_p(unsigned long port)
490 port = __swizzle_addr_b(port);
492 __val = *(volatile u8 *)(mips_io_port_base + port);
495 return __ioswab8(__val);
498 static inline unsigned short __inw_p(unsigned long port)
502 port = __swizzle_addr_w(port);
504 __val = *(volatile u16 *)(mips_io_port_base + port);
507 return __ioswab16(__val);
510 static inline unsigned int __inl_p(unsigned long port)
514 port = __swizzle_addr_l(port);
516 __val = *(volatile u32 *)(mips_io_port_base + port);
519 return __ioswab32(__val);
522 #define inb(port) __inb(port)
523 #define inw(port) __inw(port)
524 #define inl(port) __inl(port)
525 #define inb_p(port) __inb_p(port)
526 #define inw_p(port) __inw_p(port)
527 #define inl_p(port) __inl_p(port)
529 static inline void __outsb(unsigned long port, void *addr, unsigned int count)
532 outb(*(u8 *)addr, port);
537 static inline void __insb(unsigned long port, void *addr, unsigned int count)
540 *(u8 *)addr = inb(port);
545 static inline void __outsw(unsigned long port, void *addr, unsigned int count)
548 outw(*(u16 *)addr, port);
553 static inline void __insw(unsigned long port, void *addr, unsigned int count)
556 *(u16 *)addr = inw(port);
561 static inline void __outsl(unsigned long port, void *addr, unsigned int count)
564 outl(*(u32 *)addr, port);
569 static inline void __insl(unsigned long port, void *addr, unsigned int count)
572 *(u32 *)addr = inl(port);
577 #define outsb(port, addr, count) __outsb(port, addr, count)
578 #define insb(port, addr, count) __insb(port, addr, count)
579 #define outsw(port, addr, count) __outsw(port, addr, count)
580 #define insw(port, addr, count) __insw(port, addr, count)
581 #define outsl(port, addr, count) __outsl(port, addr, count)
582 #define insl(port, addr, count) __insl(port, addr, count)
585 * The caches on some architectures aren't dma-coherent and have need to
586 * handle this in software. There are three types of operations that
587 * can be applied to dma buffers.
589 * - dma_cache_wback_inv(start, size) makes caches and coherent by
590 * writing the content of the caches back to memory, if necessary.
591 * The function also invalidates the affected part of the caches as
592 * necessary before DMA transfers from outside to memory.
593 * - dma_cache_wback(start, size) makes caches and coherent by
594 * writing the content of the caches back to memory, if necessary.
595 * The function also invalidates the affected part of the caches as
596 * necessary before DMA transfers from outside to memory.
597 * - dma_cache_inv(start, size) invalidates the affected parts of the
598 * caches. Dirty lines of the caches may be written back or simply
599 * be discarded. This operation is necessary before dma operations
602 #ifdef CONFIG_DMA_NONCOHERENT
604 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
605 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
606 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
608 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
609 #define dma_cache_wback(start, size) _dma_cache_wback(start,size)
610 #define dma_cache_inv(start, size) _dma_cache_inv(start,size)
612 #else /* Sane hardware */
614 #define dma_cache_wback_inv(start,size) \
615 do { (void) (start); (void) (size); } while (0)
616 #define dma_cache_wback(start,size) \
617 do { (void) (start); (void) (size); } while (0)
618 #define dma_cache_inv(start,size) \
619 do { (void) (start); (void) (size); } while (0)
621 #endif /* CONFIG_DMA_NONCOHERENT */
624 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
625 * Avoid interrupt mucking, just adjust the address for 4-byte access.
626 * Assume the addresses are 8-byte aligned.
629 #define __CSR_32_ADJUST 4
631 #define __CSR_32_ADJUST 0
634 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
635 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
637 #endif /* _ASM_IO_H */