5 #include <linux/config.h>
6 #include <linux/string.h>
7 #include <linux/types.h>
10 #include <asm/byteorder.h>
13 #define SIO_CONFIG_RA 0x398
14 #define SIO_CONFIG_RD 0x399
18 #define PMAC_ISA_MEM_BASE 0
19 #define PMAC_PCI_DRAM_OFFSET 0
20 #define CHRP_ISA_IO_BASE 0xf8000000
21 #define CHRP_ISA_MEM_BASE 0xf7000000
22 #define CHRP_PCI_DRAM_OFFSET 0
23 #define PREP_ISA_IO_BASE 0x80000000
24 #define PREP_ISA_MEM_BASE 0xc0000000
25 #define PREP_PCI_DRAM_OFFSET 0x80000000
27 #if defined(CONFIG_4xx)
28 #include <asm/ibm4xx.h>
29 #elif defined(CONFIG_8xx)
30 #include <asm/mpc8xx.h>
31 #elif defined(CONFIG_8260)
32 #include <asm/mpc8260.h>
33 #elif defined(CONFIG_85xx)
34 #include <asm/mpc85xx.h>
35 #elif defined(CONFIG_APUS)
37 #define _ISA_MEM_BASE 0
38 #define PCI_DRAM_OFFSET 0
39 #else /* Everyone else */
40 #define _IO_BASE isa_io_base
41 #define _ISA_MEM_BASE isa_mem_base
42 #define PCI_DRAM_OFFSET pci_dram_offset
43 #endif /* Platform-dependent I/O */
45 #define ___IO_BASE ((void __iomem *)_IO_BASE)
46 extern unsigned long isa_io_base;
47 extern unsigned long isa_mem_base;
48 extern unsigned long pci_dram_offset;
51 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
53 * Read operations have additional twi & isync to make sure the read
54 * is actually performed (i.e. the data has come back) before we start
55 * executing any following instructions.
57 extern inline int in_8(volatile unsigned char __iomem *addr)
64 "isync" : "=r" (ret) : "m" (*addr));
68 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
70 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
73 extern inline int in_le16(volatile unsigned short __iomem *addr)
77 __asm__ __volatile__("lhbrx %0,0,%1;\n"
79 "isync" : "=r" (ret) :
80 "r" (addr), "m" (*addr));
84 extern inline int in_be16(volatile unsigned short __iomem *addr)
88 __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
90 "isync" : "=r" (ret) : "m" (*addr));
94 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
96 __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
97 "r" (val), "r" (addr));
100 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
102 __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
105 extern inline unsigned in_le32(volatile unsigned __iomem *addr)
109 __asm__ __volatile__("lwbrx %0,0,%1;\n"
111 "isync" : "=r" (ret) :
112 "r" (addr), "m" (*addr));
116 extern inline unsigned in_be32(volatile unsigned __iomem *addr)
120 __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
122 "isync" : "=r" (ret) : "m" (*addr));
126 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
128 __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
129 "r" (val), "r" (addr));
132 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
134 __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
137 static inline __u8 readb(volatile void __iomem *addr)
141 static inline void writeb(__u8 b, volatile void __iomem *addr)
145 #if defined(CONFIG_APUS)
146 static inline __u16 readw(volatile void __iomem *addr)
148 return *(__force volatile __u16 *)(addr);
150 static inline __u32 readl(volatile void __iomem *addr)
152 return *(__force volatile __u32 *)(addr);
154 static inline void writew(__u16 b, volatile void __iomem *addr)
156 *(__force volatile __u16 *)(addr) = b;
158 static inline void writel(__u32 b, volatile void __iomem *addr)
160 *(__force volatile __u32 *)(addr) = b;
163 static inline __u16 readw(volatile void __iomem *addr)
165 return in_le16(addr);
167 static inline __u32 readl(volatile void __iomem *addr)
169 return in_le32(addr);
171 static inline void writew(__u16 b, volatile void __iomem *addr)
175 static inline void writel(__u32 b, volatile void __iomem *addr)
179 #endif /* CONFIG_APUS */
181 #define readb_relaxed(addr) readb(addr)
182 #define readw_relaxed(addr) readw(addr)
183 #define readl_relaxed(addr) readl(addr)
185 static inline __u8 __raw_readb(volatile void __iomem *addr)
187 return *(__force volatile __u8 *)(addr);
189 static inline __u16 __raw_readw(volatile void __iomem *addr)
191 return *(__force volatile __u16 *)(addr);
193 static inline __u32 __raw_readl(volatile void __iomem *addr)
195 return *(__force volatile __u32 *)(addr);
197 static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
199 *(__force volatile __u8 *)(addr) = b;
201 static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
203 *(__force volatile __u16 *)(addr) = b;
205 static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
207 *(__force volatile __u32 *)(addr) = b;
213 * The insw/outsw/insl/outsl macros don't do byte-swapping.
214 * They are only used in practice for transferring buffers which
215 * are arrays of bytes, and byte-swapping is not appropriate in
216 * that case. - paulus
218 #define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
219 #define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
220 #define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
221 #define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
222 #define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
223 #define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
226 * On powermacs, we will get a machine check exception if we
227 * try to read data from a non-existent I/O port. Because the
228 * machine check is an asynchronous exception, it isn't
229 * well-defined which instruction SRR0 will point to when the
231 * With the sequence below (twi; isync; nop), we have found that
232 * the machine check occurs on one of the three instructions on
233 * all PPC implementations tested so far. The twi and isync are
234 * needed on the 601 (in fact twi; sync works too), the isync and
235 * nop are needed on 604[e|r], and any of twi, sync or isync will
236 * work on 603[e], 750, 74xx.
237 * The twi creates an explicit data dependency on the returned
238 * value which seems to be needed to make the 601 wait for the
242 #define __do_in_asm(name, op) \
243 extern __inline__ unsigned int name(unsigned int port) \
246 __asm__ __volatile__( \
252 ".section .fixup,\"ax\"\n" \
256 ".section __ex_table,\"a\"\n" \
263 : "r" (port + ___IO_BASE)); \
267 #define __do_out_asm(name, op) \
268 extern __inline__ void name(unsigned int val, unsigned int port) \
270 __asm__ __volatile__( \
274 ".section __ex_table,\"a\"\n" \
278 : : "r" (val), "r" (port + ___IO_BASE)); \
281 __do_out_asm(outb, "stbx")
283 __do_in_asm(inb, "lbzx")
284 __do_in_asm(inw, "lhz%U1%X1")
285 __do_in_asm(inl, "lwz%U1%X1")
286 __do_out_asm(outl,"stw%U0%X0")
287 __do_out_asm(outw, "sth%U0%X0")
288 #elif defined (CONFIG_8260_PCI9)
289 /* in asm cannot be defined if PCI9 workaround is used */
290 #define inb(port) in_8((port)+___IO_BASE)
291 #define inw(port) in_le16((port)+___IO_BASE)
292 #define inl(port) in_le32((port)+___IO_BASE)
293 __do_out_asm(outw, "sthbrx")
294 __do_out_asm(outl, "stwbrx")
296 __do_in_asm(inb, "lbzx")
297 __do_in_asm(inw, "lhbrx")
298 __do_in_asm(inl, "lwbrx")
299 __do_out_asm(outw, "sthbrx")
300 __do_out_asm(outl, "stwbrx")
304 #define inb_p(port) inb((port))
305 #define outb_p(val, port) outb((val), (port))
306 #define inw_p(port) inw((port))
307 #define outw_p(val, port) outw((val), (port))
308 #define inl_p(port) inl((port))
309 #define outl_p(val, port) outl((val), (port))
311 extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
312 extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
313 extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
314 extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
315 extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
316 extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
317 extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
318 extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
319 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
320 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
323 * The *_ns versions below don't do byte-swapping.
324 * Neither do the standard versions now, these are just here
327 #define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
328 #define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
329 #define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
330 #define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
333 #define IO_SPACE_LIMIT ~0
335 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
337 memset((void __force *)addr, val, count);
339 static inline void memcpy_fromio(void *dst, volatile void __iomem *src, int count)
341 memcpy(dst, (void __force *) src, count);
343 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
345 memcpy((void __force *) dst, src, count);
349 * Map in an area of physical address space, for accessing
352 extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
353 unsigned long flags);
354 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
356 extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
358 #define ioremap_nocache(addr, size) ioremap((addr), (size))
359 extern void iounmap(volatile void __iomem *addr);
360 extern unsigned long iopa(unsigned long addr);
361 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
362 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
363 unsigned int size, int flags);
366 * The PCI bus is inherently Little-Endian. The PowerPC is being
367 * run Big-Endian. Thus all values which cross the [PCI] barrier
368 * must be endian-adjusted. Also, the local DRAM has a different
369 * address from the PCI point of view, thus buffer addresses also
370 * have to be modified [mapped] appropriately.
372 extern inline unsigned long virt_to_bus(volatile void * address)
375 if (address == (void *)0)
377 return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
379 return iopa ((unsigned long) address);
383 extern inline void * bus_to_virt(unsigned long address)
388 return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
390 return (void*) mm_ptov (address);
395 * Change virtual addresses to physical addresses and vv, for
396 * addresses in the area where the kernel has the RAM mapped.
398 extern inline unsigned long virt_to_phys(volatile void * address)
401 return (unsigned long) address - KERNELBASE;
403 return iopa ((unsigned long) address);
407 extern inline void * phys_to_virt(unsigned long address)
410 return (void *) (address + KERNELBASE);
412 return (void*) mm_ptov (address);
417 * Change "struct page" to physical address.
419 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
420 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
423 * Enforce In-order Execution of I/O:
424 * Acts as a barrier to ensure all previous I/O accesses have
425 * completed before any further ones are issued.
427 extern inline void eieio(void)
429 __asm__ __volatile__ ("eieio" : : : "memory");
432 /* Enforce in-order execution of data I/O.
433 * No distinction between read/write on PPC; use eieio for all three.
435 #define iobarrier_rw() eieio()
436 #define iobarrier_r() eieio()
437 #define iobarrier_w() eieio()
439 static inline int check_signature(volatile void __iomem * io_addr,
440 const unsigned char *signature, int length)
444 if (readb(io_addr) != *signature)
456 * Here comes the ppc implementation of the IOMAP
459 static inline unsigned int ioread8(void __iomem *addr)
464 static inline unsigned int ioread16(void __iomem *addr)
469 static inline unsigned int ioread32(void __iomem *addr)
474 static inline void iowrite8(u8 val, void __iomem *addr)
479 static inline void iowrite16(u16 val, void __iomem *addr)
484 static inline void iowrite32(u32 val, void __iomem *addr)
489 static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
491 _insb((u8 __force *) addr, dst, count);
494 static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
496 _insw_ns((u16 __force *) addr, dst, count);
499 static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
501 _insl_ns((u32 __force *) addr, dst, count);
504 static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
506 _outsb((u8 __force *) addr, src, count);
509 static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
511 _outsw_ns((u16 __force *) addr, src, count);
514 static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
516 _outsl_ns((u32 __force *) addr, src, count);
519 /* Create a virtual mapping cookie for an IO port range */
520 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
521 extern void ioport_unmap(void __iomem *);
523 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
525 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
526 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
528 #endif /* _PPC_IO_H */
530 #ifdef CONFIG_8260_PCI9
531 #include <asm/mpc8260_pci9.h>
534 #endif /* __KERNEL__ */