2 * include/asm-ppc/mpc85xx.h
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2004 Freescale Semiconductor, Inc
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #ifndef __ASM_MPC85xx_H__
18 #define __ASM_MPC85xx_H__
20 #include <linux/config.h>
25 #ifdef CONFIG_MPC8540_ADS
26 #include <platforms/85xx/mpc8540_ads.h>
28 #ifdef CONFIG_MPC8555_CDS
29 #include <platforms/85xx/mpc8555_cds.h>
31 #ifdef CONFIG_MPC8560_ADS
32 #include <platforms/85xx/mpc8560_ads.h>
35 #include <platforms/85xx/sbc8560.h>
38 #define _IO_BASE isa_io_base
39 #define _ISA_MEM_BASE isa_mem_base
41 #define PCI_DRAM_OFFSET pci_dram_offset
43 #define PCI_DRAM_OFFSET 0
47 * The "residual" board information structure the boot loader passes
50 extern unsigned char __res[];
52 /* Internal IRQs on MPC85xx OpenPIC */
53 /* Not all of these exist on all MPC85xx implementations */
55 #ifndef MPC85xx_OPENPIC_IRQ_OFFSET
56 #define MPC85xx_OPENPIC_IRQ_OFFSET 64
59 /* The 32 internal sources */
60 #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
61 #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
62 #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
63 #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
64 #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
65 #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
66 #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
67 #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
68 #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
69 #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
70 #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
71 #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
72 #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
73 #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
74 #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
75 #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
76 #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
77 #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
78 #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
79 #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
80 #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
81 #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
82 #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
83 #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
84 #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
85 #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
87 /* The 12 external interrupt lines */
88 #define MPC85xx_IRQ_EXT0 (32 + MPC85xx_OPENPIC_IRQ_OFFSET)
89 #define MPC85xx_IRQ_EXT1 (33 + MPC85xx_OPENPIC_IRQ_OFFSET)
90 #define MPC85xx_IRQ_EXT2 (34 + MPC85xx_OPENPIC_IRQ_OFFSET)
91 #define MPC85xx_IRQ_EXT3 (35 + MPC85xx_OPENPIC_IRQ_OFFSET)
92 #define MPC85xx_IRQ_EXT4 (36 + MPC85xx_OPENPIC_IRQ_OFFSET)
93 #define MPC85xx_IRQ_EXT5 (37 + MPC85xx_OPENPIC_IRQ_OFFSET)
94 #define MPC85xx_IRQ_EXT6 (38 + MPC85xx_OPENPIC_IRQ_OFFSET)
95 #define MPC85xx_IRQ_EXT7 (39 + MPC85xx_OPENPIC_IRQ_OFFSET)
96 #define MPC85xx_IRQ_EXT8 (40 + MPC85xx_OPENPIC_IRQ_OFFSET)
97 #define MPC85xx_IRQ_EXT9 (41 + MPC85xx_OPENPIC_IRQ_OFFSET)
98 #define MPC85xx_IRQ_EXT10 (42 + MPC85xx_OPENPIC_IRQ_OFFSET)
99 #define MPC85xx_IRQ_EXT11 (43 + MPC85xx_OPENPIC_IRQ_OFFSET)
101 /* Offset from CCSRBAR */
102 #define MPC85xx_CPM_OFFSET (0x80000)
103 #define MPC85xx_CPM_SIZE (0x40000)
104 #define MPC85xx_DMA_OFFSET (0x21000)
105 #define MPC85xx_DMA_SIZE (0x01000)
106 #define MPC85xx_ENET1_OFFSET (0x24000)
107 #define MPC85xx_ENET1_SIZE (0x01000)
108 #define MPC85xx_ENET2_OFFSET (0x25000)
109 #define MPC85xx_ENET2_SIZE (0x01000)
110 #define MPC85xx_ENET3_OFFSET (0x26000)
111 #define MPC85xx_ENET3_SIZE (0x01000)
112 #define MPC85xx_GUTS_OFFSET (0xe0000)
113 #define MPC85xx_GUTS_SIZE (0x01000)
114 #define MPC85xx_IIC1_OFFSET (0x03000)
115 #define MPC85xx_IIC1_SIZE (0x01000)
116 #define MPC85xx_OPENPIC_OFFSET (0x40000)
117 #define MPC85xx_OPENPIC_SIZE (0x40000)
118 #define MPC85xx_PCI1_OFFSET (0x08000)
119 #define MPC85xx_PCI1_SIZE (0x01000)
120 #define MPC85xx_PCI2_OFFSET (0x09000)
121 #define MPC85xx_PCI2_SIZE (0x01000)
122 #define MPC85xx_PERFMON_OFFSET (0xe1000)
123 #define MPC85xx_PERFMON_SIZE (0x01000)
124 #define MPC85xx_SEC2_OFFSET (0x30000)
125 #define MPC85xx_SEC2_SIZE (0x10000)
126 #define MPC85xx_UART0_OFFSET (0x04500)
127 #define MPC85xx_UART0_SIZE (0x00100)
128 #define MPC85xx_UART1_OFFSET (0x04600)
129 #define MPC85xx_UART1_SIZE (0x00100)
131 #define MPC85xx_CCSRBAR_SIZE (1024*1024)
133 /* Let modules/drivers get at CCSRBAR */
134 extern phys_addr_t get_ccsrbar(void);
137 #define CCSRBAR get_ccsrbar()
139 #define CCSRBAR BOARD_CCSRBAR
142 #endif /* CONFIG_85xx */
143 #endif /* __ASM_MPC85xx_H__ */
144 #endif /* __KERNEL__ */