2 * PowerPC memory management structures
4 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
21 /* Time to allow for more things here */
22 typedef unsigned long mm_context_id_t;
25 #ifdef CONFIG_HUGETLB_PAGE
26 u16 htlb_segs; /* bitmask */
30 #ifdef CONFIG_HUGETLB_PAGE
31 #define KERNEL_LOW_HPAGES .htlb_segs = 0,
33 #define KERNEL_LOW_HPAGES
36 #define KERNEL_CONTEXT(ea) ({ \
37 mm_context_t ctx = { .id = REGION_ID(ea), KERNEL_LOW_HPAGES}; \
41 * Hardware Segment Lookaside Buffer Entry
42 * This structure has been padded out to two 64b doublewords (actual SLBE's are
43 * 94 bits). This padding facilites use by the segment management
47 unsigned long esid: 36; /* Effective segment ID */
48 unsigned long resv0:20; /* Reserved */
49 unsigned long v: 1; /* Entry valid (v=1) or invalid */
50 unsigned long resv1: 1; /* Reserved */
51 unsigned long ks: 1; /* Supervisor (privileged) state storage key */
52 unsigned long kp: 1; /* Problem state storage key */
53 unsigned long n: 1; /* No-execute if n=1 */
54 unsigned long resv2: 3; /* padding to a 64b boundary */
58 unsigned long vsid: 52; /* Virtual segment ID */
59 unsigned long resv0:12; /* Padding to a 64b boundary */
75 unsigned long esid: 36; /* Effective segment ID */
76 unsigned long v: 1; /* Entry valid (v=1) or invalid */
77 unsigned long null1:15; /* padding to a 64b boundary */
78 unsigned long index:12; /* Index to select SLB entry. Used by slbmte */
82 unsigned long vsid: 52; /* Virtual segment ID */
83 unsigned long ks: 1; /* Supervisor (privileged) state storage key */
84 unsigned long kp: 1; /* Problem state storage key */
85 unsigned long n: 1; /* No-execute if n=1 */
86 unsigned long l: 1; /* Virt pages are large (l=1) or 4KB (l=0) */
87 unsigned long c: 1; /* Class */
88 unsigned long resv0: 7; /* Padding to a 64b boundary */
103 /* Hardware Page Table Entry */
105 #define HPTES_PER_GROUP 8
108 unsigned long avpn:57; /* vsid | api == avpn */
109 unsigned long : 2; /* Software use */
110 unsigned long bolted: 1; /* HPTE is "bolted" */
111 unsigned long lock: 1; /* lock on pSeries SMP */
112 unsigned long l: 1; /* Virtual page is large (L=1) or 4 KB (L=0) */
113 unsigned long h: 1; /* Hash function identifier */
114 unsigned long v: 1; /* Valid (v=1) or invalid (v=0) */
118 unsigned long pp0: 1; /* Page protection bit 0 */
119 unsigned long ts: 1; /* Tag set bit */
120 unsigned long rpn: 50; /* Real page number */
121 unsigned long : 2; /* Reserved */
122 unsigned long ac: 1; /* Address compare */
123 unsigned long r: 1; /* Referenced */
124 unsigned long c: 1; /* Changed */
125 unsigned long w: 1; /* Write-thru cache mode */
126 unsigned long i: 1; /* Cache inhibited */
127 unsigned long m: 1; /* Memory coherence required */
128 unsigned long g: 1; /* Guarded */
129 unsigned long n: 1; /* No-execute */
130 unsigned long pp: 2; /* Page protection bits 1:2 */
134 char padding[6]; /* padding */
135 unsigned long : 6; /* padding */
136 unsigned long flags: 10; /* HPTE flags */
141 unsigned long dword0;
146 unsigned long dword1;
148 Hpte_dword1_flags flags;
152 /* Values for PP (assumes Ks=0, Kp=1) */
153 /* pp0 will always be 0 for linux */
154 #define PP_RWXX 0 /* Supervisor read/write, User none */
155 #define PP_RWRX 1 /* Supervisor read/write, User read */
156 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
157 #define PP_RXRX 3 /* Supervisor read, User read */
162 unsigned long htab_num_ptegs;
163 unsigned long htab_hash_mask;
164 unsigned long next_round_robin;
165 unsigned long last_kernel_address;
168 extern HTAB htab_data;
170 void invalidate_hpte( unsigned long slot );
171 long select_hpte_slot( unsigned long vpn );
172 void create_valid_hpte( unsigned long slot, unsigned long vpn,
173 unsigned long prpn, unsigned hash,
174 void * ptep, unsigned hpteflags,
177 #define PD_SHIFT (10+12) /* Page directory */
178 #define PD_MASK 0x02FF
179 #define PT_SHIFT (12) /* Page Table */
180 #define PT_MASK 0x02FF
182 #define LARGE_PAGE_SHIFT 24
184 static inline unsigned long hpt_hash(unsigned long vpn, int large)
197 return (vsid & 0x7fffffffffUL) ^ page;
200 static inline void __tlbie(unsigned long va, int large)
202 /* clear top 16 bits, non SLS segment */
203 va &= ~(0xffffULL << 48);
206 asm volatile("tlbie %0,1" : : "r"(va) : "memory");
208 asm volatile("tlbie %0,0" : : "r"(va) : "memory");
211 static inline void tlbie(unsigned long va, int large)
213 asm volatile("ptesync": : :"memory");
215 asm volatile("eieio; tlbsync; ptesync": : :"memory");
218 static inline void __tlbiel(unsigned long va)
220 /* clear top 16 bits, non SLS segment */
221 va &= ~(0xffffULL << 48);
224 * Thanks to Alan Modra we are now able to use machine specific
225 * assembly instructions (like tlbiel) by using the gas -many flag.
226 * However we have to support older toolchains so for the moment
230 asm volatile("tlbiel %0" : : "r"(va) : "memory");
232 asm volatile(".long 0x7c000224 | (%0 << 11)" : : "r"(va) : "memory");
236 static inline void tlbiel(unsigned long va)
238 asm volatile("ptesync": : :"memory");
240 asm volatile("ptesync": : :"memory");
244 * Handle a fault by adding an HPTE. If the address can't be determined
245 * to be valid via Linux page tables, return 1. If handled return 0
247 extern int __hash_page(unsigned long ea, unsigned long access,
248 unsigned long vsid, pte_t *ptep, unsigned long trap,
251 extern void htab_finish_init(void);
253 #endif /* __ASSEMBLY__ */
256 * Location of cpu0's segment table
258 #define STAB0_PAGE 0x9
259 #define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
260 #define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
262 /* Block size masks */
263 #define BL_128K 0x000
264 #define BL_256K 0x001
265 #define BL_512K 0x003
273 #define BL_128M 0x3FF
274 #define BL_256M 0x7FF
276 /* Used to set up SDR1 register */
277 #define HASH_TABLE_SIZE_64K 0x00010000
278 #define HASH_TABLE_SIZE_128K 0x00020000
279 #define HASH_TABLE_SIZE_256K 0x00040000
280 #define HASH_TABLE_SIZE_512K 0x00080000
281 #define HASH_TABLE_SIZE_1M 0x00100000
282 #define HASH_TABLE_SIZE_2M 0x00200000
283 #define HASH_TABLE_SIZE_4M 0x00400000
284 #define HASH_TABLE_MASK_64K 0x000
285 #define HASH_TABLE_MASK_128K 0x001
286 #define HASH_TABLE_MASK_256K 0x003
287 #define HASH_TABLE_MASK_512K 0x007
288 #define HASH_TABLE_MASK_1M 0x00F
289 #define HASH_TABLE_MASK_2M 0x01F
290 #define HASH_TABLE_MASK_4M 0x03F
292 /* These are the Ks and Kp from the PowerPC books. For proper operation,
296 #define MI_Ks 0x80000000 /* Should not be set */
297 #define MI_Kp 0x40000000 /* Should always be set */
299 /* The effective page number register. When read, contains the information
300 * about the last instruction TLB miss. When MI_RPN is written, bits in
301 * this register are used to create the TLB entry.
304 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
305 #define MI_EVALID 0x00000200 /* Entry is valid */
306 #define MI_ASIDMASK 0x0000000f /* ASID match value */
307 /* Reset value is undefined */
309 /* A "level 1" or "segment" or whatever you want to call it register.
310 * For the instruction TLB, it contains bits that get loaded into the
311 * TLB entry when the MI_RPN is written.
314 #define MI_APG 0x000001e0 /* Access protection group (0) */
315 #define MI_GUARDED 0x00000010 /* Guarded storage */
316 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
317 #define MI_PS8MEG 0x0000000c /* 8M page size */
318 #define MI_PS512K 0x00000004 /* 512K page size */
319 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
320 #define MI_SVALID 0x00000001 /* Segment entry is valid */
321 /* Reset value is undefined */
323 /* Real page number. Defined by the pte. Writing this register
324 * causes a TLB entry to be created for the instruction TLB, using
325 * additional information from the MI_EPN, and MI_TWC registers.
329 /* Define an RPN value for mapping kernel memory to large virtual
330 * pages for boot initialization. This has real page number of 0,
331 * large page size, shared page, cache enabled, and valid.
332 * Also mark all subpages valid and write access.
334 #define MI_BOOTINIT 0x000001fd
336 #define MD_CTR 792 /* Data TLB control register */
337 #define MD_GPM 0x80000000 /* Set domain manager mode */
338 #define MD_PPM 0x40000000 /* Set subpage protection */
339 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
340 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
341 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
342 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
343 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
344 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
345 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
347 #define M_CASID 793 /* Address space ID (context) to match */
348 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
351 /* These are the Ks and Kp from the PowerPC books. For proper operation,
355 #define MD_Ks 0x80000000 /* Should not be set */
356 #define MD_Kp 0x40000000 /* Should always be set */
358 /* The effective page number register. When read, contains the information
359 * about the last instruction TLB miss. When MD_RPN is written, bits in
360 * this register are used to create the TLB entry.
363 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
364 #define MD_EVALID 0x00000200 /* Entry is valid */
365 #define MD_ASIDMASK 0x0000000f /* ASID match value */
366 /* Reset value is undefined */
368 /* The pointer to the base address of the first level page table.
369 * During a software tablewalk, reading this register provides the address
370 * of the entry associated with MD_EPN.
373 #define M_L1TB 0xfffff000 /* Level 1 table base address */
374 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
375 /* Reset value is undefined */
377 /* A "level 1" or "segment" or whatever you want to call it register.
378 * For the data TLB, it contains bits that get loaded into the TLB entry
379 * when the MD_RPN is written. It is also provides the hardware assist
380 * for finding the PTE address during software tablewalk.
383 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
384 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
385 #define MD_APG 0x000001e0 /* Access protection group (0) */
386 #define MD_GUARDED 0x00000010 /* Guarded storage */
387 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
388 #define MD_PS8MEG 0x0000000c /* 8M page size */
389 #define MD_PS512K 0x00000004 /* 512K page size */
390 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
391 #define MD_WT 0x00000002 /* Use writethrough page attribute */
392 #define MD_SVALID 0x00000001 /* Segment entry is valid */
393 /* Reset value is undefined */
396 /* Real page number. Defined by the pte. Writing this register
397 * causes a TLB entry to be created for the data TLB, using
398 * additional information from the MD_EPN, and MD_TWC registers.
402 /* This is a temporary storage register that could be used to save
403 * a processor working register during a tablewalk.
407 #endif /* _PPC64_MMU_H_ */