6 * linux/include/asm-sh/irq.h
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
14 #include <linux/config.h>
15 #include <asm/machvec.h>
16 #include <asm/ptrace.h> /* for pt_regs */
18 #if defined(CONFIG_SH_HP600) || \
19 defined(CONFIG_SH_RTS7751R2D) || \
20 defined(CONFIG_SH_HS7751RVOIP)
21 #include <asm/mach/ide.h>
24 #if defined(CONFIG_CPU_SH3)
25 #define INTC_IPRA 0xfffffee2UL
26 #define INTC_IPRB 0xfffffee4UL
27 #elif defined(CONFIG_CPU_SH4)
28 #define INTC_IPRA 0xffd00004UL
29 #define INTC_IPRB 0xffd00008UL
30 #define INTC_IPRC 0xffd0000cUL
31 #define INTC_IPRD 0xffd00010UL
36 # define IRQ_CFCARD 14
39 # define IRQ_PCMCIA 15
44 #define TIMER_IPR_ADDR INTC_IPRA
45 #define TIMER_IPR_POS 3
46 #define TIMER_PRIORITY 2
49 #define TIMER1_IPR_ADDR INTC_IPRA
50 #define TIMER1_IPR_POS 2
51 #define TIMER1_PRIORITY 4
54 #define RTC_IPR_ADDR INTC_IPRA
56 #define RTC_PRIORITY TIMER_PRIORITY
58 #if defined(CONFIG_CPU_SH3)
63 #define DMA_IPR_ADDR INTC_IPRE
65 #define DMA_PRIORITY 7
66 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
69 #define TIMER2_IPR_ADDR INTC_IPRA
70 #define TIMER2_IPR_POS 1
71 #define TIMER2_PRIORITY 2
75 #define WDT_IPR_ADDR INTC_IPRB
77 #define WDT_PRIORITY 2
79 /* SIM (SIM Card Module) */
80 #define SIM_ERI_IRQ 23
81 #define SIM_RXI_IRQ 24
82 #define SIM_TXI_IRQ 25
83 #define SIM_TEND_IRQ 26
84 #define SIM_IPR_ADDR INTC_IPRB
86 #define SIM_PRIORITY 2
90 #define VIO_IPR_ADDR INTC_IPRE
92 #define VIO_PRIORITY 2
94 /* MFI (Multi Functional Interface) */
96 #define MFI_IPR_ADDR INTC_IPRE
98 #define MFI_PRIORITY 2
100 /* VPU (Video Processing Unit) */
102 #define VPU_IPR_ADDR INTC_IPRE
103 #define VPU_IPR_POS 0
104 #define VPU_PRIORITY 2
106 /* KEY (Key Scan Interface) */
108 #define KEY_IPR_ADDR INTC_IPRF
109 #define KEY_IPR_POS 3
110 #define KEY_PRIORITY 2
112 /* CMT (Compare Match Timer) */
114 #define CMT_IPR_ADDR INTC_IPRF
115 #define CMT_IPR_POS 0
116 #define CMT_PRIORITY 2
123 #define DMA1_IPR_ADDR INTC_IPRE
124 #define DMA1_IPR_POS 3
125 #define DMA1_PRIORITY 7
130 #define DMA2_IPR_ADDR INTC_IPRF
131 #define DMA2_IPR_POS 2
132 #define DMA2_PRIORITY 7
136 #define SIOF0_IPR_ADDR INTC_IPRH
137 #define SIOF0_IPR_POS 3
138 #define SIOF0_PRIORITY 3
140 /* FLCTL (Flash Memory Controller) */
142 #define FLTEND_IRQ 93
143 #define FLTRQ0_IRQ 94
144 #define FLTRQ1_IRQ 95
145 #define FLCTL_IPR_ADDR INTC_IPRH
146 #define FLCTL_IPR_POS 1
147 #define FLCTL_PRIORITY 3
149 /* IIC (IIC Bus Interface) */
150 #define IIC_ALI_IRQ 96
151 #define IIC_TACKI_IRQ 97
152 #define IIC_WAITI_IRQ 98
153 #define IIC_DTEI_IRQ 99
154 #define IIC_IPR_ADDR INTC_IPRH
155 #define IIC_IPR_POS 0
156 #define IIC_PRIORITY 3
160 #define SIO0_IPR_ADDR INTC_IPRI
161 #define SIO0_IPR_POS 3
162 #define SIO0_PRIORITY 3
164 /* SIU (Sound Interface Unit) */
166 #define SIU_IPR_ADDR INTC_IPRJ
167 #define SIU_IPR_POS 1
168 #define SIU_PRIORITY 3
171 #elif defined(CONFIG_CPU_SH4)
176 #define DMTE4_IRQ 44 /* 7751R only */
177 #define DMTE5_IRQ 45 /* 7751R only */
178 #define DMTE6_IRQ 46 /* 7751R only */
179 #define DMTE7_IRQ 47 /* 7751R only */
181 #define DMA_IPR_ADDR INTC_IPRC
182 #define DMA_IPR_POS 2
183 #define DMA_PRIORITY 7
186 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
187 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
188 defined (CONFIG_CPU_SUBTYPE_SH7751)
189 #define SCI_ERI_IRQ 23
190 #define SCI_RXI_IRQ 24
191 #define SCI_TXI_IRQ 25
192 #define SCI_IPR_ADDR INTC_IPRB
193 #define SCI_IPR_POS 1
194 #define SCI_PRIORITY 3
197 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
199 #define SCIF0_IPR_ADDR INTC_IPRG
200 #define SCIF0_IPR_POS 3
201 #define SCIF0_PRIORITY 3
202 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
203 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7709)
205 #define SCIF_ERI_IRQ 56
206 #define SCIF_RXI_IRQ 57
207 #define SCIF_BRI_IRQ 58
208 #define SCIF_TXI_IRQ 59
209 #define SCIF_IPR_ADDR INTC_IPRE
210 #define SCIF_IPR_POS 1
211 #define SCIF_PRIORITY 3
213 #define IRDA_ERI_IRQ 52
214 #define IRDA_RXI_IRQ 53
215 #define IRDA_BRI_IRQ 54
216 #define IRDA_TXI_IRQ 55
217 #define IRDA_IPR_ADDR INTC_IPRE
218 #define IRDA_IPR_POS 2
219 #define IRDA_PRIORITY 3
220 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
221 defined(CONFIG_CPU_SUBTYPE_ST40STB1)
222 #define SCIF_ERI_IRQ 40
223 #define SCIF_RXI_IRQ 41
224 #define SCIF_BRI_IRQ 42
225 #define SCIF_TXI_IRQ 43
226 #define SCIF_IPR_ADDR INTC_IPRC
227 #define SCIF_IPR_POS 1
228 #define SCIF_PRIORITY 3
229 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
230 #define SCIF1_ERI_IRQ 23
231 #define SCIF1_RXI_IRQ 24
232 #define SCIF1_BRI_IRQ 25
233 #define SCIF1_TXI_IRQ 26
234 #define SCIF1_IPR_ADDR INTC_IPRB
235 #define SCIF1_IPR_POS 1
236 #define SCIF1_PRIORITY 3
240 /* NR_IRQS is made from three components:
241 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
242 * 2. PINT_NR_IRQS - number of PINT interrupts
243 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
246 /* 1. ONCHIP_NR_IRQS */
247 #ifdef CONFIG_SH_GENERIC
248 # define ONCHIP_NR_IRQS 144
250 # if defined(CONFIG_CPU_SUBTYPE_SH7604)
251 # define ONCHIP_NR_IRQS 24 // Actually 21
252 # elif defined(CONFIG_CPU_SUBTYPE_SH7707)
253 # define ONCHIP_NR_IRQS 64
254 # define PINT_NR_IRQS 16
255 # elif defined(CONFIG_CPU_SUBTYPE_SH7708)
256 # define ONCHIP_NR_IRQS 32
257 # elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
258 defined(CONFIG_CPU_SUBTYPE_SH7705)
259 # define ONCHIP_NR_IRQS 64 // Actually 61
260 # define PINT_NR_IRQS 16
261 # elif defined(CONFIG_CPU_SUBTYPE_SH7750)
262 # define ONCHIP_NR_IRQS 48 // Actually 44
263 # elif defined(CONFIG_CPU_SUBTYPE_SH7751)
264 # define ONCHIP_NR_IRQS 72
265 # elif defined(CONFIG_CPU_SUBTYPE_SH7760)
266 # define ONCHIP_NR_IRQS 110
267 # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
268 # define ONCHIP_NR_IRQS 144
269 # elif defined(CONFIG_CPU_SUBTYPE_SH7300)
270 # define ONCHIP_NR_IRQS 109
274 /* 2. PINT_NR_IRQS */
275 #ifdef CONFIG_SH_GENERIC
276 # define PINT_NR_IRQS 16
278 # ifndef PINT_NR_IRQS
279 # define PINT_NR_IRQS 0
284 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
287 /* 3. OFFCHIP_NR_IRQS */
288 #ifdef CONFIG_SH_GENERIC
289 # define OFFCHIP_NR_IRQS 16
291 # if defined(CONFIG_HD64461)
292 # define OFFCHIP_NR_IRQS 18
293 # elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
294 # define OFFCHIP_NR_IRQS 48
295 # elif defined(CONFIG_HD64465)
296 # define OFFCHIP_NR_IRQS 16
297 # elif defined (CONFIG_SH_EC3104)
298 # define OFFCHIP_NR_IRQS 16
299 # elif defined (CONFIG_SH_DREAMCAST)
300 # define OFFCHIP_NR_IRQS 96
302 # define OFFCHIP_NR_IRQS 0
306 #if OFFCHIP_NR_IRQS > 0
307 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
311 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
313 /* In a generic kernel, NR_IRQS is an upper bound, and we should use
314 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
316 #ifdef CONFIG_SH_GENERIC
317 # define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
319 # define ACTUAL_NR_IRQS NR_IRQS
323 extern void disable_irq(unsigned int);
324 extern void disable_irq_nosync(unsigned int);
325 extern void enable_irq(unsigned int);
328 * Simple Mask Register Support
330 extern void make_maskreg_irq(unsigned int irq);
331 extern unsigned short *irq_mask_register;
334 * Function for "on chip support modules".
336 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
337 int pos, int priority);
338 extern void make_imask_irq(unsigned int irq);
340 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
343 #define INTC_IPRA 0xA414FEE2UL
344 #define INTC_IPRB 0xA414FEE4UL
345 #define INTC_IPRC 0xA4140016UL
346 #define INTC_IPRD 0xA4140018UL
347 #define INTC_IPRE 0xA414001AUL
348 #define INTC_IPRF 0xA4080000UL
349 #define INTC_IPRG 0xA4080002UL
350 #define INTC_IPRH 0xA4080004UL
351 #define INTC_IPRI 0xA4080006UL
352 #define INTC_IPRJ 0xA4080008UL
354 #define INTC_IMR0 0xA4080040UL
355 #define INTC_IMR1 0xA4080042UL
356 #define INTC_IMR2 0xA4080044UL
357 #define INTC_IMR3 0xA4080046UL
358 #define INTC_IMR4 0xA4080048UL
359 #define INTC_IMR5 0xA408004AUL
360 #define INTC_IMR6 0xA408004CUL
361 #define INTC_IMR7 0xA408004EUL
362 #define INTC_IMR8 0xA4080050UL
363 #define INTC_IMR9 0xA4080052UL
364 #define INTC_IMR10 0xA4080054UL
366 #define INTC_IMCR0 0xA4080060UL
367 #define INTC_IMCR1 0xA4080062UL
368 #define INTC_IMCR2 0xA4080064UL
369 #define INTC_IMCR3 0xA4080066UL
370 #define INTC_IMCR4 0xA4080068UL
371 #define INTC_IMCR5 0xA408006AUL
372 #define INTC_IMCR6 0xA408006CUL
373 #define INTC_IMCR7 0xA408006EUL
374 #define INTC_IMCR8 0xA4080070UL
375 #define INTC_IMCR9 0xA4080072UL
376 #define INTC_IMCR10 0xA4080074UL
378 #define INTC_ICR0 0xA414FEE0UL
379 #define INTC_ICR1 0xA4140010UL
381 #define INTC_IRR0 0xA4140004UL
383 #define PORT_PACR 0xA4050100UL
384 #define PORT_PBCR 0xA4050102UL
385 #define PORT_PCCR 0xA4050104UL
386 #define PORT_PDCR 0xA4050106UL
387 #define PORT_PECR 0xA4050108UL
388 #define PORT_PFCR 0xA405010AUL
389 #define PORT_PGCR 0xA405010CUL
390 #define PORT_PHCR 0xA405010EUL
391 #define PORT_PJCR 0xA4050110UL
392 #define PORT_PKCR 0xA4050112UL
393 #define PORT_PLCR 0xA4050114UL
394 #define PORT_SCPCR 0xA4050116UL
395 #define PORT_PMCR 0xA4050118UL
396 #define PORT_PNCR 0xA405011AUL
397 #define PORT_PQCR 0xA405011CUL
399 #define PORT_PSELA 0xA4050140UL
400 #define PORT_PSELB 0xA4050142UL
401 #define PORT_PSELC 0xA4050144UL
403 #define PORT_HIZCRA 0xA4050146UL
404 #define PORT_HIZCRB 0xA4050148UL
405 #define PORT_DRVCR 0xA4050150UL
407 #define PORT_PADR 0xA4050120UL
408 #define PORT_PBDR 0xA4050122UL
409 #define PORT_PCDR 0xA4050124UL
410 #define PORT_PDDR 0xA4050126UL
411 #define PORT_PEDR 0xA4050128UL
412 #define PORT_PFDR 0xA405012AUL
413 #define PORT_PGDR 0xA405012CUL
414 #define PORT_PHDR 0xA405012EUL
415 #define PORT_PJDR 0xA4050130UL
416 #define PORT_PKDR 0xA4050132UL
417 #define PORT_PLDR 0xA4050134UL
418 #define PORT_SCPDR 0xA4050136UL
419 #define PORT_PMDR 0xA4050138UL
420 #define PORT_PNDR 0xA405013AUL
421 #define PORT_PQDR 0xA405013CUL
430 #define IRQ0_IPR_ADDR INTC_IPRC
431 #define IRQ1_IPR_ADDR INTC_IPRC
432 #define IRQ2_IPR_ADDR INTC_IPRC
433 #define IRQ3_IPR_ADDR INTC_IPRC
434 #define IRQ4_IPR_ADDR INTC_IPRD
435 #define IRQ5_IPR_ADDR INTC_IPRD
437 #define IRQ0_IPR_POS 0
438 #define IRQ1_IPR_POS 1
439 #define IRQ2_IPR_POS 2
440 #define IRQ3_IPR_POS 3
441 #define IRQ4_IPR_POS 0
442 #define IRQ5_IPR_POS 1
444 #define IRQ0_PRIORITY 1
445 #define IRQ1_PRIORITY 1
446 #define IRQ2_PRIORITY 1
447 #define IRQ3_PRIORITY 1
448 #define IRQ4_PRIORITY 1
449 #define IRQ5_PRIORITY 1
451 extern int ipr_irq_demux(int irq);
452 #define __irq_demux(irq) ipr_irq_demux(irq)
454 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
455 #define INTC_IPRA 0xfffffee2UL
456 #define INTC_IPRB 0xfffffe60UL
458 #define INTC_VCRA 0xfffffe62UL
459 #define INTC_VCRB 0xfffffe64UL
460 #define INTC_VCRC 0xfffffe66UL
461 #define INTC_VCRD 0xfffffe68UL
463 #define INTC_VCRWDT 0xfffffee4UL
464 #define INTC_VCRDIV 0xffffff0cUL
465 #define INTC_VCRDMA0 0xffffffa0UL
466 #define INTC_VCRDMA1 0xffffffa8UL
468 #define INTC_ICR 0xfffffee0UL
469 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
470 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
471 defined(CONFIG_CPU_SUBTYPE_SH7709)
472 #define INTC_IRR0 0xa4000004UL
473 #define INTC_IRR1 0xa4000006UL
474 #define INTC_IRR2 0xa4000008UL
476 #define INTC_ICR0 0xfffffee0UL
477 #define INTC_ICR1 0xa4000010UL
478 #define INTC_ICR2 0xa4000012UL
479 #define INTC_INTER 0xa4000014UL
481 #define INTC_IPRC 0xa4000016UL
482 #define INTC_IPRD 0xa4000018UL
483 #define INTC_IPRE 0xa400001aUL
484 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
485 #define INTC_IPRF 0xa400001cUL
486 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
487 #define INTC_IPRF 0xa4080000UL
488 #define INTC_IPRG 0xa4080002UL
489 #define INTC_IPRH 0xa4080004UL
492 #define PORT_PACR 0xa4000100UL
493 #define PORT_PBCR 0xa4000102UL
494 #define PORT_PCCR 0xa4000104UL
495 #define PORT_PFCR 0xa400010aUL
496 #define PORT_PADR 0xa4000120UL
497 #define PORT_PBDR 0xa4000122UL
498 #define PORT_PCDR 0xa4000124UL
499 #define PORT_PFDR 0xa400012aUL
508 #define IRQ0_IPR_ADDR INTC_IPRC
509 #define IRQ1_IPR_ADDR INTC_IPRC
510 #define IRQ2_IPR_ADDR INTC_IPRC
511 #define IRQ3_IPR_ADDR INTC_IPRC
512 #define IRQ4_IPR_ADDR INTC_IPRD
513 #define IRQ5_IPR_ADDR INTC_IPRD
515 #define IRQ0_IPR_POS 0
516 #define IRQ1_IPR_POS 1
517 #define IRQ2_IPR_POS 2
518 #define IRQ3_IPR_POS 3
519 #define IRQ4_IPR_POS 0
520 #define IRQ5_IPR_POS 1
522 #define IRQ0_PRIORITY 1
523 #define IRQ1_PRIORITY 1
524 #define IRQ2_PRIORITY 1
525 #define IRQ3_PRIORITY 1
526 #define IRQ4_PRIORITY 1
527 #define IRQ5_PRIORITY 1
532 #define PINT0_IPR_ADDR INTC_IPRD
533 #define PINT8_IPR_ADDR INTC_IPRD
535 #define PINT0_IPR_POS 3
536 #define PINT8_IPR_POS 2
537 #define PINT0_PRIORITY 2
538 #define PINT8_PRIORITY 2
540 extern int ipr_irq_demux(int irq);
541 #define __irq_demux(irq) ipr_irq_demux(irq)
544 #define __irq_demux(irq) irq
545 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
547 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
548 defined(CONFIG_CPU_SUBTYPE_ST40STB1)
549 #define INTC_ICR 0xffd00000
550 #define INTC_ICR_NMIL (1<<15)
551 #define INTC_ICR_MAI (1<<14)
552 #define INTC_ICR_NMIB (1<<9)
553 #define INTC_ICR_NMIE (1<<8)
554 #define INTC_ICR_IRLM (1<<7)
557 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
558 #define INTC2_FIRST_IRQ 64
559 #define NR_INTC2_IRQS 25
561 #define INTC2_BASE0 0xfe080000
562 #define INTC2_INTC2MODE (INTC2_BASE0+0x80)
564 #define INTC2_INTPRI_OFFSET 0x00
565 #define INTC2_INTREQ_OFFSET 0x20
566 #define INTC2_INTMSK_OFFSET 0x40
567 #define INTC2_INTMSKCLR_OFFSET 0x60
569 extern void make_intc2_irq(unsigned int irq,unsigned int addr,
570 unsigned int group,int pos,int priority);
574 static inline int generic_irq_demux(int irq)
579 #define irq_canonicalize(irq) (irq)
580 #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
584 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
586 #endif /* __ASM_SH_IRQ_H */