1 #ifndef __ASM_SH64_PGTABLE_H
2 #define __ASM_SH64_PGTABLE_H
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * include/asm-sh64/pgtable.h
11 * Copyright (C) 2000, 2001 Paolo Alberelli
12 * Copyright (C) 2003, 2004 Paul Mundt
13 * Copyright (C) 2003, 2004 Richard Curnow
15 * This file contains the functions and defines necessary to modify and use
16 * the SuperH page table tree.
20 #include <asm/processor.h>
22 #include <linux/threads.h>
23 #include <linux/config.h>
25 extern void paging_init(void);
27 /* We provide our own get_unmapped_area to avoid cache synonym issue */
28 #define HAVE_ARCH_UNMAPPED_AREA
31 * Basically we have the same two-level (which is the logical three level
32 * Linux page table layout folded) page tables as the i386.
36 * ZERO_PAGE is a global shared page that is always zero: used
37 * for zero-mapped memory areas etc..
39 extern unsigned char empty_zero_page[PAGE_SIZE];
40 #define ZERO_PAGE(vaddr) (mem_map + MAP_NR(empty_zero_page))
42 #endif /* !__ASSEMBLY__ */
45 * NEFF and NPHYS related defines.
46 * FIXME : These need to be model-dependent. For now this is OK, SH5-101 and SH5-103
47 * implement 32 bits effective and 32 bits physical. But future implementations may
51 #define NEFF_SIGN (1LL << (NEFF - 1))
52 #define NEFF_MASK (-1LL << NEFF)
55 #define NPHYS_SIGN (1LL << (NPHYS - 1))
56 #define NPHYS_MASK (-1LL << NPHYS)
58 /* Typically 2-level is sufficient up to 32 bits of virtual address space, beyond
59 that 3-level would be appropriate. */
60 #if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
61 /* For 4k pages, this contains 512 entries, i.e. 9 bits worth of address. */
62 #define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long))
63 #define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */
64 #define PTE_SHIFT PAGE_SHIFT
65 #define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE)
68 #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
69 #define PGD_BITS (NEFF - PGDIR_SHIFT)
70 #define PTRS_PER_PGD (1<<PGD_BITS)
72 /* middle level: PMD. This doesn't do anything for the 2-level case. */
73 #define PTRS_PER_PMD (1)
75 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
76 #define PGDIR_MASK (~(PGDIR_SIZE-1))
77 #define PMD_SHIFT PGDIR_SHIFT
78 #define PMD_SIZE PGDIR_SIZE
79 #define PMD_MASK PGDIR_MASK
81 #elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
83 * three-level asymmetric paging structure: PGD is top level.
84 * The asymmetry comes from 32-bit pointers and 64-bit PTEs.
86 /* bottom level: PTE. It's 9 bits = 512 pointers */
87 #define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long))
88 #define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */
89 #define PTE_SHIFT PAGE_SHIFT
90 #define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE)
92 /* middle level: PMD. It's 10 bits = 1024 pointers */
93 #define PTRS_PER_PMD ((1<<PAGE_SHIFT)/sizeof(unsigned long long *))
94 #define PMD_MAGNITUDE 2 /* sizeof(unsigned long long *) magnit. */
95 #define PMD_SHIFT (PTE_SHIFT + PTE_BITS)
96 #define PMD_BITS (PAGE_SHIFT - PMD_MAGNITUDE)
98 /* top level: PMD. It's 1 bit = 2 pointers */
99 #define PGDIR_SHIFT (PMD_SHIFT + PMD_BITS)
100 #define PGD_BITS (NEFF - PGDIR_SHIFT)
101 #define PTRS_PER_PGD (1<<PGD_BITS)
103 #define PMD_SIZE (1UL << PMD_SHIFT)
104 #define PMD_MASK (~(PMD_SIZE-1))
105 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
106 #define PGDIR_MASK (~(PGDIR_SIZE-1))
109 #error "No defined number of page table levels"
115 #define pte_ERROR(e) \
116 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
117 #define pmd_ERROR(e) \
118 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
119 #define pgd_ERROR(e) \
120 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
123 * Table setting routines. Used within arch/mm only.
125 #define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
126 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
128 static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
130 unsigned long long x = ((unsigned long long) pteval.pte);
131 unsigned long long *xp = (unsigned long long *) pteptr;
133 * Sign-extend based on NPHYS.
135 *(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x;
138 static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
140 pmd_val(*pmdp) = (unsigned long) ptep;
144 * PGD defines. Top level.
147 /* To find an entry in a generic PGD. */
148 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
149 #define __pgd_offset(address) pgd_index(address)
150 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
152 /* To find an entry in a kernel PGD. */
153 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
156 * PGD level access routines.
159 * There's no need to use physical addresses since the tree walk is all
160 * in performed in software, until the PTE translation.
163 * A PGD entry can be uninitialized (_PGD_UNUSED), generically bad,
164 * clear (_PGD_EMPTY), present. When present, lower 3 nibbles contain
165 * _KERNPG_TABLE. Being a kernel virtual pointer also bit 31 must
166 * be 1. Assuming an arbitrary clear value of bit 31 set to 0 and
167 * lower 3 nibbles set to 0xFFF (_PGD_EMPTY) any other value is a
168 * bad pgd that must be notified via printk().
171 #define _PGD_EMPTY 0x0
173 #if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
174 static inline int pgd_none(pgd_t pgd) { return 0; }
175 static inline int pgd_bad(pgd_t pgd) { return 0; }
176 #define pgd_present(pgd) ((pgd_val(pgd) & _PAGE_PRESENT) ? 1 : 0)
177 #define pgd_clear(xx) do { } while(0)
179 #elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
180 #define pgd_present(pgd_entry) (1)
181 #define pgd_none(pgd_entry) (pgd_val((pgd_entry)) == _PGD_EMPTY)
182 /* TODO: Think later about what a useful definition of 'bad' would be now. */
183 #define pgd_bad(pgd_entry) (0)
184 #define pgd_clear(pgd_entry_p) (set_pgd((pgd_entry_p), __pgd(_PGD_EMPTY)))
189 #define pgd_page(pgd_entry) ((unsigned long) (pgd_val(pgd_entry) & PAGE_MASK))
192 * PMD defines. Middle level.
195 /* PGD to PMD dereferencing */
196 #if defined(CONFIG_SH64_PGTABLE_2_LEVEL)
197 static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
199 return (pmd_t *) dir;
201 #elif defined(CONFIG_SH64_PGTABLE_3_LEVEL)
202 #define __pmd_offset(address) \
203 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
204 #define pmd_offset(dir, addr) \
205 ((pmd_t *) ((pgd_val(*(dir))) & PAGE_MASK) + __pmd_offset((addr)))
209 * PMD level access routines. Same notes as above.
211 #define _PMD_EMPTY 0x0
212 /* Either the PMD is empty or present, it's not paged out */
213 #define pmd_present(pmd_entry) (pmd_val(pmd_entry) & _PAGE_PRESENT)
214 #define pmd_clear(pmd_entry_p) (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY)))
215 #define pmd_none(pmd_entry) (pmd_val((pmd_entry)) == _PMD_EMPTY)
216 #define pmd_bad(pmd_entry) ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
218 #define pmd_page_kernel(pmd_entry) \
219 ((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK))
221 #define pmd_page(pmd) \
222 (virt_to_page(pmd_val(pmd)))
224 /* PMD to PTE dereferencing */
225 #define pte_index(address) \
226 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
228 #define pte_offset_kernel(dir, addr) \
229 ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
231 #define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
232 #define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr)
233 #define pte_unmap(pte) do { } while (0)
234 #define pte_unmap_nested(pte) do { } while (0)
237 #define USER_PTRS_PER_PGD ((TASK_SIZE+PGDIR_SIZE-1)/PGDIR_SIZE)
238 #define FIRST_USER_PGD_NR 0
241 #define VMALLOC_END 0xff000000
242 #define VMALLOC_START 0xf0000000
243 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
245 #define IOBASE_VADDR 0xff000000
246 #define IOBASE_END 0xffffffff
249 * PTEL coherent flags.
250 * See Chapter 17 ST50 CPU Core Volume 1, Architecture.
252 /* The bits that are required in the SH-5 TLB are placed in the h/w-defined
253 positions, to avoid expensive bit shuffling on every refill. The remaining
254 bits are used for s/w purposes and masked out on each refill.
256 Note, the PTE slots are used to hold data of type swp_entry_t when a page is
257 swapped out. Only the _PAGE_PRESENT flag is significant when the page is
258 swapped out, and it must be placed so that it doesn't overlap either the
259 type or offset fields of swp_entry_t. For x86, offset is at [31:8] and type
260 at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t. This
261 scheme doesn't map to SH-5 because bit [0] controls cacheability. So bit
262 [2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split
263 into 2 pieces. That is handled by SWP_ENTRY and SWP_TYPE below. */
264 #define _PAGE_WT 0x001 /* CB0: if cacheable, 1->write-thru, 0->write-back */
265 #define _PAGE_DEVICE 0x001 /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */
266 #define _PAGE_CACHABLE 0x002 /* CB1: uncachable/cachable */
267 #define _PAGE_PRESENT 0x004 /* software: page referenced */
268 #define _PAGE_FILE 0x004 /* software: only when !present */
269 #define _PAGE_SIZE0 0x008 /* SZ0-bit : size of page */
270 #define _PAGE_SIZE1 0x010 /* SZ1-bit : size of page */
271 #define _PAGE_SHARED 0x020 /* software: reflects PTEH's SH */
272 #define _PAGE_READ 0x040 /* PR0-bit : read access allowed */
273 #define _PAGE_EXECUTE 0x080 /* PR1-bit : execute access allowed */
274 #define _PAGE_WRITE 0x100 /* PR2-bit : write access allowed */
275 #define _PAGE_USER 0x200 /* PR3-bit : user space access allowed */
276 #define _PAGE_DIRTY 0x400 /* software: page accessed in write */
277 #define _PAGE_ACCESSED 0x800 /* software: page referenced */
279 /* Mask which drops software flags */
280 #define _PAGE_FLAGS_HARDWARE_MASK 0xfffffffffffff3dbLL
281 /* Flags default: 4KB, Read, Not write, Not execute, Not user */
282 #define _PAGE_FLAGS_HARDWARE_DEFAULT 0x0000000000000040LL
287 #if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
288 #define _PAGE_SZHUGE (_PAGE_SIZE0)
289 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
290 #define _PAGE_SZHUGE (_PAGE_SIZE1)
291 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
292 #define _PAGE_SZHUGE (_PAGE_SIZE0 | _PAGE_SIZE1)
296 * Default flags for a Kernel page.
297 * This is fundametally also SHARED because the main use of this define
298 * (other than for PGD/PMD entries) is for the VMALLOC pool which is
301 * _PAGE_EXECUTE is required for modules
304 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
306 _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \
309 /* Default flags for a User page */
310 #define _PAGE_TABLE (_KERNPG_TABLE | _PAGE_USER)
312 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
314 #define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
315 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
316 _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_USER | \
318 /* We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
319 * protection mode for the stack. */
320 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \
321 _PAGE_ACCESSED | _PAGE_USER | _PAGE_EXECUTE)
322 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \
323 _PAGE_ACCESSED | _PAGE_USER)
324 #define PAGE_KERNEL __pgprot(_KERNPG_TABLE)
328 * In ST50 we have full permissions (Read/Write/Execute/Shared).
329 * Just match'em all. These are for mmap(), therefore all at least
330 * User/Cachable/Present/Accessed. No point in making Fault on Write.
332 #define __MMAP_COMMON (_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED)
334 #define __P000 __pgprot(__MMAP_COMMON)
335 #define __P001 __pgprot(__MMAP_COMMON | _PAGE_READ)
336 #define __P010 __pgprot(__MMAP_COMMON)
337 #define __P011 __pgprot(__MMAP_COMMON | _PAGE_READ)
338 #define __P100 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE)
339 #define __P101 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ)
340 #define __P110 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE)
341 #define __P111 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ)
343 #define __S000 __pgprot(__MMAP_COMMON | _PAGE_SHARED)
344 #define __S001 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ)
345 #define __S010 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_WRITE)
346 #define __S011 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ | _PAGE_WRITE)
347 #define __S100 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE)
348 #define __S101 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ)
349 #define __S110 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_WRITE)
350 #define __S111 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ | _PAGE_WRITE)
352 /* Make it a device mapping for maximum safety (e.g. for mapping device
353 registers into user-space via /dev/map). */
354 #define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE)
355 #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
358 * Handling allocation failures during page table setup.
360 extern void __handle_bad_pmd_kernel(pmd_t * pmd);
361 #define __handle_bad_pmd(x) __handle_bad_pmd_kernel(x)
364 * PTE level access routines.
367 * It's the tree walk leaf. This is physical address to be stored.
370 * Regarding the choice of _PTE_EMPTY:
372 We must choose a bit pattern that cannot be valid, whether or not the page
373 is present. bit[2]==1 => present, bit[2]==0 => swapped out. If swapped
374 out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is
375 left for us to select. If we force bit[7]==0 when swapped out, we could use
376 the combination bit[7,2]=2'b10 to indicate an empty PTE. Alternatively, if
377 we force bit[7]==1 when swapped out, we can use all zeroes to indicate
378 empty. This is convenient, because the page tables get cleared to zero
379 when they are allocated.
382 #define _PTE_EMPTY 0x0
383 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
384 #define pte_clear(xp) (set_pte(xp, __pte(_PTE_EMPTY)))
385 #define pte_none(x) (pte_val(x) == _PTE_EMPTY)
388 * Some definitions to translate between mem_map, PTEs, and page
393 * Given a PTE, return the index of the mem_map[] entry corresponding
394 * to the page frame the PTE. Get the absolute physical address, make
395 * a relative physical address and translate it to an index.
397 #define pte_pagenr(x) (((unsigned long) (pte_val(x)) - \
398 __MEMORY_START) >> PAGE_SHIFT)
401 * Given a PTE, return the "struct page *".
403 #define pte_page(x) (mem_map + pte_pagenr(x))
406 * Return number of (down rounded) MB corresponding to x pages.
408 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
412 * The following have defined behavior only work if pte_present() is true.
414 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
415 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXECUTE; }
416 static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
417 static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
418 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
419 static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_WRITE; }
421 extern inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_READ)); return pte; }
422 extern inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
423 extern inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_EXECUTE)); return pte; }
424 extern inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
425 extern inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
427 extern inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_READ)); return pte; }
428 extern inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; }
429 extern inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_EXECUTE)); return pte; }
430 extern inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
431 extern inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
434 * Conversion functions: convert a page and protection to a page entry.
436 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
438 #define mk_pte(page,pgprot) \
442 set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) | \
443 __MEMORY_START | pgprot_val((pgprot)))); \
448 * This takes a (absolute) physical page address that is used
449 * by the remapping functions
451 #define mk_pte_phys(physpage, pgprot) \
452 ({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; })
454 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
455 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
457 #define page_pte_prot(page, prot) mk_pte(page, prot)
458 #define page_pte(page) page_pte_prot(page, __pgprot(0))
460 typedef pte_t *pte_addr_t;
461 #define pgtable_cache_init() do { } while (0)
463 extern void update_mmu_cache(struct vm_area_struct * vma,
464 unsigned long address, pte_t pte);
466 /* Encode and decode a swap entry */
467 #define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c))
468 #define __swp_offset(x) ((x).val >> 8)
469 #define __swp_entry(type, offset) ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) })
470 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
471 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
473 /* Encode and decode a nonlinear file mapping entry */
474 #define PTE_FILE_MAX_BITS 29
475 #define pte_to_pgoff(pte) (pte_val(pte))
476 #define pgoff_to_pte(off) ((pte_t) { (off) | _PAGE_FILE })
478 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
479 #define PageSkip(page) (0)
480 #define kern_addr_valid(addr) (1)
482 #define io_remap_page_range(vma, vaddr, paddr, size, prot) \
483 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
484 #endif /* !__ASSEMBLY__ */
487 * No page table caches to initialise
489 #define pgtable_cache_init() do { } while (0)
491 #define pte_pfn(x) (((unsigned long)((x).pte)) >> PAGE_SHIFT)
492 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
493 #define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
495 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
497 #include <asm-generic/pgtable.h>
499 #endif /* __ASM_SH64_PGTABLE_H */