2 * ite8172.c -- ITE IT8172G Sound Driver.
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * stevel@mvista.com or source@mvista.com
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Module command line parameters:
32 * /dev/dsp standard OSS /dev/dsp device
33 * /dev/mixer standard OSS /dev/mixer device
37 * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
38 * taken, slightly modified or not at all, from the ES1371 driver,
39 * so refer to the credits in es1371.c for those. The rest of the
40 * code (probe, open, read, write, the ISR, etc.) is new.
41 * 2. The following support is untested:
42 * * Memory mapping the audio buffers, and the ioctl controls that go
46 * 3. The following is not supported:
47 * * legacy audio mode.
48 * 4. Support for volume button interrupts is implemented but doesn't
52 * 02.08.2001 Initial release
53 * 06.22.2001 Added I2S support
54 * 07.30.2003 Removed initialisation to zero for static variables
55 * (spdif[NR_DEVICE], i2s_fmt[NR_DEVICE], and devindex)
57 #include <linux/module.h>
58 #include <linux/string.h>
59 #include <linux/ioport.h>
60 #include <linux/sched.h>
61 #include <linux/delay.h>
62 #include <linux/sound.h>
63 #include <linux/slab.h>
64 #include <linux/soundcard.h>
65 #include <linux/pci.h>
66 #include <linux/init.h>
67 #include <linux/poll.h>
68 #include <linux/bitops.h>
69 #include <linux/proc_fs.h>
70 #include <linux/spinlock.h>
71 #include <linux/smp_lock.h>
72 #include <linux/ac97_codec.h>
73 #include <linux/interrupt.h>
76 #include <asm/uaccess.h>
77 #include <asm/it8172/it8172.h>
79 /* --------------------------------------------------------------------- */
81 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
83 #undef IT8172_VERBOSE_DEBUG
86 #define IT8172_MODULE_NAME "IT8172 audio"
87 #define PFX IT8172_MODULE_NAME
90 #define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
92 #define dbg(format, arg...) do {} while (0)
94 #define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
95 #define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
96 #define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
99 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
103 * Audio Controller register bit definitions follow. See
104 * include/asm/it8172/it8172.h for register offsets.
107 /* PCM Out Volume Reg */
108 #define PCMOV_PCMOM (1<<15) /* PCM Out Mute default 1: mute */
109 #define PCMOV_PCMRCG_BIT 8 /* PCM Right channel Gain */
110 #define PCMOV_PCMRCG_MASK (0x1f<<PCMOV_PCMRCG_BIT)
111 #define PCMOV_PCMLCG_BIT 0 /* PCM Left channel gain */
112 #define PCMOV_PCMLCG_MASK 0x1f
114 /* FM Out Volume Reg */
115 #define FMOV_FMOM (1<<15) /* FM Out Mute default 1: mute */
116 #define FMOV_FMRCG_BIT 8 /* FM Right channel Gain */
117 #define FMOV_FMRCG_MASK (0x1f<<FMOV_FMRCG_BIT)
118 #define FMOV_FMLCG_BIT 0 /* FM Left channel gain */
119 #define FMOV_FMLCG_MASK 0x1f
121 /* I2S Out Volume Reg */
122 #define I2SV_I2SOM (1<<15) /* I2S Out Mute default 1: mute */
123 #define I2SV_I2SRCG_BIT 8 /* I2S Right channel Gain */
124 #define I2SV_I2SRCG_MASK (0x1f<<I2SV_I2SRCG_BIT)
125 #define I2SV_I2SLCG_BIT 0 /* I2S Left channel gain */
126 #define I2SV_I2SLCG_MASK 0x1f
128 /* Digital Recording Source Select Reg */
130 #define DRSS_MASK 0x07
131 #define DRSS_AC97_PRIM 0
135 #define DRSS_AC97_SEC 4
137 /* Playback/Capture Channel Control Registers */
138 #define CC_SM (1<<15) /* Stereo, Mone 0: mono 1: stereo */
139 #define CC_DF (1<<14) /* Data Format 0: 8 bit 1: 16 bit */
140 #define CC_FMT_BIT 14
141 #define CC_FMT_MASK (0x03<<CC_FMT_BIT)
142 #define CC_CF_BIT 12 /* Channel format (Playback only) */
143 #define CC_CF_MASK (0x03<<CC_CF_BIT)
145 #define CC_CF_4 (1<<CC_CF_BIT)
146 #define CC_CF_6 (2<<CC_CF_BIT)
147 #define CC_SR_BIT 8 /* sample Rate */
148 #define CC_SR_MASK (0x0f<<CC_SR_BIT)
150 #define CC_SR_8000 (1<<CC_SR_BIT)
151 #define CC_SR_9600 (2<<CC_SR_BIT)
152 #define CC_SR_11025 (3<<CC_SR_BIT)
153 #define CC_SR_16000 (4<<CC_SR_BIT)
154 #define CC_SR_19200 (5<<CC_SR_BIT)
155 #define CC_SR_22050 (6<<CC_SR_BIT)
156 #define CC_SR_32000 (7<<CC_SR_BIT)
157 #define CC_SR_38400 (8<<CC_SR_BIT)
158 #define CC_SR_44100 (9<<CC_SR_BIT)
159 #define CC_SR_48000 (10<<CC_SR_BIT)
160 #define CC_CSP (1<<7) /* Channel stop
161 * 0: End of Current buffer
162 * 1: Immediately stop when rec stop */
163 #define CC_CP (1<<6) /* Channel pause 0: normal, 1: pause */
164 #define CC_CA (1<<5) /* Channel Action 0: Stop , 1: start */
165 #define CC_CB2L (1<<2) /* Cur. buf. 2 xfr is last 0: No, 1: Yes */
166 #define CC_CB1L (1<<1) /* Cur. buf. 1 xfr is last 0: No, 1: Yes */
167 #define CC_DE 1 /* DFC/DFIFO Data Empty 1: empty, 0: not empty
171 /* Codec Control Reg */
172 #define CODECC_GME (1<<9) /* AC97 GPIO Mode enable */
173 #define CODECC_ATM (1<<8) /* AC97 ATE test mode 0: test 1: normal */
174 #define CODECC_WR (1<<6) /* AC97 Warn reset 1: warm reset , 0: Normal */
175 #define CODECC_CR (1<<5) /* AC97 Cold reset 1: Cold reset , 0: Normal */
178 /* I2S Control Reg */
179 #define I2SMC_SR_BIT 6 /* I2S Sampling rate
180 * 00: 48KHz, 01: 44.1 KHz, 10: 32 32 KHz */
181 #define I2SMC_SR_MASK (0x03<<I2SMC_SR_BIT)
182 #define I2SMC_SR_48000 0
183 #define I2SMC_SR_44100 (1<<I2SMC_SR_BIT)
184 #define I2SMC_SR_32000 (2<<I2SMC_SR_BIT)
185 #define I2SMC_SRSS (1<<5) /* Sample Rate Source Select 1:S/W, 0: H/W */
186 #define I2SMC_I2SF_BIT 0 /* I2S Format */
187 #define I2SMC_I2SF_MASK 0x03
188 #define I2SMC_I2SF_DAC 0
189 #define I2SMC_I2SF_ADC 2
190 #define I2SMC_I2SF_I2S 3
193 /* Volume up, Down, Mute */
194 #define VS_VMP (1<<2) /* Volume mute 1: pushed, 0: not */
195 #define VS_VDP (1<<1) /* Volume Down 1: pushed, 0: not */
196 #define VS_VUP 1 /* Volime Up 1: pushed, 0: not */
198 /* SRC, Mixer test control/DFC status reg */
199 #define SRCS_DPUSC (1<<5) /* DFC Playback underrun Status/clear */
200 #define SRCS_DCOSC (1<<4) /* DFC Capture Overrun Status/clear */
201 #define SRCS_SIS (1<<3) /* SRC input select 1: Mixer, 0: Codec I/F */
202 #define SRCS_CDIS_BIT 0 /* Codec Data Input Select */
203 #define SRCS_CDIS_MASK 0x07
204 #define SRCS_CDIS_MIXER 0
205 #define SRCS_CDIS_PCM 1
206 #define SRCS_CDIS_I2S 2
207 #define SRCS_CDIS_FM 3
208 #define SRCS_CDIS_DFC 4
211 /* Codec Index Reg command Port */
212 #define CIRCP_CID_BIT 10
213 #define CIRCP_CID_MASK (0x03<<CIRCP_CID_BIT)
214 #define CIRCP_CPS (1<<9) /* Command Port Status 0: ready, 1: busy */
215 #define CIRCP_DPVF (1<<8) /* Data Port Valid Flag 0: invalis, 1: valid */
216 #define CIRCP_RWC (1<<7) /* Read/write command */
217 #define CIRCP_CIA_BIT 0
218 #define CIRCP_CIA_MASK 0x007F /* Codec Index Address */
220 /* Test Mode Control/Test group Select Control */
222 /* General Control Reg */
223 #define GC_VDC_BIT 6 /* Volume Division Control */
224 #define GC_VDC_MASK (0x03<<GC_VDC_BIT)
225 #define GC_VDC_NONE 0
226 #define GC_VDC_DIV2 (1<<GC_VDC_BIT)
227 #define GC_VDC_DIV4 (2<<GC_VDC_BIT)
228 #define GC_SOE (1<<2) /* S/PDIF Output enable */
229 #define GC_SWR 1 /* Software warn reset */
231 /* Interrupt mask Control Reg */
232 #define IMC_VCIM (1<<6) /* Volume CNTL interrupt mask */
233 #define IMC_CCIM (1<<1) /* Capture Chan. iterrupt mask */
234 #define IMC_PCIM 1 /* Playback Chan. interrupt mask */
236 /* Interrupt status/clear reg */
237 #define ISC_VCI (1<<6) /* Volume CNTL interrupt 1: clears */
238 #define ISC_CCI (1<<1) /* Capture Chan. interrupt 1: clears */
239 #define ISC_PCI 1 /* Playback Chan. interrupt 1: clears */
242 #define POLL_COUNT 0x5000
245 /* --------------------------------------------------------------------- */
248 * Define DIGITAL1 as the I2S channel, since it is not listed in
251 #define SOUND_MIXER_I2S SOUND_MIXER_DIGITAL1
252 #define SOUND_MASK_I2S SOUND_MASK_DIGITAL1
253 #define SOUND_MIXER_READ_I2S MIXER_READ(SOUND_MIXER_I2S)
254 #define SOUND_MIXER_WRITE_I2S MIXER_WRITE(SOUND_MIXER_I2S)
256 /* --------------------------------------------------------------------- */
258 struct it8172_state {
259 /* list of it8172 devices */
260 struct list_head devs;
262 /* the corresponding pci_dev structure */
265 /* soundcore stuff */
268 /* hardware resources */
275 u8 rev; /* the chip revision */
278 int spdif_volume; /* S/PDIF output is enabled if != -1 */
279 int i2s_volume; /* current I2S out volume, in OSS format */
280 int i2s_recording;/* 1 = recording from I2S, 0 = not */
283 /* debug /proc entry */
284 struct proc_dir_entry *ps;
285 struct proc_dir_entry *ac97_ps;
286 #endif /* IT8172_DEBUG */
288 struct ac97_codec *codec;
290 unsigned short pcc, capcc;
291 unsigned dacrate, adcrate;
294 struct semaphore open_sem;
296 wait_queue_head_t open_wait;
308 unsigned total_bytes;
309 unsigned error; /* over/underrun */
310 wait_queue_head_t wait;
311 /* redundant, but makes calculations easier */
314 unsigned fragsamples;
319 unsigned ossfragshift;
321 unsigned subdivision;
325 /* --------------------------------------------------------------------- */
327 static LIST_HEAD(devs);
329 /* --------------------------------------------------------------------- */
331 static inline unsigned ld2(unsigned int x)
356 /* --------------------------------------------------------------------- */
358 static void it8172_delay(int msec)
366 tmo = jiffies + (msec*HZ)/1000;
368 tmo2 = tmo - jiffies;
371 schedule_timeout(tmo2);
376 static unsigned short
377 get_compat_rate(unsigned* rate)
379 unsigned rate_out = *rate;
382 if (rate_out >= 46050) {
383 sr = CC_SR_48000; rate_out = 48000;
384 } else if (rate_out >= 41250) {
385 sr = CC_SR_44100; rate_out = 44100;
386 } else if (rate_out >= 35200) {
387 sr = CC_SR_38400; rate_out = 38400;
388 } else if (rate_out >= 27025) {
389 sr = CC_SR_32000; rate_out = 32000;
390 } else if (rate_out >= 20625) {
391 sr = CC_SR_22050; rate_out = 22050;
392 } else if (rate_out >= 17600) {
393 sr = CC_SR_19200; rate_out = 19200;
394 } else if (rate_out >= 13513) {
395 sr = CC_SR_16000; rate_out = 16000;
396 } else if (rate_out >= 10313) {
397 sr = CC_SR_11025; rate_out = 11025;
398 } else if (rate_out >= 8800) {
399 sr = CC_SR_9600; rate_out = 9600;
400 } else if (rate_out >= 6750) {
401 sr = CC_SR_8000; rate_out = 8000;
403 sr = CC_SR_5500; rate_out = 5500;
410 static void set_adc_rate(struct it8172_state *s, unsigned rate)
415 sr = get_compat_rate(&rate);
417 spin_lock_irqsave(&s->lock, flags);
418 s->capcc &= ~CC_SR_MASK;
420 outw(s->capcc, s->io+IT_AC_CAPCC);
421 spin_unlock_irqrestore(&s->lock, flags);
427 static void set_dac_rate(struct it8172_state *s, unsigned rate)
432 sr = get_compat_rate(&rate);
434 spin_lock_irqsave(&s->lock, flags);
435 s->pcc &= ~CC_SR_MASK;
437 outw(s->pcc, s->io+IT_AC_PCC);
438 spin_unlock_irqrestore(&s->lock, flags);
444 /* --------------------------------------------------------------------- */
446 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
448 struct it8172_state *s = (struct it8172_state *)codec->private_data;
450 unsigned short circp, data;
453 spin_lock_irqsave(&s->lock, flags);
455 for (i = 0; i < POLL_COUNT; i++)
456 if (!(inw(s->io+IT_AC_CIRCP) & CIRCP_CPS))
459 err("rdcodec: codec ready poll expired!");
461 circp = addr & CIRCP_CIA_MASK;
462 circp |= (codec->id << CIRCP_CID_BIT);
463 circp |= CIRCP_RWC; // read command
464 outw(circp, s->io+IT_AC_CIRCP);
466 /* now wait for the data */
467 for (i = 0; i < POLL_COUNT; i++)
468 if (inw(s->io+IT_AC_CIRCP) & CIRCP_DPVF)
471 err("rdcodec: read poll expired!");
473 data = inw(s->io+IT_AC_CIRDP);
474 spin_unlock_irqrestore(&s->lock, flags);
480 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
482 struct it8172_state *s = (struct it8172_state *)codec->private_data;
484 unsigned short circp;
487 spin_lock_irqsave(&s->lock, flags);
489 for (i = 0; i < POLL_COUNT; i++)
490 if (!(inw(s->io+IT_AC_CIRCP) & CIRCP_CPS))
493 err("wrcodec: codec ready poll expired!");
495 circp = addr & CIRCP_CIA_MASK;
496 circp |= (codec->id << CIRCP_CID_BIT);
497 circp &= ~CIRCP_RWC; // write command
499 outw(data, s->io+IT_AC_CIRDP); // send data first
500 outw(circp, s->io+IT_AC_CIRCP);
502 spin_unlock_irqrestore(&s->lock, flags);
506 static void waitcodec(struct ac97_codec *codec)
510 /* codec_wait is used to wait for a ready state after
514 temp = rdcodec(codec, 0x26);
516 // If power down, power up
519 wrcodec(codec, 0x26, 0);
522 temp = rdcodec(codec, 0x26);
525 // Check if Codec REF,ANL,DAC,ADC ready***/
526 if ((temp & 0x3f0f) != 0x000f) {
527 err("codec reg 26 status (0x%x) not ready!!", temp);
533 /* --------------------------------------------------------------------- */
535 static inline void stop_adc(struct it8172_state *s)
537 struct dmabuf* db = &s->dma_adc;
544 spin_lock_irqsave(&s->lock, flags);
546 s->capcc &= ~(CC_CA | CC_CP | CC_CB2L | CC_CB1L);
548 outw(s->capcc, s->io+IT_AC_CAPCC);
550 // disable capture interrupt
551 imc = inb(s->io+IT_AC_IMC);
552 outb(imc | IMC_CCIM, s->io+IT_AC_IMC);
556 spin_unlock_irqrestore(&s->lock, flags);
559 static inline void stop_dac(struct it8172_state *s)
561 struct dmabuf* db = &s->dma_dac;
568 spin_lock_irqsave(&s->lock, flags);
570 s->pcc &= ~(CC_CA | CC_CP | CC_CB2L | CC_CB1L);
572 outw(s->pcc, s->io+IT_AC_PCC);
574 // disable playback interrupt
575 imc = inb(s->io+IT_AC_IMC);
576 outb(imc | IMC_PCIM, s->io+IT_AC_IMC);
580 spin_unlock_irqrestore(&s->lock, flags);
583 static void start_dac(struct it8172_state *s)
585 struct dmabuf* db = &s->dma_dac;
588 unsigned long buf1, buf2;
593 spin_lock_irqsave(&s->lock, flags);
595 // reset Buffer 1 and 2 pointers to nextOut and nextOut+fragsize
596 buf1 = virt_to_bus(db->nextOut);
597 buf2 = buf1 + db->fragsize;
598 if (buf2 >= db->dmaaddr + db->dmasize)
601 outl(buf1, s->io+IT_AC_PCB1STA);
602 outl(buf2, s->io+IT_AC_PCB2STA);
603 db->curBufPtr = IT_AC_PCB1STA;
605 // enable playback interrupt
606 imc = inb(s->io+IT_AC_IMC);
607 outb(imc & ~IMC_PCIM, s->io+IT_AC_IMC);
609 s->pcc &= ~(CC_CSP | CC_CP | CC_CB2L | CC_CB1L);
611 outw(s->pcc, s->io+IT_AC_PCC);
615 spin_unlock_irqrestore(&s->lock, flags);
618 static void start_adc(struct it8172_state *s)
620 struct dmabuf* db = &s->dma_adc;
623 unsigned long buf1, buf2;
628 spin_lock_irqsave(&s->lock, flags);
630 // reset Buffer 1 and 2 pointers to nextIn and nextIn+fragsize
631 buf1 = virt_to_bus(db->nextIn);
632 buf2 = buf1 + db->fragsize;
633 if (buf2 >= db->dmaaddr + db->dmasize)
636 outl(buf1, s->io+IT_AC_CAPB1STA);
637 outl(buf2, s->io+IT_AC_CAPB2STA);
638 db->curBufPtr = IT_AC_CAPB1STA;
640 // enable capture interrupt
641 imc = inb(s->io+IT_AC_IMC);
642 outb(imc & ~IMC_CCIM, s->io+IT_AC_IMC);
644 s->capcc &= ~(CC_CSP | CC_CP | CC_CB2L | CC_CB1L);
646 outw(s->capcc, s->io+IT_AC_CAPCC);
650 spin_unlock_irqrestore(&s->lock, flags);
653 /* --------------------------------------------------------------------- */
655 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
656 #define DMABUF_MINORDER 1
658 static inline void dealloc_dmabuf(struct it8172_state *s, struct dmabuf *db)
660 struct page *page, *pend;
663 /* undo marking the pages as reserved */
664 pend = virt_to_page(db->rawbuf +
665 (PAGE_SIZE << db->buforder) - 1);
666 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
667 mem_map_unreserve(page);
668 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder,
669 db->rawbuf, db->dmaaddr);
671 db->rawbuf = db->nextIn = db->nextOut = NULL;
672 db->mapped = db->ready = 0;
675 static int prog_dmabuf(struct it8172_state *s, struct dmabuf *db,
676 unsigned rate, unsigned fmt, unsigned reg)
681 struct page *page, *pend;
684 db->ready = db->mapped = 0;
685 for (order = DMABUF_DEFAULTORDER;
686 order >= DMABUF_MINORDER; order--)
688 pci_alloc_consistent(s->dev,
694 db->buforder = order;
695 /* now mark the pages as reserved;
696 otherwise remap_pfn_range doesn't do what we want */
697 pend = virt_to_page(db->rawbuf +
698 (PAGE_SIZE << db->buforder) - 1);
699 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
700 mem_map_reserve(page);
704 db->nextIn = db->nextOut = db->rawbuf;
706 bytepersec = rate << sample_shift[fmt];
707 bufs = PAGE_SIZE << db->buforder;
708 if (db->ossfragshift) {
709 if ((1000 << db->ossfragshift) < bytepersec)
710 db->fragshift = ld2(bytepersec/1000);
712 db->fragshift = db->ossfragshift;
714 db->fragshift = ld2(bytepersec/100/(db->subdivision ?
715 db->subdivision : 1));
716 if (db->fragshift < 3)
719 db->numfrag = bufs >> db->fragshift;
720 while (db->numfrag < 4 && db->fragshift > 3) {
722 db->numfrag = bufs >> db->fragshift;
724 db->fragsize = 1 << db->fragshift;
725 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
726 db->numfrag = db->ossmaxfrags;
727 db->fragsamples = db->fragsize >> sample_shift[fmt];
728 db->dmasize = db->numfrag << db->fragshift;
729 memset(db->rawbuf, (fmt & (CC_DF>>CC_FMT_BIT)) ? 0 : 0x80, bufs);
731 #ifdef IT8172_VERBOSE_DEBUG
732 dbg("rate=%d, fragsize=%d, numfrag=%d, dmasize=%d",
733 rate, db->fragsize, db->numfrag, db->dmasize);
736 // set data length register
737 outw(db->fragsize, s->io+reg+2);
743 static inline int prog_dmabuf_adc(struct it8172_state *s)
746 return prog_dmabuf(s, &s->dma_adc, s->adcrate,
747 (s->capcc & CC_FMT_MASK) >> CC_FMT_BIT,
751 static inline int prog_dmabuf_dac(struct it8172_state *s)
754 return prog_dmabuf(s, &s->dma_dac, s->dacrate,
755 (s->pcc & CC_FMT_MASK) >> CC_FMT_BIT,
760 /* hold spinlock for the following! */
762 static irqreturn_t it8172_interrupt(int irq, void *dev_id, struct pt_regs *regs)
764 struct it8172_state *s = (struct it8172_state *)dev_id;
765 struct dmabuf* dac = &s->dma_dac;
766 struct dmabuf* adc = &s->dma_adc;
767 unsigned char isc, vs;
768 unsigned short vol, mute;
769 unsigned long newptr;
773 isc = inb(s->io+IT_AC_ISC);
775 /* fastpath out, to ease interrupt sharing */
776 if (!(isc & (ISC_VCI | ISC_CCI | ISC_PCI))) {
777 spin_unlock(&s->lock);
781 /* clear audio interrupts first */
782 outb(isc | ISC_VCI | ISC_CCI | ISC_PCI, s->io+IT_AC_ISC);
784 /* handle volume button events (ignore if S/PDIF enabled) */
785 if ((isc & ISC_VCI) && s->spdif_volume == -1) {
786 vs = inb(s->io+IT_AC_VS);
787 outb(0, s->io+IT_AC_VS);
788 vol = inw(s->io+IT_AC_PCMOV);
789 mute = vol & PCMOV_PCMOM;
790 vol &= PCMOV_PCMLCG_MASK;
791 if ((vs & VS_VUP) && vol > 0)
793 if ((vs & VS_VDP) && vol < 0x1f)
795 vol |= (vol << PCMOV_PCMRCG_BIT);
797 vol |= (mute ^ PCMOV_PCMOM);
798 outw(vol, s->io+IT_AC_PCMOV);
801 /* update capture pointers */
803 if (adc->count > adc->dmasize - adc->fragsize) {
804 // Overrun. Stop ADC and log the error
809 newptr = virt_to_bus(adc->nextIn) + 2*adc->fragsize;
810 if (newptr >= adc->dmaaddr + adc->dmasize)
811 newptr -= adc->dmasize;
813 outl(newptr, s->io+adc->curBufPtr);
814 adc->curBufPtr = (adc->curBufPtr == IT_AC_CAPB1STA) ?
815 IT_AC_CAPB2STA : IT_AC_CAPB1STA;
817 adc->nextIn += adc->fragsize;
818 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
819 adc->nextIn -= adc->dmasize;
821 adc->count += adc->fragsize;
822 adc->total_bytes += adc->fragsize;
824 /* wake up anybody listening */
825 if (waitqueue_active(&adc->wait))
826 wake_up_interruptible(&adc->wait);
830 /* update playback pointers */
832 newptr = virt_to_bus(dac->nextOut) + 2*dac->fragsize;
833 if (newptr >= dac->dmaaddr + dac->dmasize)
834 newptr -= dac->dmasize;
836 outl(newptr, s->io+dac->curBufPtr);
837 dac->curBufPtr = (dac->curBufPtr == IT_AC_PCB1STA) ?
838 IT_AC_PCB2STA : IT_AC_PCB1STA;
840 dac->nextOut += dac->fragsize;
841 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
842 dac->nextOut -= dac->dmasize;
844 dac->count -= dac->fragsize;
845 dac->total_bytes += dac->fragsize;
847 /* wake up anybody listening */
848 if (waitqueue_active(&dac->wait))
849 wake_up_interruptible(&dac->wait);
855 spin_unlock(&s->lock);
859 /* --------------------------------------------------------------------- */
861 static loff_t it8172_llseek(struct file *file, loff_t offset, int origin)
867 static int it8172_open_mixdev(struct inode *inode, struct file *file)
869 int minor = iminor(inode);
870 struct list_head *list;
871 struct it8172_state *s;
873 for (list = devs.next; ; list = list->next) {
876 s = list_entry(list, struct it8172_state, devs);
877 if (s->codec->dev_mixer == minor)
880 file->private_data = s;
881 return nonseekable_open(inode, file);
884 static int it8172_release_mixdev(struct inode *inode, struct file *file)
891 cvt_ossvol(unsigned int gain)
901 ret = (100 - gain + 32) / 4;
902 ret = ret > 31 ? 31 : ret;
907 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
910 struct it8172_state *s = (struct it8172_state *)codec->private_data;
911 unsigned int left, right;
917 * When we are in S/PDIF mode, we want to disable any analog output so
918 * we filter the master/PCM channel volume ioctls.
920 * Also filter I2S channel, which AC'97 knows nothing about.
924 case SOUND_MIXER_WRITE_VOLUME:
925 // if not in S/PDIF mode, pass to AC'97
926 if (s->spdif_volume == -1)
929 case SOUND_MIXER_WRITE_PCM:
930 // if not in S/PDIF mode, pass to AC'97
931 if (s->spdif_volume == -1)
933 if (get_user(val, (int *)arg))
935 right = ((val >> 8) & 0xff);
941 s->spdif_volume = (right << 8) | left;
942 vol = cvt_ossvol(left);
943 vol |= (cvt_ossvol(right) << PCMOV_PCMRCG_BIT);
945 vol = PCMOV_PCMOM; // mute
946 spin_lock_irqsave(&s->lock, flags);
947 outw(vol, s->io+IT_AC_PCMOV);
948 spin_unlock_irqrestore(&s->lock, flags);
949 return put_user(s->spdif_volume, (int *)arg);
950 case SOUND_MIXER_READ_PCM:
951 // if not in S/PDIF mode, pass to AC'97
952 if (s->spdif_volume == -1)
954 return put_user(s->spdif_volume, (int *)arg);
955 case SOUND_MIXER_WRITE_I2S:
956 if (get_user(val, (int *)arg))
958 right = ((val >> 8) & 0xff);
964 s->i2s_volume = (right << 8) | left;
965 vol = cvt_ossvol(left);
966 vol |= (cvt_ossvol(right) << I2SV_I2SRCG_BIT);
968 vol = I2SV_I2SOM; // mute
969 outw(vol, s->io+IT_AC_I2SV);
970 return put_user(s->i2s_volume, (int *)arg);
971 case SOUND_MIXER_READ_I2S:
972 return put_user(s->i2s_volume, (int *)arg);
973 case SOUND_MIXER_WRITE_RECSRC:
974 if (get_user(val, (int *)arg))
976 if (val & SOUND_MASK_I2S) {
977 s->i2s_recording = 1;
978 outb(DRSS_I2S, s->io+IT_AC_DRSS);
981 s->i2s_recording = 0;
982 outb(DRSS_AC97_PRIM, s->io+IT_AC_DRSS);
983 // now let AC'97 select record source
986 case SOUND_MIXER_READ_RECSRC:
987 if (s->i2s_recording)
988 return put_user(SOUND_MASK_I2S, (int *)arg);
990 // let AC'97 report recording source
994 return codec->mixer_ioctl(codec, cmd, arg);
997 static int it8172_ioctl_mixdev(struct inode *inode, struct file *file,
998 unsigned int cmd, unsigned long arg)
1000 struct it8172_state *s = (struct it8172_state *)file->private_data;
1001 struct ac97_codec *codec = s->codec;
1003 return mixdev_ioctl(codec, cmd, arg);
1006 static /*const*/ struct file_operations it8172_mixer_fops = {
1007 .owner = THIS_MODULE,
1008 .llseek = it8172_llseek,
1009 .ioctl = it8172_ioctl_mixdev,
1010 .open = it8172_open_mixdev,
1011 .release = it8172_release_mixdev,
1014 /* --------------------------------------------------------------------- */
1016 static int drain_dac(struct it8172_state *s, int nonblock)
1018 unsigned long flags;
1021 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
1025 spin_lock_irqsave(&s->lock, flags);
1026 count = s->dma_dac.count;
1027 spin_unlock_irqrestore(&s->lock, flags);
1030 if (signal_pending(current))
1034 tmo = 1000 * count / s->dacrate;
1035 tmo >>= sample_shift[(s->pcc & CC_FMT_MASK) >> CC_FMT_BIT];
1038 if (signal_pending(current))
1039 return -ERESTARTSYS;
1043 /* --------------------------------------------------------------------- */
1047 * Copy audio data to/from user buffer from/to dma buffer, taking care
1048 * that we wrap when reading/writing the dma buffer. Returns actual byte
1049 * count written to or read from the dma buffer.
1051 static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
1052 int count, int to_user)
1054 char* bufptr = to_user ? db->nextOut : db->nextIn;
1055 char* bufend = db->rawbuf + db->dmasize;
1057 if (bufptr + count > bufend) {
1058 int partial = (int)(bufend - bufptr);
1060 if (copy_to_user(userbuf, bufptr, partial))
1062 if (copy_to_user(userbuf + partial, db->rawbuf,
1066 if (copy_from_user(bufptr, userbuf, partial))
1068 if (copy_from_user(db->rawbuf,
1075 if (copy_to_user(userbuf, bufptr, count))
1078 if (copy_from_user(bufptr, userbuf, count))
1087 static ssize_t it8172_read(struct file *file, char *buffer,
1088 size_t count, loff_t *ppos)
1090 struct it8172_state *s = (struct it8172_state *)file->private_data;
1091 struct dmabuf *db = &s->dma_adc;
1093 unsigned long flags;
1094 int cnt, remainder, avail;
1098 if (!access_ok(VERIFY_WRITE, buffer, count))
1103 // wait for samples in capture buffer
1105 spin_lock_irqsave(&s->lock, flags);
1109 spin_unlock_irqrestore(&s->lock, flags);
1111 if (file->f_flags & O_NONBLOCK) {
1116 interruptible_sleep_on(&db->wait);
1117 if (signal_pending(current)) {
1123 } while (avail <= 0);
1125 // copy from nextOut to user
1126 if ((cnt = copy_dmabuf_user(db, buffer, count > avail ?
1127 avail : count, 1)) < 0) {
1133 spin_lock_irqsave(&s->lock, flags);
1135 spin_unlock_irqrestore(&s->lock, flags);
1138 if (db->nextOut >= db->rawbuf + db->dmasize)
1139 db->nextOut -= db->dmasize;
1144 } // while (count > 0)
1147 * See if the dma buffer count after this read call is
1148 * aligned on a fragsize boundary. If not, read from
1149 * buffer until we reach a boundary, and let's hope this
1150 * is just the last remainder of an audio record. If not
1151 * it means the user is not reading in fragsize chunks, in
1152 * which case it's his/her fault that there are audio gaps
1155 spin_lock_irqsave(&s->lock, flags);
1156 remainder = db->count % db->fragsize;
1158 db->nextOut += remainder;
1159 if (db->nextOut >= db->rawbuf + db->dmasize)
1160 db->nextOut -= db->dmasize;
1161 db->count -= remainder;
1163 spin_unlock_irqrestore(&s->lock, flags);
1168 static ssize_t it8172_write(struct file *file, const char *buffer,
1169 size_t count, loff_t *ppos)
1171 struct it8172_state *s = (struct it8172_state *)file->private_data;
1172 struct dmabuf *db = &s->dma_dac;
1174 unsigned long flags;
1175 int cnt, remainder, avail;
1179 if (!access_ok(VERIFY_READ, buffer, count))
1184 // wait for space in playback buffer
1186 spin_lock_irqsave(&s->lock, flags);
1187 avail = db->dmasize - db->count;
1188 spin_unlock_irqrestore(&s->lock, flags);
1190 if (file->f_flags & O_NONBLOCK) {
1195 interruptible_sleep_on(&db->wait);
1196 if (signal_pending(current)) {
1202 } while (avail <= 0);
1205 if ((cnt = copy_dmabuf_user(db, (char*)buffer,
1207 avail : count, 0)) < 0) {
1213 spin_lock_irqsave(&s->lock, flags);
1217 spin_unlock_irqrestore(&s->lock, flags);
1220 if (db->nextIn >= db->rawbuf + db->dmasize)
1221 db->nextIn -= db->dmasize;
1226 } // while (count > 0)
1229 * See if the dma buffer count after this write call is
1230 * aligned on a fragsize boundary. If not, fill buffer
1231 * with silence to the next boundary, and let's hope this
1232 * is just the last remainder of an audio playback. If not
1233 * it means the user is not sending us fragsize chunks, in
1234 * which case it's his/her fault that there are audio gaps
1235 * in their playback.
1237 spin_lock_irqsave(&s->lock, flags);
1238 remainder = db->count % db->fragsize;
1240 int fill_cnt = db->fragsize - remainder;
1241 memset(db->nextIn, 0, fill_cnt);
1242 db->nextIn += fill_cnt;
1243 if (db->nextIn >= db->rawbuf + db->dmasize)
1244 db->nextIn -= db->dmasize;
1245 db->count += fill_cnt;
1247 spin_unlock_irqrestore(&s->lock, flags);
1252 /* No kernel lock - we have our own spinlock */
1253 static unsigned int it8172_poll(struct file *file,
1254 struct poll_table_struct *wait)
1256 struct it8172_state *s = (struct it8172_state *)file->private_data;
1257 unsigned long flags;
1258 unsigned int mask = 0;
1260 if (file->f_mode & FMODE_WRITE) {
1261 if (!s->dma_dac.ready)
1263 poll_wait(file, &s->dma_dac.wait, wait);
1265 if (file->f_mode & FMODE_READ) {
1266 if (!s->dma_adc.ready)
1268 poll_wait(file, &s->dma_adc.wait, wait);
1271 spin_lock_irqsave(&s->lock, flags);
1272 if (file->f_mode & FMODE_READ) {
1273 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1274 mask |= POLLIN | POLLRDNORM;
1276 if (file->f_mode & FMODE_WRITE) {
1277 if (s->dma_dac.mapped) {
1278 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1279 mask |= POLLOUT | POLLWRNORM;
1281 if ((signed)s->dma_dac.dmasize >=
1282 s->dma_dac.count + (signed)s->dma_dac.fragsize)
1283 mask |= POLLOUT | POLLWRNORM;
1286 spin_unlock_irqrestore(&s->lock, flags);
1290 static int it8172_mmap(struct file *file, struct vm_area_struct *vma)
1292 struct it8172_state *s = (struct it8172_state *)file->private_data;
1297 if (vma->vm_flags & VM_WRITE)
1299 else if (vma->vm_flags & VM_READ)
1305 if (vma->vm_pgoff != 0) {
1309 size = vma->vm_end - vma->vm_start;
1310 if (size > (PAGE_SIZE << db->buforder)) {
1314 if (remap_pfn_range(vma, vma->vm_start,
1315 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1316 size, vma->vm_page_prot)) {
1326 #ifdef IT8172_VERBOSE_DEBUG
1327 static struct ioctl_str_t {
1331 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1332 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1333 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1334 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1335 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1336 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1337 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1338 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1339 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1340 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1341 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1342 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1343 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1344 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1345 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1346 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1347 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1348 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1349 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1350 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1351 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1352 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1353 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1354 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1355 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1356 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1357 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1358 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1359 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1360 {OSS_GETVERSION, "OSS_GETVERSION"},
1361 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1362 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1363 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1364 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1368 static int it8172_ioctl(struct inode *inode, struct file *file,
1369 unsigned int cmd, unsigned long arg)
1371 struct it8172_state *s = (struct it8172_state *)file->private_data;
1372 unsigned long flags;
1373 audio_buf_info abinfo;
1376 int val, mapped, ret, diff;
1378 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1379 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1381 #ifdef IT8172_VERBOSE_DEBUG
1382 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1383 if (ioctl_str[count].cmd == cmd)
1386 if (count < sizeof(ioctl_str)/sizeof(ioctl_str[0]))
1387 dbg("ioctl %s, arg=0x%08x",
1388 ioctl_str[count].str, (unsigned int)arg);
1390 dbg("ioctl unknown, 0x%x", cmd);
1394 case OSS_GETVERSION:
1395 return put_user(SOUND_VERSION, (int *)arg);
1397 case SNDCTL_DSP_SYNC:
1398 if (file->f_mode & FMODE_WRITE)
1399 return drain_dac(s, file->f_flags & O_NONBLOCK);
1402 case SNDCTL_DSP_SETDUPLEX:
1405 case SNDCTL_DSP_GETCAPS:
1406 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1407 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1409 case SNDCTL_DSP_RESET:
1410 if (file->f_mode & FMODE_WRITE) {
1413 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1414 s->dma_dac.nextIn = s->dma_dac.nextOut =
1417 if (file->f_mode & FMODE_READ) {
1420 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1421 s->dma_adc.nextIn = s->dma_adc.nextOut =
1426 case SNDCTL_DSP_SPEED:
1427 if (get_user(val, (int *)arg))
1430 if (file->f_mode & FMODE_READ) {
1432 set_adc_rate(s, val);
1433 if ((ret = prog_dmabuf_adc(s)))
1436 if (file->f_mode & FMODE_WRITE) {
1438 set_dac_rate(s, val);
1439 if ((ret = prog_dmabuf_dac(s)))
1443 return put_user((file->f_mode & FMODE_READ) ?
1444 s->adcrate : s->dacrate, (int *)arg);
1446 case SNDCTL_DSP_STEREO:
1447 if (get_user(val, (int *)arg))
1449 if (file->f_mode & FMODE_READ) {
1455 outw(s->capcc, s->io+IT_AC_CAPCC);
1456 if ((ret = prog_dmabuf_adc(s)))
1459 if (file->f_mode & FMODE_WRITE) {
1465 outw(s->pcc, s->io+IT_AC_PCC);
1466 if ((ret = prog_dmabuf_dac(s)))
1471 case SNDCTL_DSP_CHANNELS:
1472 if (get_user(val, (int *)arg))
1475 if (file->f_mode & FMODE_READ) {
1483 outw(s->capcc, s->io+IT_AC_CAPCC);
1484 if ((ret = prog_dmabuf_adc(s)))
1487 if (file->f_mode & FMODE_WRITE) {
1497 // FIX! support multichannel???
1502 outw(s->pcc, s->io+IT_AC_PCC);
1503 if ((ret = prog_dmabuf_dac(s)))
1507 return put_user(val, (int *)arg);
1509 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1510 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1512 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1513 if (get_user(val, (int *)arg))
1515 if (val != AFMT_QUERY) {
1516 if (file->f_mode & FMODE_READ) {
1518 if (val == AFMT_S16_LE)
1524 outw(s->capcc, s->io+IT_AC_CAPCC);
1525 if ((ret = prog_dmabuf_adc(s)))
1528 if (file->f_mode & FMODE_WRITE) {
1530 if (val == AFMT_S16_LE)
1536 outw(s->pcc, s->io+IT_AC_PCC);
1537 if ((ret = prog_dmabuf_dac(s)))
1541 if (file->f_mode & FMODE_READ)
1542 val = (s->capcc & CC_DF) ?
1543 AFMT_S16_LE : AFMT_U8;
1545 val = (s->pcc & CC_DF) ?
1546 AFMT_S16_LE : AFMT_U8;
1548 return put_user(val, (int *)arg);
1550 case SNDCTL_DSP_POST:
1553 case SNDCTL_DSP_GETTRIGGER:
1555 spin_lock_irqsave(&s->lock, flags);
1556 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1557 val |= PCM_ENABLE_INPUT;
1558 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1559 val |= PCM_ENABLE_OUTPUT;
1560 spin_unlock_irqrestore(&s->lock, flags);
1561 return put_user(val, (int *)arg);
1563 case SNDCTL_DSP_SETTRIGGER:
1564 if (get_user(val, (int *)arg))
1566 if (file->f_mode & FMODE_READ) {
1567 if (val & PCM_ENABLE_INPUT)
1572 if (file->f_mode & FMODE_WRITE) {
1573 if (val & PCM_ENABLE_OUTPUT)
1580 case SNDCTL_DSP_GETOSPACE:
1581 if (!(file->f_mode & FMODE_WRITE))
1583 abinfo.fragsize = s->dma_dac.fragsize;
1584 spin_lock_irqsave(&s->lock, flags);
1585 count = s->dma_dac.count;
1586 if (!s->dma_dac.stopped)
1587 count -= (s->dma_dac.fragsize -
1588 inw(s->io+IT_AC_PCDL));
1589 spin_unlock_irqrestore(&s->lock, flags);
1592 abinfo.bytes = s->dma_dac.dmasize - count;
1593 abinfo.fragstotal = s->dma_dac.numfrag;
1594 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1595 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ?
1598 case SNDCTL_DSP_GETISPACE:
1599 if (!(file->f_mode & FMODE_READ))
1601 abinfo.fragsize = s->dma_adc.fragsize;
1602 spin_lock_irqsave(&s->lock, flags);
1603 count = s->dma_adc.count;
1604 if (!s->dma_adc.stopped)
1605 count += (s->dma_adc.fragsize -
1606 inw(s->io+IT_AC_CAPCDL));
1607 spin_unlock_irqrestore(&s->lock, flags);
1610 abinfo.bytes = count;
1611 abinfo.fragstotal = s->dma_adc.numfrag;
1612 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1613 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ?
1616 case SNDCTL_DSP_NONBLOCK:
1617 file->f_flags |= O_NONBLOCK;
1620 case SNDCTL_DSP_GETODELAY:
1621 if (!(file->f_mode & FMODE_WRITE))
1623 spin_lock_irqsave(&s->lock, flags);
1624 count = s->dma_dac.count;
1625 if (!s->dma_dac.stopped)
1626 count -= (s->dma_dac.fragsize -
1627 inw(s->io+IT_AC_PCDL));
1628 spin_unlock_irqrestore(&s->lock, flags);
1631 return put_user(count, (int *)arg);
1633 case SNDCTL_DSP_GETIPTR:
1634 if (!(file->f_mode & FMODE_READ))
1636 spin_lock_irqsave(&s->lock, flags);
1637 cinfo.bytes = s->dma_adc.total_bytes;
1638 count = s->dma_adc.count;
1639 if (!s->dma_adc.stopped) {
1640 diff = s->dma_adc.fragsize - inw(s->io+IT_AC_CAPCDL);
1642 cinfo.bytes += diff;
1643 cinfo.ptr = inl(s->io+s->dma_adc.curBufPtr) -
1646 cinfo.ptr = virt_to_bus(s->dma_adc.nextIn) -
1648 if (s->dma_adc.mapped)
1649 s->dma_adc.count &= s->dma_adc.fragsize-1;
1650 spin_unlock_irqrestore(&s->lock, flags);
1653 cinfo.blocks = count >> s->dma_adc.fragshift;
1654 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
1656 case SNDCTL_DSP_GETOPTR:
1657 if (!(file->f_mode & FMODE_READ))
1659 spin_lock_irqsave(&s->lock, flags);
1660 cinfo.bytes = s->dma_dac.total_bytes;
1661 count = s->dma_dac.count;
1662 if (!s->dma_dac.stopped) {
1663 diff = s->dma_dac.fragsize - inw(s->io+IT_AC_CAPCDL);
1665 cinfo.bytes += diff;
1666 cinfo.ptr = inl(s->io+s->dma_dac.curBufPtr) -
1669 cinfo.ptr = virt_to_bus(s->dma_dac.nextOut) -
1671 if (s->dma_dac.mapped)
1672 s->dma_dac.count &= s->dma_dac.fragsize-1;
1673 spin_unlock_irqrestore(&s->lock, flags);
1676 cinfo.blocks = count >> s->dma_dac.fragshift;
1677 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
1679 case SNDCTL_DSP_GETBLKSIZE:
1680 if (file->f_mode & FMODE_WRITE)
1681 return put_user(s->dma_dac.fragsize, (int *)arg);
1683 return put_user(s->dma_adc.fragsize, (int *)arg);
1685 case SNDCTL_DSP_SETFRAGMENT:
1686 if (get_user(val, (int *)arg))
1688 if (file->f_mode & FMODE_READ) {
1690 s->dma_adc.ossfragshift = val & 0xffff;
1691 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1692 if (s->dma_adc.ossfragshift < 4)
1693 s->dma_adc.ossfragshift = 4;
1694 if (s->dma_adc.ossfragshift > 15)
1695 s->dma_adc.ossfragshift = 15;
1696 if (s->dma_adc.ossmaxfrags < 4)
1697 s->dma_adc.ossmaxfrags = 4;
1698 if ((ret = prog_dmabuf_adc(s)))
1701 if (file->f_mode & FMODE_WRITE) {
1703 s->dma_dac.ossfragshift = val & 0xffff;
1704 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1705 if (s->dma_dac.ossfragshift < 4)
1706 s->dma_dac.ossfragshift = 4;
1707 if (s->dma_dac.ossfragshift > 15)
1708 s->dma_dac.ossfragshift = 15;
1709 if (s->dma_dac.ossmaxfrags < 4)
1710 s->dma_dac.ossmaxfrags = 4;
1711 if ((ret = prog_dmabuf_dac(s)))
1716 case SNDCTL_DSP_SUBDIVIDE:
1717 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1718 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1720 if (get_user(val, (int *)arg))
1722 if (val != 1 && val != 2 && val != 4)
1724 if (file->f_mode & FMODE_READ) {
1726 s->dma_adc.subdivision = val;
1727 if ((ret = prog_dmabuf_adc(s)))
1730 if (file->f_mode & FMODE_WRITE) {
1732 s->dma_dac.subdivision = val;
1733 if ((ret = prog_dmabuf_dac(s)))
1738 case SOUND_PCM_READ_RATE:
1739 return put_user((file->f_mode & FMODE_READ) ?
1740 s->adcrate : s->dacrate, (int *)arg);
1742 case SOUND_PCM_READ_CHANNELS:
1743 if (file->f_mode & FMODE_READ)
1744 return put_user((s->capcc & CC_SM) ? 2 : 1,
1747 return put_user((s->pcc & CC_SM) ? 2 : 1,
1750 case SOUND_PCM_READ_BITS:
1751 if (file->f_mode & FMODE_READ)
1752 return put_user((s->capcc & CC_DF) ? 16 : 8,
1755 return put_user((s->pcc & CC_DF) ? 16 : 8,
1758 case SOUND_PCM_WRITE_FILTER:
1759 case SNDCTL_DSP_SETSYNCRO:
1760 case SOUND_PCM_READ_FILTER:
1764 return mixdev_ioctl(s->codec, cmd, arg);
1768 static int it8172_open(struct inode *inode, struct file *file)
1770 int minor = iminor(inode);
1771 DECLARE_WAITQUEUE(wait, current);
1772 unsigned long flags;
1773 struct list_head *list;
1774 struct it8172_state *s;
1777 #ifdef IT8172_VERBOSE_DEBUG
1778 if (file->f_flags & O_NONBLOCK)
1779 dbg("%s: non-blocking", __FUNCTION__);
1781 dbg("%s: blocking", __FUNCTION__);
1784 for (list = devs.next; ; list = list->next) {
1787 s = list_entry(list, struct it8172_state, devs);
1788 if (!((s->dev_audio ^ minor) & ~0xf))
1791 file->private_data = s;
1792 /* wait for device to become free */
1794 while (s->open_mode & file->f_mode) {
1795 if (file->f_flags & O_NONBLOCK) {
1799 add_wait_queue(&s->open_wait, &wait);
1800 __set_current_state(TASK_INTERRUPTIBLE);
1803 remove_wait_queue(&s->open_wait, &wait);
1804 set_current_state(TASK_RUNNING);
1805 if (signal_pending(current))
1806 return -ERESTARTSYS;
1810 spin_lock_irqsave(&s->lock, flags);
1812 if (file->f_mode & FMODE_READ) {
1813 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1814 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1815 s->capcc &= ~(CC_SM | CC_DF);
1816 set_adc_rate(s, 8000);
1817 if ((minor & 0xf) == SND_DEV_DSP16)
1819 outw(s->capcc, s->io+IT_AC_CAPCC);
1820 if ((ret = prog_dmabuf_adc(s))) {
1821 spin_unlock_irqrestore(&s->lock, flags);
1825 if (file->f_mode & FMODE_WRITE) {
1826 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1827 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1828 s->pcc &= ~(CC_SM | CC_DF);
1829 set_dac_rate(s, 8000);
1830 if ((minor & 0xf) == SND_DEV_DSP16)
1832 outw(s->pcc, s->io+IT_AC_PCC);
1833 if ((ret = prog_dmabuf_dac(s))) {
1834 spin_unlock_irqrestore(&s->lock, flags);
1839 spin_unlock_irqrestore(&s->lock, flags);
1841 s->open_mode |= (file->f_mode & (FMODE_READ | FMODE_WRITE));
1843 return nonseekable_open(inode, file);
1846 static int it8172_release(struct inode *inode, struct file *file)
1848 struct it8172_state *s = (struct it8172_state *)file->private_data;
1850 #ifdef IT8172_VERBOSE_DEBUG
1854 if (file->f_mode & FMODE_WRITE)
1855 drain_dac(s, file->f_flags & O_NONBLOCK);
1857 if (file->f_mode & FMODE_WRITE) {
1859 dealloc_dmabuf(s, &s->dma_dac);
1861 if (file->f_mode & FMODE_READ) {
1863 dealloc_dmabuf(s, &s->dma_adc);
1865 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1867 wake_up(&s->open_wait);
1872 static /*const*/ struct file_operations it8172_audio_fops = {
1873 .owner = THIS_MODULE,
1874 .llseek = it8172_llseek,
1875 .read = it8172_read,
1876 .write = it8172_write,
1877 .poll = it8172_poll,
1878 .ioctl = it8172_ioctl,
1879 .mmap = it8172_mmap,
1880 .open = it8172_open,
1881 .release = it8172_release,
1885 /* --------------------------------------------------------------------- */
1888 /* --------------------------------------------------------------------- */
1891 * for debugging purposes, we'll create a proc device that dumps the
1896 static int proc_it8172_dump (char *buf, char **start, off_t fpos,
1897 int length, int *eof, void *data)
1899 struct it8172_state *s;
1902 if (list_empty(&devs))
1904 s = list_entry(devs.next, struct it8172_state, devs);
1906 /* print out header */
1907 len += sprintf(buf + len, "\n\t\tIT8172 Audio Debug\n\n");
1909 // print out digital controller state
1910 len += sprintf (buf + len, "IT8172 Audio Controller registers\n");
1911 len += sprintf (buf + len, "---------------------------------\n");
1913 while (cnt < 0x72) {
1914 if (cnt == IT_AC_PCB1STA || cnt == IT_AC_PCB2STA ||
1915 cnt == IT_AC_CAPB1STA || cnt == IT_AC_CAPB2STA ||
1916 cnt == IT_AC_PFDP) {
1917 len+= sprintf (buf + len, "reg %02x = %08x\n",
1918 cnt, inl(s->io+cnt));
1921 len+= sprintf (buf + len, "reg %02x = %04x\n",
1922 cnt, inw(s->io+cnt));
1927 /* print out CODEC state */
1928 len += sprintf (buf + len, "\nAC97 CODEC registers\n");
1929 len += sprintf (buf + len, "----------------------\n");
1930 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
1931 len+= sprintf (buf + len, "reg %02x = %04x\n",
1932 cnt, rdcodec(s->codec, cnt));
1939 *start = buf + fpos;
1940 if ((len -= fpos) > length)
1946 #endif /* IT8172_DEBUG */
1948 /* --------------------------------------------------------------------- */
1950 /* maximum number of devices; only used for command line params */
1953 static int spdif[NR_DEVICE];
1954 static int i2s_fmt[NR_DEVICE];
1956 static unsigned int devindex;
1958 MODULE_PARM(spdif, "1-" __MODULE_STRING(NR_DEVICE) "i");
1959 MODULE_PARM_DESC(spdif, "if 1 the S/PDIF digital output is enabled");
1960 MODULE_PARM(i2s_fmt, "1-" __MODULE_STRING(NR_DEVICE) "i");
1961 MODULE_PARM_DESC(i2s_fmt, "the format of I2S");
1963 MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
1964 MODULE_DESCRIPTION("IT8172 Audio Driver");
1966 /* --------------------------------------------------------------------- */
1968 static int __devinit it8172_probe(struct pci_dev *pcidev,
1969 const struct pci_device_id *pciid)
1971 struct it8172_state *s;
1973 unsigned short pcisr, vol;
1974 unsigned char legacy, imc;
1977 if (pcidev->irq == 0)
1980 if (!(s = kmalloc(sizeof(struct it8172_state), GFP_KERNEL))) {
1981 err("alloc of device struct failed");
1985 memset(s, 0, sizeof(struct it8172_state));
1986 init_waitqueue_head(&s->dma_adc.wait);
1987 init_waitqueue_head(&s->dma_dac.wait);
1988 init_waitqueue_head(&s->open_wait);
1989 init_MUTEX(&s->open_sem);
1990 spin_lock_init(&s->lock);
1992 s->io = pci_resource_start(pcidev, 0);
1993 s->irq = pcidev->irq;
1994 s->vendor = pcidev->vendor;
1995 s->device = pcidev->device;
1996 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
1998 s->codec = ac97_alloc_codec();
1999 if(s->codec == NULL)
2002 s->codec->private_data = s;
2004 s->codec->codec_read = rdcodec;
2005 s->codec->codec_write = wrcodec;
2006 s->codec->codec_wait = waitcodec;
2008 if (!request_region(s->io, pci_resource_len(pcidev,0),
2009 IT8172_MODULE_NAME)) {
2010 err("io ports %#lx->%#lx in use",
2011 s->io, s->io + pci_resource_len(pcidev,0)-1);
2014 if (request_irq(s->irq, it8172_interrupt, SA_INTERRUPT,
2015 IT8172_MODULE_NAME, s)) {
2016 err("irq %u in use", s->irq);
2020 info("IO at %#lx, IRQ %d", s->io, s->irq);
2022 /* register devices */
2023 if ((s->dev_audio = register_sound_dsp(&it8172_audio_fops, -1)) < 0)
2025 if ((s->codec->dev_mixer =
2026 register_sound_mixer(&it8172_mixer_fops, -1)) < 0)
2030 /* intialize the debug proc device */
2031 s->ps = create_proc_read_entry(IT8172_MODULE_NAME, 0, NULL,
2032 proc_it8172_dump, NULL);
2033 #endif /* IT8172_DEBUG */
2036 * Reset the Audio device using the IT8172 PCI Reset register. This
2037 * creates an audible double click on a speaker connected to Line-out.
2039 IT_IO_READ16(IT_PM_PCISR, pcisr);
2040 pcisr |= IT_PM_PCISR_ACSR;
2041 IT_IO_WRITE16(IT_PM_PCISR, pcisr);
2042 /* wait up to 100msec for reset to complete */
2043 for (i=0; pcisr & IT_PM_PCISR_ACSR; i++) {
2047 IT_IO_READ16(IT_PM_PCISR, pcisr);
2050 err("chip reset timeout!");
2054 /* enable pci io and bus mastering */
2055 if (pci_enable_device(pcidev))
2057 pci_set_master(pcidev);
2059 /* get out of legacy mode */
2060 pci_read_config_byte (pcidev, 0x40, &legacy);
2061 pci_write_config_byte (pcidev, 0x40, legacy & ~1);
2063 s->spdif_volume = -1;
2064 /* check to see if s/pdif mode is being requested */
2065 if (spdif[devindex]) {
2066 info("enabling S/PDIF output");
2067 s->spdif_volume = 0;
2068 outb(GC_SOE, s->io+IT_AC_GC);
2070 info("disabling S/PDIF output");
2071 outb(0, s->io+IT_AC_GC);
2074 /* check to see if I2S format requested */
2075 if (i2s_fmt[devindex]) {
2076 info("setting I2S format to 0x%02x", i2s_fmt[devindex]);
2077 outb(i2s_fmt[devindex], s->io+IT_AC_I2SMC);
2079 outb(I2SMC_I2SF_I2S, s->io+IT_AC_I2SMC);
2082 /* cold reset the AC97 */
2083 outw(CODECC_CR, s->io+IT_AC_CODECC);
2085 outw(0, s->io+IT_AC_CODECC);
2086 /* need to delay around 500msec(bleech) to give
2087 some CODECs enough time to wakeup */
2090 /* AC97 warm reset to start the bitclk */
2091 outw(CODECC_WR, s->io+IT_AC_CODECC);
2093 outw(0, s->io+IT_AC_CODECC);
2096 if (!ac97_probe_codec(s->codec))
2099 /* add I2S as allowable recording source */
2100 s->codec->record_sources |= SOUND_MASK_I2S;
2102 /* Enable Volume button interrupts */
2103 imc = inb(s->io+IT_AC_IMC);
2104 outb(imc & ~IMC_VCIM, s->io+IT_AC_IMC);
2106 /* Un-mute PCM and FM out on the controller */
2107 vol = inw(s->io+IT_AC_PCMOV);
2108 outw(vol & ~PCMOV_PCMOM, s->io+IT_AC_PCMOV);
2109 vol = inw(s->io+IT_AC_FMOV);
2110 outw(vol & ~FMOV_FMOM, s->io+IT_AC_FMOV);
2112 /* set channel defaults to 8-bit, mono, 8 Khz */
2115 set_dac_rate(s, 8000);
2116 set_adc_rate(s, 8000);
2118 /* set mic to be the recording source */
2119 val = SOUND_MASK_MIC;
2120 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2121 (unsigned long)&val);
2123 /* mute AC'97 master and PCM when in S/PDIF mode */
2124 if (s->spdif_volume != -1) {
2126 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME,
2127 (unsigned long)&val);
2128 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM,
2129 (unsigned long)&val);
2133 sprintf(proc_str, "driver/%s/%d/ac97", IT8172_MODULE_NAME,
2135 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
2136 ac97_read_proc, s->codec);
2139 /* store it in the driver field */
2140 pci_set_drvdata(pcidev, s);
2141 pcidev->dma_mask = 0xffffffff;
2142 /* put it into driver list */
2143 list_add_tail(&s->devs, &devs);
2144 /* increment devindex */
2145 if (devindex < NR_DEVICE-1)
2150 unregister_sound_mixer(s->codec->dev_mixer);
2152 unregister_sound_dsp(s->dev_audio);
2154 err("cannot register misc device");
2155 free_irq(s->irq, s);
2157 release_region(s->io, pci_resource_len(pcidev,0));
2159 ac97_release_codec(s->codec);
2165 static void __devexit it8172_remove(struct pci_dev *dev)
2167 struct it8172_state *s = pci_get_drvdata(dev);
2174 remove_proc_entry(IT8172_MODULE_NAME, NULL);
2175 #endif /* IT8172_DEBUG */
2177 free_irq(s->irq, s);
2178 release_region(s->io, pci_resource_len(dev,0));
2179 unregister_sound_dsp(s->dev_audio);
2180 unregister_sound_mixer(s->codec->dev_mixer);
2181 ac97_codec_release(s->codec);
2183 pci_set_drvdata(dev, NULL);
2188 static struct pci_device_id id_table[] = {
2189 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G_AUDIO, PCI_ANY_ID,
2194 MODULE_DEVICE_TABLE(pci, id_table);
2196 static struct pci_driver it8172_driver = {
2197 .name = IT8172_MODULE_NAME,
2198 .id_table = id_table,
2199 .probe = it8172_probe,
2200 .remove = __devexit_p(it8172_remove)
2203 static int __init init_it8172(void)
2205 if (!pci_present()) /* No PCI bus in this machine! */
2207 info("version v0.5 time " __TIME__ " " __DATE__);
2208 return pci_module_init(&it8172_driver);
2211 static void __exit cleanup_it8172(void)
2214 pci_unregister_driver(&it8172_driver);
2217 module_init(init_it8172);
2218 module_exit(cleanup_it8172);
2220 /* --------------------------------------------------------------------- */
2224 /* format is: it8172=[spdif],[i2s:<I2S format>] */
2226 static int __init it8172_setup(char *options)
2229 static unsigned __initdata nr_dev = 0;
2231 if (nr_dev >= NR_DEVICE)
2234 if (!options || !*options)
2237 while (this_opt = strsep(&options, ",")) {
2240 if (!strncmp(this_opt, "spdif", 5)) {
2242 } else if (!strncmp(this_opt, "i2s:", 4)) {
2243 if (!strncmp(this_opt+4, "dac", 3))
2244 i2s_fmt[nr_dev] = I2SMC_I2SF_DAC;
2245 else if (!strncmp(this_opt+4, "adc", 3))
2246 i2s_fmt[nr_dev] = I2SMC_I2SF_ADC;
2247 else if (!strncmp(this_opt+4, "i2s", 3))
2248 i2s_fmt[nr_dev] = I2SMC_I2SF_I2S;
2256 __setup("it8172=", it8172_setup);