2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 * Routines for control of EMU10K1 chips
6 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
7 * Added support for Audigy 2 Value.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 #include <sound/driver.h>
33 #include <linux/delay.h>
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vmalloc.h>
40 #include <sound/core.h>
41 #include <sound/emu10k1.h>
44 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Creative Labs, Inc.");
45 MODULE_DESCRIPTION("Routines for control of EMU10K1 chips");
46 MODULE_LICENSE("GPL");
49 /*************************************************************************
51 *************************************************************************/
53 void snd_emu10k1_voice_init(emu10k1_t * emu, int ch)
55 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
56 snd_emu10k1_ptr_write(emu, IP, ch, 0);
57 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
58 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
59 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
60 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
61 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
63 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
64 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
65 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
66 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
67 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
68 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
70 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
71 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
72 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
73 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
74 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
75 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
76 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
77 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
79 /*** these are last so OFF prevents writing ***/
80 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
81 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
82 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
83 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
84 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
86 /* Audigy extra stuffs */
88 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
89 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
90 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
91 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
92 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
93 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
94 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
98 static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
101 unsigned int silent_page;
103 emu->fx8010.itram_size = (16 * 1024)/2;
104 emu->fx8010.etram_pages.area = NULL;
105 emu->fx8010.etram_pages.bytes = 0;
107 /* disable audio and lock cache */
108 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
110 /* reset recording buffers */
111 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
112 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
113 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
114 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
115 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
116 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
118 /* disable channel interrupt */
119 outl(0, emu->port + INTE);
120 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
121 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
122 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
123 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
126 /* set SPDIF bypass mode */
127 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
128 /* enable rear left + rear right AC97 slots */
129 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT | AC97SLOT_REAR_LEFT);
132 /* init envelope engine */
133 for (ch = 0; ch < NUM_G; ch++) {
134 emu->voices[ch].emu = emu;
135 emu->voices[ch].number = ch;
136 snd_emu10k1_voice_init(emu, ch);
140 * Init to 0x02109204 :
141 * Clock accuracy = 0 (1000ppm)
142 * Sample Rate = 2 (48kHz)
143 * Audio Channel = 1 (Left of 2)
144 * Source Number = 0 (Unspecified)
145 * Generation Status = 1 (Original for Cat Code 12)
146 * Cat Code = 12 (Digital Signal Mixer)
148 * Emphasis = 0 (None)
149 * CP = 1 (Copyright unasserted)
150 * AN = 0 (Audio data)
153 snd_emu10k1_ptr_write(emu, SPCS0, 0,
155 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
156 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
157 SPCS_GENERATIONSTATUS | 0x00001200 |
158 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
159 snd_emu10k1_ptr_write(emu, SPCS1, 0,
161 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
162 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
163 SPCS_GENERATIONSTATUS | 0x00001200 |
164 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
165 snd_emu10k1_ptr_write(emu, SPCS2, 0,
167 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
168 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
169 SPCS_GENERATIONSTATUS | 0x00001200 |
170 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
172 if (emu->audigy && emu->revision == 4) { /* audigy2 */
173 /* Hacks for Alice3 to work independent of haP16V driver */
176 //Setup SRCMulti_I2S SamplingRate
177 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
180 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
182 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
183 outl(0x600000, emu->port + 0x20);
184 outl(0x14, emu->port + 0x24);
186 /* Setup SRCMulti Input Audio Enable */
187 outl(0x6E0000, emu->port + 0x20);
188 outl(0xFF00FF00, emu->port + 0x24);
190 if (emu->audigy && (emu->serial == 0x10011102) ) { /* audigy2 Value */
191 /* Hacks for Alice3 to work independent of haP16V driver */
194 snd_printk(KERN_ERR "Audigy2 value:Special config.\n");
195 //Setup SRCMulti_I2S SamplingRate
196 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
199 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
201 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
202 outl(0x600000, emu->port + 0x20);
203 outl(0x14, emu->port + 0x24);
205 /* Setup SRCMulti Input Audio Enable */
206 outl(0x7b0000, emu->port + 0x20);
207 outl(0xFF000000, emu->port + 0x24);
212 * Clear page with silence & setup all pointers to this page
214 memset(emu->silent_page.area, 0, PAGE_SIZE);
215 silent_page = emu->silent_page.addr << 1;
216 for (idx = 0; idx < MAXPAGES; idx++)
217 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
218 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
219 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
220 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
222 silent_page = (emu->silent_page.addr << 1) | MAP_PTI_MASK;
223 for (ch = 0; ch < NUM_G; ch++) {
224 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
225 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
230 * Mute Disable Audio = 0
231 * Lock Tank Memory = 1
232 * Lock Sound Memory = 0
236 if (emu->revision == 4) /* audigy2 */
237 outl(HCFG_AUDIOENABLE |
238 HCFG_AC3ENABLE_CDSPDIF |
239 HCFG_AC3ENABLE_GPSPDIF |
240 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
242 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
243 } else if (emu->model == 0x20 ||
244 emu->model == 0xc400 ||
245 (emu->model == 0x21 && emu->revision < 6))
246 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
248 // With on-chip joystick
249 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
251 if (enable_ir) { /* enable IR for SB Live */
253 unsigned int reg = inl(emu->port + A_IOCFG);
254 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
256 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
258 outl(reg, emu->port + A_IOCFG);
260 unsigned int reg = inl(emu->port + HCFG);
261 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
263 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
265 outl(reg, emu->port + HCFG);
269 if (emu->audigy) { /* enable analog output */
270 unsigned int reg = inl(emu->port + A_IOCFG);
271 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
275 * Initialize the effect engine
277 if ((err = snd_emu10k1_init_efx(emu)) < 0)
281 * Enable the audio bit
283 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
285 /* Enable analog/digital outs on audigy */
287 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
289 if (emu->revision == 4) { /* audigy2 */
290 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
291 * This has to be done after init ALice3 I2SOut beyond 48KHz.
292 * So, sequence is important. */
293 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
294 } else if (emu->serial == 0x10011102) { /* audigy2 value */
295 /* Unmute Analog now. */
296 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
298 /* Disable routing from AC97 line out to Front speakers */
299 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
306 /* FIXME: the following routine disables LiveDrive-II !! */
309 tmp = inl(emu->port + HCFG);
310 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
311 outl(tmp|0x800, emu->port + HCFG);
313 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
315 outl(tmp, emu->port + HCFG);
321 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
323 emu->reserved_page = (emu10k1_memblk_t *)snd_emu10k1_synth_alloc(emu, 4096);
324 if (emu->reserved_page)
325 emu->reserved_page->map_locked = 1;
330 static int snd_emu10k1_done(emu10k1_t * emu)
334 outl(0, emu->port + INTE);
339 for (ch = 0; ch < NUM_G; ch++)
340 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
341 for (ch = 0; ch < NUM_G; ch++) {
342 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
343 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
344 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
345 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
348 /* reset recording buffers */
349 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
350 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
351 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
352 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
353 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
354 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
355 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
356 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
357 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
359 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
361 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
363 /* disable channel interrupt */
364 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
365 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
366 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
367 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
369 /* remove reserved page */
370 if (emu->reserved_page != NULL) {
371 snd_emu10k1_synth_free(emu, (snd_util_memblk_t *)emu->reserved_page);
372 emu->reserved_page = NULL;
375 /* disable audio and lock cache */
376 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
377 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
379 snd_emu10k1_free_efx(emu);
384 /*************************************************************************
385 * ECARD functional implementation
386 *************************************************************************/
388 /* In A1 Silicon, these bits are in the HC register */
389 #define HOOKN_BIT (1L << 12)
390 #define HANDN_BIT (1L << 11)
391 #define PULSEN_BIT (1L << 10)
393 #define EC_GDI1 (1 << 13)
394 #define EC_GDI0 (1 << 14)
396 #define EC_NUM_CONTROL_BITS 20
398 #define EC_AC3_DATA_SELN 0x0001L
399 #define EC_EE_DATA_SEL 0x0002L
400 #define EC_EE_CNTRL_SELN 0x0004L
401 #define EC_EECLK 0x0008L
402 #define EC_EECS 0x0010L
403 #define EC_EESDO 0x0020L
404 #define EC_TRIM_CSN 0x0040L
405 #define EC_TRIM_SCLK 0x0080L
406 #define EC_TRIM_SDATA 0x0100L
407 #define EC_TRIM_MUTEN 0x0200L
408 #define EC_ADCCAL 0x0400L
409 #define EC_ADCRSTN 0x0800L
410 #define EC_DACCAL 0x1000L
411 #define EC_DACMUTEN 0x2000L
412 #define EC_LEDN 0x4000L
414 #define EC_SPDIF0_SEL_SHIFT 15
415 #define EC_SPDIF1_SEL_SHIFT 17
416 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
417 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
418 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
419 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
420 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
421 * be incremented any time the EEPROM's
422 * format is changed. */
424 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
426 /* Addresses for special values stored in to EEPROM */
427 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
428 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
429 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
431 #define EC_LAST_PROMFILE_ADDR 0x2f
433 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
434 * can be up to 30 characters in length
435 * and is stored as a NULL-terminated
436 * ASCII string. Any unused bytes must be
437 * filled with zeros */
438 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
441 /* Most of this stuff is pretty self-evident. According to the hardware
442 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
443 * offset problem. Weird.
445 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
449 #define EC_DEFAULT_ADC_GAIN 0xC4C4
450 #define EC_DEFAULT_SPDIF0_SEL 0x0
451 #define EC_DEFAULT_SPDIF1_SEL 0x4
453 /**************************************************************************
454 * @func Clock bits into the Ecard's control latch. The Ecard uses a
455 * control latch will is loaded bit-serially by toggling the Modem control
456 * lines from function 2 on the E8010. This function hides these details
457 * and presents the illusion that we are actually writing to a distinct
461 static void snd_emu10k1_ecard_write(emu10k1_t * emu, unsigned int value)
463 unsigned short count;
465 unsigned long hc_port;
466 unsigned int hc_value;
468 hc_port = emu->port + HCFG;
469 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
470 outl(hc_value, hc_port);
472 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
474 /* Set up the value */
475 data = ((value & 0x1) ? PULSEN_BIT : 0);
478 outl(hc_value | data, hc_port);
480 /* Clock the shift register */
481 outl(hc_value | data | HANDN_BIT, hc_port);
482 outl(hc_value | data, hc_port);
486 outl(hc_value | HOOKN_BIT, hc_port);
487 outl(hc_value, hc_port);
490 /**************************************************************************
491 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
492 * trim value consists of a 16bit value which is composed of two
493 * 8 bit gain/trim values, one for the left channel and one for the
494 * right channel. The following table maps from the Gain/Attenuation
495 * value in decibels into the corresponding bit pattern for a single
499 static void snd_emu10k1_ecard_setadcgain(emu10k1_t * emu,
504 /* Enable writing to the TRIM registers */
505 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
507 /* Do it again to insure that we meet hold time requirements */
508 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
510 for (bit = (1 << 15); bit; bit >>= 1) {
513 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
516 value |= EC_TRIM_SDATA;
519 snd_emu10k1_ecard_write(emu, value);
520 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
521 snd_emu10k1_ecard_write(emu, value);
524 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
527 static int __devinit snd_emu10k1_ecard_init(emu10k1_t * emu)
529 unsigned int hc_value;
531 /* Set up the initial settings */
532 emu->ecard_ctrl = EC_RAW_RUN_MODE |
533 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
534 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
536 /* Step 0: Set the codec type in the hardware control register
537 * and enable audio output */
538 hc_value = inl(emu->port + HCFG);
539 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
540 inl(emu->port + HCFG);
542 /* Step 1: Turn off the led and deassert TRIM_CS */
543 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
545 /* Step 2: Calibrate the ADC and DAC */
546 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
548 /* Step 3: Wait for awhile; XXX We can't get away with this
549 * under a real operating system; we'll need to block and wait that
551 snd_emu10k1_wait(emu, 48000);
553 /* Step 4: Switch off the DAC and ADC calibration. Note
554 * That ADC_CAL is actually an inverted signal, so we assert
555 * it here to stop calibration. */
556 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
558 /* Step 4: Switch into run mode */
559 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
561 /* Step 5: Set the analog input gain */
562 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
568 * Create the EMU10K1 instance
571 static int snd_emu10k1_free(emu10k1_t *emu)
573 if (emu->port) { /* avoid access to already used hardware */
574 snd_emu10k1_fx8010_tram_setup(emu, 0);
575 snd_emu10k1_done(emu);
578 snd_util_memhdr_free(emu->memhdr);
579 if (emu->silent_page.area)
580 snd_dma_free_pages(&emu->silent_page);
581 if (emu->ptb_pages.area)
582 snd_dma_free_pages(&emu->ptb_pages);
583 vfree(emu->page_ptr_table);
584 vfree(emu->page_addr_table);
586 free_irq(emu->irq, (void *)emu);
588 pci_release_regions(emu->pci);
589 pci_disable_device(emu->pci);
594 static int snd_emu10k1_dev_free(snd_device_t *device)
596 emu10k1_t *emu = device->device_data;
597 return snd_emu10k1_free(emu);
600 int __devinit snd_emu10k1_create(snd_card_t * card,
601 struct pci_dev * pci,
602 unsigned short extin_mask,
603 unsigned short extout_mask,
604 long max_cache_bytes,
611 static snd_device_ops_t ops = {
612 .dev_free = snd_emu10k1_dev_free,
617 // is_audigy = (int)pci->driver_data;
618 is_audigy = (pci->device == 0x0004) || ( (pci->device == 0x0008) );
620 /* enable PCI device */
621 if ((err = pci_enable_device(pci)) < 0)
624 emu = kcalloc(1, sizeof(*emu), GFP_KERNEL);
626 pci_disable_device(pci);
629 /* set the DMA transfer mask */
630 emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
631 if (pci_set_dma_mask(pci, emu->dma_mask) < 0 ||
632 pci_set_consistent_dma_mask(pci, emu->dma_mask) < 0) {
633 snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
635 pci_disable_device(pci);
639 spin_lock_init(&emu->reg_lock);
640 spin_lock_init(&emu->emu_lock);
641 spin_lock_init(&emu->voice_lock);
642 spin_lock_init(&emu->synth_lock);
643 spin_lock_init(&emu->memblk_lock);
644 init_MUTEX(&emu->ptb_lock);
645 init_MUTEX(&emu->fx8010.lock);
646 INIT_LIST_HEAD(&emu->mapped_link_head);
647 INIT_LIST_HEAD(&emu->mapped_order_link_head);
651 emu->get_synth_voice = NULL;
653 emu->audigy = is_audigy;
655 emu->gpr_base = A_FXGPREGBASE;
657 emu->gpr_base = FXGPREGBASE;
659 if ((err = pci_request_regions(pci, "EMU10K1")) < 0) {
661 pci_disable_device(pci);
664 emu->port = pci_resource_start(pci, 0);
666 if (request_irq(pci->irq, snd_emu10k1_interrupt, SA_INTERRUPT|SA_SHIRQ, "EMU10K1", (void *)emu)) {
667 snd_emu10k1_free(emu);
672 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
673 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
674 32 * 1024, &emu->ptb_pages) < 0) {
675 snd_emu10k1_free(emu);
679 emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
680 emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
681 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
682 snd_emu10k1_free(emu);
686 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
687 EMUPAGESIZE, &emu->silent_page) < 0) {
688 snd_emu10k1_free(emu);
691 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
692 if (emu->memhdr == NULL) {
693 snd_emu10k1_free(emu);
696 emu->memhdr->block_extra_size = sizeof(emu10k1_memblk_t) - sizeof(snd_util_memblk_t);
699 /* read revision & serial */
700 pci_read_config_byte(pci, PCI_REVISION_ID, (char *)&emu->revision);
701 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
702 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
703 emu->card_type = EMU10K1_CARD_CREATIVE;
704 if (emu->serial == 0x40011102) {
705 emu->card_type = EMU10K1_CARD_EMUAPS;
707 emu->no_ac97 = 1; /* APS has no AC97 chip */
709 else if (emu->revision == 4 && emu->serial == 0x10051102) {
710 /* Audigy 2 EX has apparently no effective AC97 controls
711 * (for both input and output), so we skip the AC97 detections
713 snd_printdd(KERN_INFO "Audigy2 EX is detected. skipping ac97.\n");
717 if (emu->revision == 4 && (emu->model == 0x2001 || emu->model == 0x2002)) {
719 snd_printdd(KERN_INFO "Audigy2 ZS is detected. setting 7.1 mode.\n");
724 emu->fx8010.fxbus_mask = 0x303f;
727 if (extout_mask == 0)
728 extout_mask = 0x7fff;
729 emu->fx8010.extin_mask = extin_mask;
730 emu->fx8010.extout_mask = extout_mask;
733 if ((err = snd_emu10k1_ecard_init(emu)) < 0) {
734 snd_emu10k1_free(emu);
738 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
739 does not support this, it shouldn't do any harm */
740 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
743 if ((err = snd_emu10k1_init(emu, enable_ir)) < 0) {
744 snd_emu10k1_free(emu);
748 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0) {
749 snd_emu10k1_free(emu);
753 snd_emu10k1_proc_init(emu);
755 snd_card_set_dev(card, &pci->dev);
761 EXPORT_SYMBOL(snd_emu10k1_synth_alloc);
762 EXPORT_SYMBOL(snd_emu10k1_synth_free);
763 EXPORT_SYMBOL(snd_emu10k1_synth_bzero);
764 EXPORT_SYMBOL(snd_emu10k1_synth_copy_from_user);
765 EXPORT_SYMBOL(snd_emu10k1_memblk_map);
767 EXPORT_SYMBOL(snd_emu10k1_voice_alloc);
768 EXPORT_SYMBOL(snd_emu10k1_voice_free);
770 EXPORT_SYMBOL(snd_emu10k1_ptr_read);
771 EXPORT_SYMBOL(snd_emu10k1_ptr_write);