2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <sound/driver.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
34 #include <sound/core.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/asoundef.h>
40 #include <sound/initval.h>
44 /* note, two last pcis should be equal, it is not a bug */
46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
49 MODULE_LICENSE("GPL");
50 MODULE_CLASSES("{sound}");
51 MODULE_DEVICES("{{RME,Digi96},"
55 "{RME,Digi96/8 PAD}}");
57 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
58 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
59 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
62 module_param_array(index, int, boot_devs, 0444);
63 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
64 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
65 module_param_array(id, charp, boot_devs, 0444);
66 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
67 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
68 module_param_array(enable, bool, boot_devs, 0444);
69 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
70 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
73 * Defines for RME Digi96 series, from internal RME reference documents
77 #define RME96_SPDIF_NCHANNELS 2
79 /* Playback and capture buffer size */
80 #define RME96_BUFFER_SIZE 0x10000
83 #define RME96_IO_SIZE 0x60000
86 #define RME96_IO_PLAY_BUFFER 0x0
87 #define RME96_IO_REC_BUFFER 0x10000
88 #define RME96_IO_CONTROL_REGISTER 0x20000
89 #define RME96_IO_ADDITIONAL_REG 0x20004
90 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
91 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
92 #define RME96_IO_SET_PLAY_POS 0x40000
93 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
94 #define RME96_IO_SET_REC_POS 0x50000
95 #define RME96_IO_RESET_REC_POS 0x5FFFC
96 #define RME96_IO_GET_PLAY_POS 0x20000
97 #define RME96_IO_GET_REC_POS 0x30000
99 /* Write control register bits */
100 #define RME96_WCR_START (1 << 0)
101 #define RME96_WCR_START_2 (1 << 1)
102 #define RME96_WCR_GAIN_0 (1 << 2)
103 #define RME96_WCR_GAIN_1 (1 << 3)
104 #define RME96_WCR_MODE24 (1 << 4)
105 #define RME96_WCR_MODE24_2 (1 << 5)
106 #define RME96_WCR_BM (1 << 6)
107 #define RME96_WCR_BM_2 (1 << 7)
108 #define RME96_WCR_ADAT (1 << 8)
109 #define RME96_WCR_FREQ_0 (1 << 9)
110 #define RME96_WCR_FREQ_1 (1 << 10)
111 #define RME96_WCR_DS (1 << 11)
112 #define RME96_WCR_PRO (1 << 12)
113 #define RME96_WCR_EMP (1 << 13)
114 #define RME96_WCR_SEL (1 << 14)
115 #define RME96_WCR_MASTER (1 << 15)
116 #define RME96_WCR_PD (1 << 16)
117 #define RME96_WCR_INP_0 (1 << 17)
118 #define RME96_WCR_INP_1 (1 << 18)
119 #define RME96_WCR_THRU_0 (1 << 19)
120 #define RME96_WCR_THRU_1 (1 << 20)
121 #define RME96_WCR_THRU_2 (1 << 21)
122 #define RME96_WCR_THRU_3 (1 << 22)
123 #define RME96_WCR_THRU_4 (1 << 23)
124 #define RME96_WCR_THRU_5 (1 << 24)
125 #define RME96_WCR_THRU_6 (1 << 25)
126 #define RME96_WCR_THRU_7 (1 << 26)
127 #define RME96_WCR_DOLBY (1 << 27)
128 #define RME96_WCR_MONITOR_0 (1 << 28)
129 #define RME96_WCR_MONITOR_1 (1 << 29)
130 #define RME96_WCR_ISEL (1 << 30)
131 #define RME96_WCR_IDIS (1 << 31)
133 #define RME96_WCR_BITPOS_GAIN_0 2
134 #define RME96_WCR_BITPOS_GAIN_1 3
135 #define RME96_WCR_BITPOS_FREQ_0 9
136 #define RME96_WCR_BITPOS_FREQ_1 10
137 #define RME96_WCR_BITPOS_INP_0 17
138 #define RME96_WCR_BITPOS_INP_1 18
139 #define RME96_WCR_BITPOS_MONITOR_0 28
140 #define RME96_WCR_BITPOS_MONITOR_1 29
142 /* Read control register bits */
143 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
144 #define RME96_RCR_IRQ_2 (1 << 16)
145 #define RME96_RCR_T_OUT (1 << 17)
146 #define RME96_RCR_DEV_ID_0 (1 << 21)
147 #define RME96_RCR_DEV_ID_1 (1 << 22)
148 #define RME96_RCR_LOCK (1 << 23)
149 #define RME96_RCR_VERF (1 << 26)
150 #define RME96_RCR_F0 (1 << 27)
151 #define RME96_RCR_F1 (1 << 28)
152 #define RME96_RCR_F2 (1 << 29)
153 #define RME96_RCR_AUTOSYNC (1 << 30)
154 #define RME96_RCR_IRQ (1 << 31)
156 #define RME96_RCR_BITPOS_F0 27
157 #define RME96_RCR_BITPOS_F1 28
158 #define RME96_RCR_BITPOS_F2 29
160 /* Additonal register bits */
161 #define RME96_AR_WSEL (1 << 0)
162 #define RME96_AR_ANALOG (1 << 1)
163 #define RME96_AR_FREQPAD_0 (1 << 2)
164 #define RME96_AR_FREQPAD_1 (1 << 3)
165 #define RME96_AR_FREQPAD_2 (1 << 4)
166 #define RME96_AR_PD2 (1 << 5)
167 #define RME96_AR_DAC_EN (1 << 6)
168 #define RME96_AR_CLATCH (1 << 7)
169 #define RME96_AR_CCLK (1 << 8)
170 #define RME96_AR_CDATA (1 << 9)
172 #define RME96_AR_BITPOS_F0 2
173 #define RME96_AR_BITPOS_F1 3
174 #define RME96_AR_BITPOS_F2 4
177 #define RME96_MONITOR_TRACKS_1_2 0
178 #define RME96_MONITOR_TRACKS_3_4 1
179 #define RME96_MONITOR_TRACKS_5_6 2
180 #define RME96_MONITOR_TRACKS_7_8 3
183 #define RME96_ATTENUATION_0 0
184 #define RME96_ATTENUATION_6 1
185 #define RME96_ATTENUATION_12 2
186 #define RME96_ATTENUATION_18 3
189 #define RME96_INPUT_OPTICAL 0
190 #define RME96_INPUT_COAXIAL 1
191 #define RME96_INPUT_INTERNAL 2
192 #define RME96_INPUT_XLR 3
193 #define RME96_INPUT_ANALOG 4
196 #define RME96_CLOCKMODE_SLAVE 0
197 #define RME96_CLOCKMODE_MASTER 1
198 #define RME96_CLOCKMODE_WORDCLOCK 2
200 /* Block sizes in bytes */
201 #define RME96_SMALL_BLOCK_SIZE 2048
202 #define RME96_LARGE_BLOCK_SIZE 8192
205 #define RME96_AD1852_VOL_BITS 14
206 #define RME96_AD1855_VOL_BITS 10
209 * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
210 * therefore #ifndef is used.
212 #ifndef PCI_VENDOR_ID_XILINX
213 #define PCI_VENDOR_ID_XILINX 0x10ee
215 #ifndef PCI_DEVICE_ID_DIGI96
216 #define PCI_DEVICE_ID_DIGI96 0x3fc0
218 #ifndef PCI_DEVICE_ID_DIGI96_8
219 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1
221 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO
222 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
224 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
225 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
228 typedef struct snd_rme96 {
232 struct resource *res_port;
233 unsigned long iobase;
235 u32 wcreg; /* cached write control register value */
236 u32 wcreg_spdif; /* S/PDIF setup */
237 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
238 u32 rcreg; /* cached read control register value */
239 u32 areg; /* cached additional register value */
240 u16 vol[2]; /* cached volume of analog output */
242 u8 rev; /* card revision number */
244 snd_pcm_substream_t *playback_substream;
245 snd_pcm_substream_t *capture_substream;
247 int playback_frlog; /* log2 of framesize */
250 size_t playback_periodsize; /* in bytes, zero if not used */
251 size_t capture_periodsize; /* in bytes, zero if not used */
253 snd_pcm_uframes_t playback_last_appl_ptr;
258 snd_pcm_t *spdif_pcm;
261 snd_kcontrol_t *spdif_ctl;
264 static struct pci_device_id snd_rme96_ids[] = {
265 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
267 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
269 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
271 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
276 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
278 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
279 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
280 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
281 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
282 (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
283 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
284 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
285 ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
286 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
289 snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
292 snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
295 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
299 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
302 static snd_pcm_uframes_t
303 snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
305 static snd_pcm_uframes_t
306 snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
308 static void __devinit
309 snd_rme96_proc_init(rme96_t *rme96);
312 snd_rme96_create_switches(snd_card_t *card,
316 snd_rme96_getinputtype(rme96_t *rme96);
318 static inline unsigned int
319 snd_rme96_playback_ptr(rme96_t *rme96)
321 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
322 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
325 static inline unsigned int
326 snd_rme96_capture_ptr(rme96_t *rme96)
328 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
329 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
333 snd_rme96_ratecode(int rate)
336 case 32000: return SNDRV_PCM_RATE_32000;
337 case 44100: return SNDRV_PCM_RATE_44100;
338 case 48000: return SNDRV_PCM_RATE_48000;
339 case 64000: return SNDRV_PCM_RATE_64000;
340 case 88200: return SNDRV_PCM_RATE_88200;
341 case 96000: return SNDRV_PCM_RATE_96000;
347 snd_rme96_playback_silence(snd_pcm_substream_t *substream,
348 int channel, /* not used (interleaved data) */
349 snd_pcm_uframes_t pos,
350 snd_pcm_uframes_t count)
352 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
353 count <<= rme96->playback_frlog;
354 pos <<= rme96->playback_frlog;
355 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
361 snd_rme96_playback_copy(snd_pcm_substream_t *substream,
362 int channel, /* not used (interleaved data) */
363 snd_pcm_uframes_t pos,
365 snd_pcm_uframes_t count)
367 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
368 count <<= rme96->playback_frlog;
369 pos <<= rme96->playback_frlog;
370 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
376 snd_rme96_capture_copy(snd_pcm_substream_t *substream,
377 int channel, /* not used (interleaved data) */
378 snd_pcm_uframes_t pos,
380 snd_pcm_uframes_t count)
382 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
383 count <<= rme96->capture_frlog;
384 pos <<= rme96->capture_frlog;
385 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
391 * Digital output capabilites (S/PDIF)
393 static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
395 .info = (SNDRV_PCM_INFO_MMAP |
396 SNDRV_PCM_INFO_MMAP_VALID |
397 SNDRV_PCM_INFO_INTERLEAVED |
398 SNDRV_PCM_INFO_PAUSE),
399 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
400 SNDRV_PCM_FMTBIT_S32_LE),
401 .rates = (SNDRV_PCM_RATE_32000 |
402 SNDRV_PCM_RATE_44100 |
403 SNDRV_PCM_RATE_48000 |
404 SNDRV_PCM_RATE_64000 |
405 SNDRV_PCM_RATE_88200 |
406 SNDRV_PCM_RATE_96000),
411 .buffer_bytes_max = RME96_BUFFER_SIZE,
412 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
413 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
414 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
415 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
420 * Digital input capabilites (S/PDIF)
422 static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
424 .info = (SNDRV_PCM_INFO_MMAP |
425 SNDRV_PCM_INFO_MMAP_VALID |
426 SNDRV_PCM_INFO_INTERLEAVED |
427 SNDRV_PCM_INFO_PAUSE),
428 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
429 SNDRV_PCM_FMTBIT_S32_LE),
430 .rates = (SNDRV_PCM_RATE_32000 |
431 SNDRV_PCM_RATE_44100 |
432 SNDRV_PCM_RATE_48000 |
433 SNDRV_PCM_RATE_64000 |
434 SNDRV_PCM_RATE_88200 |
435 SNDRV_PCM_RATE_96000),
440 .buffer_bytes_max = RME96_BUFFER_SIZE,
441 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
442 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
443 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
444 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
449 * Digital output capabilites (ADAT)
451 static snd_pcm_hardware_t snd_rme96_playback_adat_info =
453 .info = (SNDRV_PCM_INFO_MMAP |
454 SNDRV_PCM_INFO_MMAP_VALID |
455 SNDRV_PCM_INFO_INTERLEAVED |
456 SNDRV_PCM_INFO_PAUSE),
457 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
458 SNDRV_PCM_FMTBIT_S32_LE),
459 .rates = (SNDRV_PCM_RATE_44100 |
460 SNDRV_PCM_RATE_48000),
465 .buffer_bytes_max = RME96_BUFFER_SIZE,
466 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
467 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
468 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
469 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
474 * Digital input capabilites (ADAT)
476 static snd_pcm_hardware_t snd_rme96_capture_adat_info =
478 .info = (SNDRV_PCM_INFO_MMAP |
479 SNDRV_PCM_INFO_MMAP_VALID |
480 SNDRV_PCM_INFO_INTERLEAVED |
481 SNDRV_PCM_INFO_PAUSE),
482 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
483 SNDRV_PCM_FMTBIT_S32_LE),
484 .rates = (SNDRV_PCM_RATE_44100 |
485 SNDRV_PCM_RATE_48000),
490 .buffer_bytes_max = RME96_BUFFER_SIZE,
491 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
492 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
493 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
494 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
499 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
500 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
501 * on the falling edge of CCLK and be stable on the rising edge. The rising
502 * edge of CLATCH after the last data bit clocks in the whole data word.
503 * A fast processor could probably drive the SPI interface faster than the
504 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
505 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
507 * NOTE: increased delay from 1 to 10, since there where problems setting
511 snd_rme96_write_SPI(rme96_t *rme96, u16 val)
515 for (i = 0; i < 16; i++) {
517 rme96->areg |= RME96_AR_CDATA;
519 rme96->areg &= ~RME96_AR_CDATA;
521 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
522 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
524 rme96->areg |= RME96_AR_CCLK;
525 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
529 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
530 rme96->areg |= RME96_AR_CLATCH;
531 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
533 rme96->areg &= ~RME96_AR_CLATCH;
534 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
538 snd_rme96_apply_dac_volume(rme96_t *rme96)
540 if (RME96_DAC_IS_1852(rme96)) {
541 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
542 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
543 } else if (RME96_DAC_IS_1855(rme96)) {
544 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
545 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
550 snd_rme96_reset_dac(rme96_t *rme96)
552 writel(rme96->wcreg | RME96_WCR_PD,
553 rme96->iobase + RME96_IO_CONTROL_REGISTER);
554 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
558 snd_rme96_getmontracks(rme96_t *rme96)
560 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
561 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
565 snd_rme96_setmontracks(rme96_t *rme96,
569 rme96->wcreg |= RME96_WCR_MONITOR_0;
571 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
574 rme96->wcreg |= RME96_WCR_MONITOR_1;
576 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
578 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
583 snd_rme96_getattenuation(rme96_t *rme96)
585 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
586 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
590 snd_rme96_setattenuation(rme96_t *rme96,
593 switch (attenuation) {
595 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
599 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
603 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
607 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
613 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
618 snd_rme96_capture_getrate(rme96_t *rme96,
624 if (rme96->areg & RME96_AR_ANALOG) {
625 /* Analog input, overrides S/PDIF setting */
626 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
627 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
641 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
644 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
645 if (rme96->rcreg & RME96_RCR_LOCK) {
648 if (rme96->rcreg & RME96_RCR_T_OUT) {
654 if (rme96->rcreg & RME96_RCR_VERF) {
659 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
660 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
661 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
665 if (rme96->rcreg & RME96_RCR_T_OUT) {
669 case 3: return 96000;
670 case 4: return 88200;
671 case 5: return 48000;
672 case 6: return 44100;
673 case 7: return 32000;
681 snd_rme96_playback_getrate(rme96_t *rme96)
685 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
686 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
687 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
692 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
693 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
707 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
711 snd_rme96_playback_setrate(rme96_t *rme96,
716 ds = rme96->wcreg & RME96_WCR_DS;
719 rme96->wcreg &= ~RME96_WCR_DS;
720 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
724 rme96->wcreg &= ~RME96_WCR_DS;
725 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
729 rme96->wcreg &= ~RME96_WCR_DS;
730 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
734 rme96->wcreg |= RME96_WCR_DS;
735 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
739 rme96->wcreg |= RME96_WCR_DS;
740 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
744 rme96->wcreg |= RME96_WCR_DS;
745 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
751 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
752 (ds && !(rme96->wcreg & RME96_WCR_DS)))
754 /* change to/from double-speed: reset the DAC (if available) */
755 snd_rme96_reset_dac(rme96);
757 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
763 snd_rme96_capture_analog_setrate(rme96_t *rme96,
768 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
769 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
772 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
773 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
776 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
777 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
780 if (rme96->rev < 4) {
783 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
784 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
787 if (rme96->rev < 4) {
790 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
791 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
794 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
795 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
800 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
805 snd_rme96_setclockmode(rme96_t *rme96,
809 case RME96_CLOCKMODE_SLAVE:
811 rme96->wcreg &= ~RME96_WCR_MASTER;
812 rme96->areg &= ~RME96_AR_WSEL;
814 case RME96_CLOCKMODE_MASTER:
816 rme96->wcreg |= RME96_WCR_MASTER;
817 rme96->areg &= ~RME96_AR_WSEL;
819 case RME96_CLOCKMODE_WORDCLOCK:
820 /* Word clock is a master mode */
821 rme96->wcreg |= RME96_WCR_MASTER;
822 rme96->areg |= RME96_AR_WSEL;
827 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
828 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
833 snd_rme96_getclockmode(rme96_t *rme96)
835 if (rme96->areg & RME96_AR_WSEL) {
836 return RME96_CLOCKMODE_WORDCLOCK;
838 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
839 RME96_CLOCKMODE_SLAVE;
843 snd_rme96_setinputtype(rme96_t *rme96,
849 case RME96_INPUT_OPTICAL:
850 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
853 case RME96_INPUT_COAXIAL:
854 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
857 case RME96_INPUT_INTERNAL:
858 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
861 case RME96_INPUT_XLR:
862 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
863 rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) ||
864 (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
867 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
870 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
873 case RME96_INPUT_ANALOG:
874 if (!RME96_HAS_ANALOG_IN(rme96)) {
877 rme96->areg |= RME96_AR_ANALOG;
878 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
879 if (rme96->rev < 4) {
881 * Revision less than 004 does not support 64 and
884 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
885 snd_rme96_capture_analog_setrate(rme96, 44100);
887 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
888 snd_rme96_capture_analog_setrate(rme96, 32000);
895 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
896 rme96->areg &= ~RME96_AR_ANALOG;
897 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
899 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
904 snd_rme96_getinputtype(rme96_t *rme96)
906 if (rme96->areg & RME96_AR_ANALOG) {
907 return RME96_INPUT_ANALOG;
909 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
910 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
914 snd_rme96_setframelog(rme96_t *rme96,
920 if (n_channels == 2) {
923 /* assume 8 channels */
927 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
928 rme96->playback_frlog = frlog;
930 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
931 rme96->capture_frlog = frlog;
936 snd_rme96_playback_setformat(rme96_t *rme96,
940 case SNDRV_PCM_FORMAT_S16_LE:
941 rme96->wcreg &= ~RME96_WCR_MODE24;
943 case SNDRV_PCM_FORMAT_S32_LE:
944 rme96->wcreg |= RME96_WCR_MODE24;
949 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
954 snd_rme96_capture_setformat(rme96_t *rme96,
958 case SNDRV_PCM_FORMAT_S16_LE:
959 rme96->wcreg &= ~RME96_WCR_MODE24_2;
961 case SNDRV_PCM_FORMAT_S32_LE:
962 rme96->wcreg |= RME96_WCR_MODE24_2;
967 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
972 snd_rme96_set_period_properties(rme96_t *rme96,
975 switch (period_bytes) {
976 case RME96_LARGE_BLOCK_SIZE:
977 rme96->wcreg &= ~RME96_WCR_ISEL;
979 case RME96_SMALL_BLOCK_SIZE:
980 rme96->wcreg |= RME96_WCR_ISEL;
986 rme96->wcreg &= ~RME96_WCR_IDIS;
987 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
991 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
992 snd_pcm_hw_params_t *params)
995 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
996 int err, rate, dummy;
998 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
1000 spin_lock_irqsave(&rme96->lock, flags);
1001 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1002 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1003 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1006 if ((int)params_rate(params) != rate) {
1007 spin_unlock_irqrestore(&rme96->lock, flags);
1010 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1011 spin_unlock_irqrestore(&rme96->lock, flags);
1014 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1015 spin_unlock_irqrestore(&rme96->lock, flags);
1018 snd_rme96_setframelog(rme96, params_channels(params), 1);
1019 if (rme96->capture_periodsize != 0) {
1020 if (params_period_size(params) << rme96->playback_frlog !=
1021 rme96->capture_periodsize)
1023 spin_unlock_irqrestore(&rme96->lock, flags);
1027 rme96->playback_periodsize =
1028 params_period_size(params) << rme96->playback_frlog;
1029 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1031 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1032 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1033 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1035 spin_unlock_irqrestore(&rme96->lock, flags);
1041 snd_rme96_playback_hw_free(snd_pcm_substream_t *substream)
1043 snd_pcm_lib_free_pages(substream);
1048 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
1049 snd_pcm_hw_params_t *params)
1051 unsigned long flags;
1052 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1053 snd_pcm_runtime_t *runtime = substream->runtime;
1054 int err, isadat, rate;
1056 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
1058 spin_lock_irqsave(&rme96->lock, flags);
1059 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1060 spin_unlock_irqrestore(&rme96->lock, flags);
1063 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1064 if ((err = snd_rme96_capture_analog_setrate(rme96,
1065 params_rate(params))) < 0)
1067 spin_unlock_irqrestore(&rme96->lock, flags);
1070 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1071 if ((int)params_rate(params) != rate) {
1072 spin_unlock_irqrestore(&rme96->lock, flags);
1075 if ((isadat && runtime->hw.channels_min == 2) ||
1076 (!isadat && runtime->hw.channels_min == 8))
1078 spin_unlock_irqrestore(&rme96->lock, flags);
1082 snd_rme96_setframelog(rme96, params_channels(params), 0);
1083 if (rme96->playback_periodsize != 0) {
1084 if (params_period_size(params) << rme96->capture_frlog !=
1085 rme96->playback_periodsize)
1087 spin_unlock_irqrestore(&rme96->lock, flags);
1091 rme96->capture_periodsize =
1092 params_period_size(params) << rme96->capture_frlog;
1093 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1094 spin_unlock_irqrestore(&rme96->lock, flags);
1100 snd_rme96_capture_hw_free(snd_pcm_substream_t *substream)
1102 snd_pcm_lib_free_pages(substream);
1107 snd_rme96_playback_start(rme96_t *rme96,
1111 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1112 rme96->playback_last_appl_ptr = 0;
1113 rme96->playback_ptr = 0;
1116 rme96->wcreg |= RME96_WCR_START;
1117 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1121 snd_rme96_capture_start(rme96_t *rme96,
1125 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1126 rme96->capture_ptr = 0;
1129 rme96->wcreg |= RME96_WCR_START_2;
1130 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1134 snd_rme96_playback_stop(rme96_t *rme96)
1137 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1138 * the hardware will not stop generating interrupts
1140 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1141 if (rme96->rcreg & RME96_RCR_IRQ) {
1142 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1144 rme96->wcreg &= ~RME96_WCR_START;
1145 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1149 snd_rme96_capture_stop(rme96_t *rme96)
1151 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1152 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1153 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1155 rme96->wcreg &= ~RME96_WCR_START_2;
1156 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1160 snd_rme96_interrupt(int irq,
1162 struct pt_regs *regs)
1164 rme96_t *rme96 = (rme96_t *)dev_id;
1166 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1167 /* fastpath out, to ease interrupt sharing */
1168 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1169 (rme96->rcreg & RME96_RCR_IRQ_2)))
1174 if (rme96->rcreg & RME96_RCR_IRQ) {
1176 snd_pcm_period_elapsed(rme96->playback_substream);
1177 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1179 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1181 snd_pcm_period_elapsed(rme96->capture_substream);
1182 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1187 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1189 #define PERIOD_BYTES sizeof(period_bytes) / sizeof(period_bytes[0])
1191 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1192 .count = PERIOD_BYTES,
1193 .list = period_bytes,
1198 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1200 unsigned long flags;
1202 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1203 snd_pcm_runtime_t *runtime = substream->runtime;
1205 snd_pcm_set_sync(substream);
1207 spin_lock_irqsave(&rme96->lock, flags);
1208 if (rme96->playback_substream != NULL) {
1209 spin_unlock_irqrestore(&rme96->lock, flags);
1212 rme96->wcreg &= ~RME96_WCR_ADAT;
1213 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1214 rme96->playback_substream = substream;
1215 rme96->playback_last_appl_ptr = 0;
1216 rme96->playback_ptr = 0;
1217 spin_unlock_irqrestore(&rme96->lock, flags);
1219 runtime->hw = snd_rme96_playback_spdif_info;
1220 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1221 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1222 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1225 runtime->hw.rates = snd_rme96_ratecode(rate);
1226 runtime->hw.rate_min = rate;
1227 runtime->hw.rate_max = rate;
1229 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1230 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1232 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1233 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1234 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1235 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1240 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1242 unsigned long flags;
1244 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1245 snd_pcm_runtime_t *runtime = substream->runtime;
1247 snd_pcm_set_sync(substream);
1249 runtime->hw = snd_rme96_capture_spdif_info;
1250 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1251 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1256 runtime->hw.rates = snd_rme96_ratecode(rate);
1257 runtime->hw.rate_min = rate;
1258 runtime->hw.rate_max = rate;
1261 spin_lock_irqsave(&rme96->lock, flags);
1262 if (rme96->capture_substream != NULL) {
1263 spin_unlock_irqrestore(&rme96->lock, flags);
1266 rme96->capture_substream = substream;
1267 rme96->capture_ptr = 0;
1268 spin_unlock_irqrestore(&rme96->lock, flags);
1270 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1271 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1277 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1279 unsigned long flags;
1281 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1282 snd_pcm_runtime_t *runtime = substream->runtime;
1284 snd_pcm_set_sync(substream);
1286 spin_lock_irqsave(&rme96->lock, flags);
1287 if (rme96->playback_substream != NULL) {
1288 spin_unlock_irqrestore(&rme96->lock, flags);
1291 rme96->wcreg |= RME96_WCR_ADAT;
1292 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1293 rme96->playback_substream = substream;
1294 rme96->playback_last_appl_ptr = 0;
1295 rme96->playback_ptr = 0;
1296 spin_unlock_irqrestore(&rme96->lock, flags);
1298 runtime->hw = snd_rme96_playback_adat_info;
1299 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1300 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1301 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1304 runtime->hw.rates = snd_rme96_ratecode(rate);
1305 runtime->hw.rate_min = rate;
1306 runtime->hw.rate_max = rate;
1308 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1309 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1314 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1316 unsigned long flags;
1318 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1319 snd_pcm_runtime_t *runtime = substream->runtime;
1321 snd_pcm_set_sync(substream);
1323 runtime->hw = snd_rme96_capture_adat_info;
1324 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1325 /* makes no sense to use analog input. Note that analog
1326 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1329 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1333 runtime->hw.rates = snd_rme96_ratecode(rate);
1334 runtime->hw.rate_min = rate;
1335 runtime->hw.rate_max = rate;
1338 spin_lock_irqsave(&rme96->lock, flags);
1339 if (rme96->capture_substream != NULL) {
1340 spin_unlock_irqrestore(&rme96->lock, flags);
1343 rme96->capture_substream = substream;
1344 rme96->capture_ptr = 0;
1345 spin_unlock_irqrestore(&rme96->lock, flags);
1347 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1348 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1353 snd_rme96_playback_close(snd_pcm_substream_t *substream)
1355 unsigned long flags;
1356 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1359 spin_lock_irqsave(&rme96->lock, flags);
1360 if (RME96_ISPLAYING(rme96)) {
1361 snd_rme96_playback_stop(rme96);
1363 rme96->playback_substream = NULL;
1364 rme96->playback_periodsize = 0;
1365 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1366 spin_unlock_irqrestore(&rme96->lock, flags);
1368 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1369 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1370 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1376 snd_rme96_capture_close(snd_pcm_substream_t *substream)
1378 unsigned long flags;
1379 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1381 spin_lock_irqsave(&rme96->lock, flags);
1382 if (RME96_ISRECORDING(rme96)) {
1383 snd_rme96_capture_stop(rme96);
1385 rme96->capture_substream = NULL;
1386 rme96->capture_periodsize = 0;
1387 spin_unlock_irqrestore(&rme96->lock, flags);
1392 snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1394 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1395 unsigned long flags;
1397 spin_lock_irqsave(&rme96->lock, flags);
1398 if (RME96_ISPLAYING(rme96)) {
1399 snd_rme96_playback_stop(rme96);
1401 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1402 spin_unlock_irqrestore(&rme96->lock, flags);
1407 snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1409 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1410 unsigned long flags;
1412 spin_lock_irqsave(&rme96->lock, flags);
1413 if (RME96_ISRECORDING(rme96)) {
1414 snd_rme96_capture_stop(rme96);
1416 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1417 spin_unlock_irqrestore(&rme96->lock, flags);
1422 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1425 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1428 case SNDRV_PCM_TRIGGER_START:
1429 if (!RME96_ISPLAYING(rme96)) {
1430 if (substream != rme96->playback_substream) {
1433 snd_rme96_playback_start(rme96, 0);
1437 case SNDRV_PCM_TRIGGER_STOP:
1438 if (RME96_ISPLAYING(rme96)) {
1439 if (substream != rme96->playback_substream) {
1442 snd_rme96_playback_stop(rme96);
1446 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1447 if (RME96_ISPLAYING(rme96)) {
1448 snd_rme96_playback_stop(rme96);
1452 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1453 if (!RME96_ISPLAYING(rme96)) {
1454 snd_rme96_playback_start(rme96, 1);
1465 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1468 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1471 case SNDRV_PCM_TRIGGER_START:
1472 if (!RME96_ISRECORDING(rme96)) {
1473 if (substream != rme96->capture_substream) {
1476 snd_rme96_capture_start(rme96, 0);
1480 case SNDRV_PCM_TRIGGER_STOP:
1481 if (RME96_ISRECORDING(rme96)) {
1482 if (substream != rme96->capture_substream) {
1485 snd_rme96_capture_stop(rme96);
1489 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1490 if (RME96_ISRECORDING(rme96)) {
1491 snd_rme96_capture_stop(rme96);
1495 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1496 if (!RME96_ISRECORDING(rme96)) {
1497 snd_rme96_capture_start(rme96, 1);
1508 static snd_pcm_uframes_t
1509 snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1511 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1512 snd_pcm_runtime_t *runtime = substream->runtime;
1513 snd_pcm_sframes_t diff;
1516 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1517 diff = runtime->control->appl_ptr -
1518 rme96->playback_last_appl_ptr;
1519 rme96->playback_last_appl_ptr = runtime->control->appl_ptr;
1521 diff < -(snd_pcm_sframes_t)(runtime->boundary >> 1))
1523 diff += runtime->boundary;
1525 bytes = diff << rme96->playback_frlog;
1527 if (bytes > RME96_BUFFER_SIZE - rme96->playback_ptr) {
1528 memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER +
1529 rme96->playback_ptr),
1530 runtime->dma_area + rme96->playback_ptr,
1531 RME96_BUFFER_SIZE - rme96->playback_ptr);
1532 bytes -= RME96_BUFFER_SIZE - rme96->playback_ptr;
1533 if (bytes > RME96_BUFFER_SIZE) {
1534 bytes = RME96_BUFFER_SIZE;
1536 memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER),
1539 rme96->playback_ptr = bytes;
1540 } else if (bytes != 0) {
1541 memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER +
1542 rme96->playback_ptr),
1543 runtime->dma_area + rme96->playback_ptr,
1545 rme96->playback_ptr += bytes;
1548 return snd_rme96_playback_ptr(rme96);
1551 static snd_pcm_uframes_t
1552 snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1554 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1555 snd_pcm_runtime_t *runtime = substream->runtime;
1556 snd_pcm_uframes_t frameptr;
1559 frameptr = snd_rme96_capture_ptr(rme96);
1560 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1561 ptr = frameptr << rme96->capture_frlog;
1562 if (ptr > rme96->capture_ptr) {
1563 memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1564 (void *)(rme96->iobase + RME96_IO_REC_BUFFER +
1565 rme96->capture_ptr),
1566 ptr - rme96->capture_ptr);
1567 rme96->capture_ptr += ptr - rme96->capture_ptr;
1568 } else if (ptr < rme96->capture_ptr) {
1569 memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1570 (void *)(rme96->iobase + RME96_IO_REC_BUFFER +
1571 rme96->capture_ptr),
1572 RME96_BUFFER_SIZE - rme96->capture_ptr);
1573 memcpy_fromio(runtime->dma_area,
1574 (void *)(rme96->iobase + RME96_IO_REC_BUFFER),
1576 rme96->capture_ptr = ptr;
1582 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1583 .open = snd_rme96_playback_spdif_open,
1584 .close = snd_rme96_playback_close,
1585 .ioctl = snd_pcm_lib_ioctl,
1586 .hw_params = snd_rme96_playback_hw_params,
1587 .hw_free = snd_rme96_playback_hw_free,
1588 .prepare = snd_rme96_playback_prepare,
1589 .trigger = snd_rme96_playback_trigger,
1590 .pointer = snd_rme96_playback_pointer,
1591 .copy = snd_rme96_playback_copy,
1592 .silence = snd_rme96_playback_silence,
1595 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1596 .open = snd_rme96_capture_spdif_open,
1597 .close = snd_rme96_capture_close,
1598 .ioctl = snd_pcm_lib_ioctl,
1599 .hw_params = snd_rme96_capture_hw_params,
1600 .hw_free = snd_rme96_capture_hw_free,
1601 .prepare = snd_rme96_capture_prepare,
1602 .trigger = snd_rme96_capture_trigger,
1603 .pointer = snd_rme96_capture_pointer,
1604 .copy = snd_rme96_capture_copy,
1607 static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1608 .open = snd_rme96_playback_adat_open,
1609 .close = snd_rme96_playback_close,
1610 .ioctl = snd_pcm_lib_ioctl,
1611 .hw_params = snd_rme96_playback_hw_params,
1612 .hw_free = snd_rme96_playback_hw_free,
1613 .prepare = snd_rme96_playback_prepare,
1614 .trigger = snd_rme96_playback_trigger,
1615 .pointer = snd_rme96_playback_pointer,
1616 .copy = snd_rme96_playback_copy,
1617 .silence = snd_rme96_playback_silence,
1620 static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1621 .open = snd_rme96_capture_adat_open,
1622 .close = snd_rme96_capture_close,
1623 .ioctl = snd_pcm_lib_ioctl,
1624 .hw_params = snd_rme96_capture_hw_params,
1625 .hw_free = snd_rme96_capture_hw_free,
1626 .prepare = snd_rme96_capture_prepare,
1627 .trigger = snd_rme96_capture_trigger,
1628 .pointer = snd_rme96_capture_pointer,
1629 .copy = snd_rme96_capture_copy,
1633 snd_rme96_free(void *private_data)
1635 rme96_t *rme96 = (rme96_t *)private_data;
1637 if (rme96 == NULL) {
1640 if (rme96->irq >= 0) {
1641 snd_rme96_playback_stop(rme96);
1642 snd_rme96_capture_stop(rme96);
1643 rme96->areg &= ~RME96_AR_DAC_EN;
1644 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1645 free_irq(rme96->irq, (void *)rme96);
1648 if (rme96->iobase) {
1649 iounmap((void *)rme96->iobase);
1652 if (rme96->res_port != NULL) {
1653 release_resource(rme96->res_port);
1654 kfree_nocheck(rme96->res_port);
1655 rme96->res_port = NULL;
1660 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1662 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1663 rme96->spdif_pcm = NULL;
1664 snd_pcm_lib_preallocate_free_for_all(pcm);
1668 snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1670 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1671 rme96->adat_pcm = NULL;
1672 snd_pcm_lib_preallocate_free_for_all(pcm);
1675 static int __devinit
1676 snd_rme96_create(rme96_t *rme96)
1678 struct pci_dev *pci = rme96->pci;
1683 if ((err = pci_enable_device(pci)) < 0)
1686 rme96->port = pci_resource_start(rme96->pci, 0);
1688 if ((rme96->res_port = request_mem_region(rme96->port, RME96_IO_SIZE, "RME96")) == NULL) {
1689 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1693 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1694 snd_printk("unable to grab IRQ %d\n", pci->irq);
1697 rme96->irq = pci->irq;
1699 spin_lock_init(&rme96->lock);
1700 if ((rme96->iobase = (unsigned long) ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1701 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1705 /* read the card's revision number */
1706 pci_read_config_byte(pci, 8, &rme96->rev);
1708 /* set up ALSA pcm device for S/PDIF */
1709 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1710 1, 1, &rme96->spdif_pcm)) < 0)
1714 rme96->spdif_pcm->private_data = rme96;
1715 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1716 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1717 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1718 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1720 rme96->spdif_pcm->info_flags = 0;
1722 snd_pcm_lib_preallocate_pages_for_all(rme96->spdif_pcm,
1723 SNDRV_DMA_TYPE_CONTINUOUS,
1724 snd_dma_continuous_data(GFP_KERNEL),
1728 /* set up ALSA pcm device for ADAT */
1729 if (pci->device == PCI_DEVICE_ID_DIGI96) {
1730 /* ADAT is not available on the base model */
1731 rme96->adat_pcm = NULL;
1733 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1734 1, 1, &rme96->adat_pcm)) < 0)
1738 rme96->adat_pcm->private_data = rme96;
1739 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1740 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1741 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1742 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1744 rme96->adat_pcm->info_flags = 0;
1746 snd_pcm_lib_preallocate_pages_for_all(rme96->adat_pcm,
1747 SNDRV_DMA_TYPE_CONTINUOUS,
1748 snd_dma_continuous_data(GFP_KERNEL),
1753 rme96->playback_periodsize = 0;
1754 rme96->capture_periodsize = 0;
1756 /* make sure playback/capture is stopped, if by some reason active */
1757 snd_rme96_playback_stop(rme96);
1758 snd_rme96_capture_stop(rme96);
1760 /* set default values in registers */
1762 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1763 RME96_WCR_SEL | /* normal playback */
1764 RME96_WCR_MASTER | /* set to master clock mode */
1765 RME96_WCR_INP_0; /* set coaxial input */
1767 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1769 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1770 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1773 writel(rme96->areg | RME96_AR_PD2,
1774 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1775 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1777 /* reset and enable the DAC (order is important). */
1778 snd_rme96_reset_dac(rme96);
1779 rme96->areg |= RME96_AR_DAC_EN;
1780 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1782 /* reset playback and record buffer pointers */
1783 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1784 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1787 rme96->vol[0] = rme96->vol[1] = 0;
1788 if (RME96_HAS_ANALOG_OUT(rme96)) {
1789 snd_rme96_apply_dac_volume(rme96);
1792 /* init switch interface */
1793 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1797 /* init proc interface */
1798 snd_rme96_proc_init(rme96);
1808 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1811 rme96_t *rme96 = (rme96_t *)entry->private_data;
1813 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1815 snd_iprintf(buffer, rme96->card->longname);
1816 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1818 snd_iprintf(buffer, "\nGeneral settings\n");
1819 if (rme96->wcreg & RME96_WCR_IDIS) {
1820 snd_iprintf(buffer, " period size: N/A (interrupts "
1822 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1823 snd_iprintf(buffer, " period size: 2048 bytes\n");
1825 snd_iprintf(buffer, " period size: 8192 bytes\n");
1827 snd_iprintf(buffer, "\nInput settings\n");
1828 switch (snd_rme96_getinputtype(rme96)) {
1829 case RME96_INPUT_OPTICAL:
1830 snd_iprintf(buffer, " input: optical");
1832 case RME96_INPUT_COAXIAL:
1833 snd_iprintf(buffer, " input: coaxial");
1835 case RME96_INPUT_INTERNAL:
1836 snd_iprintf(buffer, " input: internal");
1838 case RME96_INPUT_XLR:
1839 snd_iprintf(buffer, " input: XLR");
1841 case RME96_INPUT_ANALOG:
1842 snd_iprintf(buffer, " input: analog");
1845 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1846 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1849 snd_iprintf(buffer, " (8 channels)\n");
1851 snd_iprintf(buffer, " (2 channels)\n");
1853 snd_iprintf(buffer, " sample rate: %d Hz\n",
1854 snd_rme96_capture_getrate(rme96, &n));
1856 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1857 snd_iprintf(buffer, " sample format: 24 bit\n");
1859 snd_iprintf(buffer, " sample format: 16 bit\n");
1862 snd_iprintf(buffer, "\nOutput settings\n");
1863 if (rme96->wcreg & RME96_WCR_SEL) {
1864 snd_iprintf(buffer, " output signal: normal playback\n");
1866 snd_iprintf(buffer, " output signal: same as input\n");
1868 snd_iprintf(buffer, " sample rate: %d Hz\n",
1869 snd_rme96_playback_getrate(rme96));
1870 if (rme96->wcreg & RME96_WCR_MODE24) {
1871 snd_iprintf(buffer, " sample format: 24 bit\n");
1873 snd_iprintf(buffer, " sample format: 16 bit\n");
1875 if (rme96->areg & RME96_AR_WSEL) {
1876 snd_iprintf(buffer, " sample clock source: word clock\n");
1877 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1878 snd_iprintf(buffer, " sample clock source: internal\n");
1879 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1880 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1881 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1882 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1884 snd_iprintf(buffer, " sample clock source: autosync\n");
1886 if (rme96->wcreg & RME96_WCR_PRO) {
1887 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1889 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1891 if (rme96->wcreg & RME96_WCR_EMP) {
1892 snd_iprintf(buffer, " emphasis: on\n");
1894 snd_iprintf(buffer, " emphasis: off\n");
1896 if (rme96->wcreg & RME96_WCR_DOLBY) {
1897 snd_iprintf(buffer, " non-audio (dolby): on\n");
1899 snd_iprintf(buffer, " non-audio (dolby): off\n");
1901 if (RME96_HAS_ANALOG_IN(rme96)) {
1902 snd_iprintf(buffer, "\nAnalog output settings\n");
1903 switch (snd_rme96_getmontracks(rme96)) {
1904 case RME96_MONITOR_TRACKS_1_2:
1905 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1907 case RME96_MONITOR_TRACKS_3_4:
1908 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1910 case RME96_MONITOR_TRACKS_5_6:
1911 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1913 case RME96_MONITOR_TRACKS_7_8:
1914 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1917 switch (snd_rme96_getattenuation(rme96)) {
1918 case RME96_ATTENUATION_0:
1919 snd_iprintf(buffer, " attenuation: 0 dB\n");
1921 case RME96_ATTENUATION_6:
1922 snd_iprintf(buffer, " attenuation: -6 dB\n");
1924 case RME96_ATTENUATION_12:
1925 snd_iprintf(buffer, " attenuation: -12 dB\n");
1927 case RME96_ATTENUATION_18:
1928 snd_iprintf(buffer, " attenuation: -18 dB\n");
1931 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1932 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1936 static void __devinit
1937 snd_rme96_proc_init(rme96_t *rme96)
1939 snd_info_entry_t *entry;
1941 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1942 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1950 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1952 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1954 uinfo->value.integer.min = 0;
1955 uinfo->value.integer.max = 1;
1959 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1961 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1962 unsigned long flags;
1964 spin_lock_irqsave(&rme96->lock, flags);
1965 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1966 spin_unlock_irqrestore(&rme96->lock, flags);
1970 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1972 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1973 unsigned long flags;
1977 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1978 spin_lock_irqsave(&rme96->lock, flags);
1979 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1980 change = val != rme96->wcreg;
1981 writel(rme96->wcreg = val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1982 spin_unlock_irqrestore(&rme96->lock, flags);
1987 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1989 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1990 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1991 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1993 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1995 switch (rme96->pci->device) {
1996 case PCI_DEVICE_ID_DIGI96:
1997 case PCI_DEVICE_ID_DIGI96_8:
1998 uinfo->value.enumerated.items = 3;
2000 case PCI_DEVICE_ID_DIGI96_8_PRO:
2001 uinfo->value.enumerated.items = 4;
2003 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2004 if (rme96->rev > 4) {
2006 uinfo->value.enumerated.items = 4;
2007 texts[3] = _texts[4]; /* Analog instead of XLR */
2010 uinfo->value.enumerated.items = 5;
2017 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
2018 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2020 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2024 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2026 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2027 unsigned long flags;
2028 unsigned int items = 3;
2030 spin_lock_irqsave(&rme96->lock, flags);
2031 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
2033 switch (rme96->pci->device) {
2034 case PCI_DEVICE_ID_DIGI96:
2035 case PCI_DEVICE_ID_DIGI96_8:
2038 case PCI_DEVICE_ID_DIGI96_8_PRO:
2041 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2042 if (rme96->rev > 4) {
2043 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
2044 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
2045 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
2056 if (ucontrol->value.enumerated.item[0] >= items) {
2057 ucontrol->value.enumerated.item[0] = items - 1;
2060 spin_unlock_irqrestore(&rme96->lock, flags);
2064 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2066 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2067 unsigned long flags;
2069 int change, items = 3;
2071 switch (rme96->pci->device) {
2072 case PCI_DEVICE_ID_DIGI96:
2073 case PCI_DEVICE_ID_DIGI96_8:
2076 case PCI_DEVICE_ID_DIGI96_8_PRO:
2079 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2080 if (rme96->rev > 4) {
2090 val = ucontrol->value.enumerated.item[0] % items;
2092 /* special case for PST */
2093 if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
2094 if (val == RME96_INPUT_XLR) {
2095 val = RME96_INPUT_ANALOG;
2099 spin_lock_irqsave(&rme96->lock, flags);
2100 change = (int)val != snd_rme96_getinputtype(rme96);
2101 snd_rme96_setinputtype(rme96, val);
2102 spin_unlock_irqrestore(&rme96->lock, flags);
2107 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2109 static char *texts[3] = { "AutoSync", "Internal", "Word" };
2111 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2113 uinfo->value.enumerated.items = 3;
2114 if (uinfo->value.enumerated.item > 2) {
2115 uinfo->value.enumerated.item = 2;
2117 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2121 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2123 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2124 unsigned long flags;
2126 spin_lock_irqsave(&rme96->lock, flags);
2127 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2128 spin_unlock_irqrestore(&rme96->lock, flags);
2132 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2134 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2135 unsigned long flags;
2139 val = ucontrol->value.enumerated.item[0] % 3;
2140 spin_lock_irqsave(&rme96->lock, flags);
2141 change = (int)val != snd_rme96_getclockmode(rme96);
2142 snd_rme96_setclockmode(rme96, val);
2143 spin_unlock_irqrestore(&rme96->lock, flags);
2148 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2150 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2152 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2154 uinfo->value.enumerated.items = 4;
2155 if (uinfo->value.enumerated.item > 3) {
2156 uinfo->value.enumerated.item = 3;
2158 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2162 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2164 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2165 unsigned long flags;
2167 spin_lock_irqsave(&rme96->lock, flags);
2168 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2169 spin_unlock_irqrestore(&rme96->lock, flags);
2173 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2175 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2176 unsigned long flags;
2180 val = ucontrol->value.enumerated.item[0] % 4;
2181 spin_lock_irqsave(&rme96->lock, flags);
2183 change = (int)val != snd_rme96_getattenuation(rme96);
2184 snd_rme96_setattenuation(rme96, val);
2185 spin_unlock_irqrestore(&rme96->lock, flags);
2190 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2192 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2194 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2196 uinfo->value.enumerated.items = 4;
2197 if (uinfo->value.enumerated.item > 3) {
2198 uinfo->value.enumerated.item = 3;
2200 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2204 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2206 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2207 unsigned long flags;
2209 spin_lock_irqsave(&rme96->lock, flags);
2210 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2211 spin_unlock_irqrestore(&rme96->lock, flags);
2215 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2217 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2218 unsigned long flags;
2222 val = ucontrol->value.enumerated.item[0] % 4;
2223 spin_lock_irqsave(&rme96->lock, flags);
2224 change = (int)val != snd_rme96_getmontracks(rme96);
2225 snd_rme96_setmontracks(rme96, val);
2226 spin_unlock_irqrestore(&rme96->lock, flags);
2230 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2233 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2234 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2235 if (val & RME96_WCR_PRO)
2236 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2238 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2242 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2244 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2245 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2246 if (val & RME96_WCR_PRO)
2247 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2249 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2252 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2254 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2259 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2261 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2263 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2267 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2269 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2270 unsigned long flags;
2274 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2275 spin_lock_irqsave(&rme96->lock, flags);
2276 change = val != rme96->wcreg_spdif;
2277 rme96->wcreg_spdif = val;
2278 spin_unlock_irqrestore(&rme96->lock, flags);
2282 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2284 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2289 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2291 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2293 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2297 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2299 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2300 unsigned long flags;
2304 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2305 spin_lock_irqsave(&rme96->lock, flags);
2306 change = val != rme96->wcreg_spdif_stream;
2307 rme96->wcreg_spdif_stream = val;
2308 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2309 writel(rme96->wcreg |= val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2310 spin_unlock_irqrestore(&rme96->lock, flags);
2314 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2316 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2321 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2323 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2328 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2330 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2332 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2334 uinfo->value.integer.min = 0;
2335 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2340 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2342 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2343 unsigned long flags;
2345 spin_lock_irqsave(&rme96->lock, flags);
2346 u->value.integer.value[0] = rme96->vol[0];
2347 u->value.integer.value[1] = rme96->vol[1];
2348 spin_unlock_irqrestore(&rme96->lock, flags);
2354 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2356 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2357 unsigned long flags;
2360 if (!RME96_HAS_ANALOG_OUT(rme96)) {
2363 spin_lock_irqsave(&rme96->lock, flags);
2364 if (u->value.integer.value[0] != rme96->vol[0]) {
2365 rme96->vol[0] = u->value.integer.value[0];
2368 if (u->value.integer.value[1] != rme96->vol[1]) {
2369 rme96->vol[1] = u->value.integer.value[1];
2373 snd_rme96_apply_dac_volume(rme96);
2375 spin_unlock_irqrestore(&rme96->lock, flags);
2380 static snd_kcontrol_new_t snd_rme96_controls[] = {
2382 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2383 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2384 .info = snd_rme96_control_spdif_info,
2385 .get = snd_rme96_control_spdif_get,
2386 .put = snd_rme96_control_spdif_put
2389 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2390 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2391 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2392 .info = snd_rme96_control_spdif_stream_info,
2393 .get = snd_rme96_control_spdif_stream_get,
2394 .put = snd_rme96_control_spdif_stream_put
2397 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2398 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2399 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2400 .info = snd_rme96_control_spdif_mask_info,
2401 .get = snd_rme96_control_spdif_mask_get,
2402 .private_value = IEC958_AES0_NONAUDIO |
2403 IEC958_AES0_PROFESSIONAL |
2404 IEC958_AES0_CON_EMPHASIS
2407 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2408 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2409 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2410 .info = snd_rme96_control_spdif_mask_info,
2411 .get = snd_rme96_control_spdif_mask_get,
2412 .private_value = IEC958_AES0_NONAUDIO |
2413 IEC958_AES0_PROFESSIONAL |
2414 IEC958_AES0_PRO_EMPHASIS
2417 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2418 .name = "Input Connector",
2419 .info = snd_rme96_info_inputtype_control,
2420 .get = snd_rme96_get_inputtype_control,
2421 .put = snd_rme96_put_inputtype_control
2424 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2425 .name = "Loopback Input",
2426 .info = snd_rme96_info_loopback_control,
2427 .get = snd_rme96_get_loopback_control,
2428 .put = snd_rme96_put_loopback_control
2431 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2432 .name = "Sample Clock Source",
2433 .info = snd_rme96_info_clockmode_control,
2434 .get = snd_rme96_get_clockmode_control,
2435 .put = snd_rme96_put_clockmode_control
2438 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2439 .name = "Monitor Tracks",
2440 .info = snd_rme96_info_montracks_control,
2441 .get = snd_rme96_get_montracks_control,
2442 .put = snd_rme96_put_montracks_control
2445 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2446 .name = "Attenuation",
2447 .info = snd_rme96_info_attenuation_control,
2448 .get = snd_rme96_get_attenuation_control,
2449 .put = snd_rme96_put_attenuation_control
2452 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2453 .name = "DAC Playback Volume",
2454 .info = snd_rme96_dac_volume_info,
2455 .get = snd_rme96_dac_volume_get,
2456 .put = snd_rme96_dac_volume_put
2461 snd_rme96_create_switches(snd_card_t *card,
2465 snd_kcontrol_t *kctl;
2467 for (idx = 0; idx < 7; idx++) {
2468 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2470 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2471 rme96->spdif_ctl = kctl;
2474 if (RME96_HAS_ANALOG_OUT(rme96)) {
2475 for (idx = 7; idx < 10; idx++)
2476 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2484 * Card initialisation
2487 static void snd_rme96_card_free(snd_card_t *card)
2489 snd_rme96_free(card->private_data);
2492 static int __devinit
2493 snd_rme96_probe(struct pci_dev *pci,
2494 const struct pci_device_id *pci_id)
2502 if (dev >= SNDRV_CARDS) {
2509 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2510 sizeof(rme96_t))) == NULL)
2512 card->private_free = snd_rme96_card_free;
2513 rme96 = (rme96_t *)card->private_data;
2516 snd_card_set_dev(card, &pci->dev);
2517 if ((err = snd_rme96_create(rme96)) < 0) {
2518 snd_card_free(card);
2522 strcpy(card->driver, "Digi96");
2523 switch (rme96->pci->device) {
2524 case PCI_DEVICE_ID_DIGI96:
2525 strcpy(card->shortname, "RME Digi96");
2527 case PCI_DEVICE_ID_DIGI96_8:
2528 strcpy(card->shortname, "RME Digi96/8");
2530 case PCI_DEVICE_ID_DIGI96_8_PRO:
2531 strcpy(card->shortname, "RME Digi96/8 PRO");
2533 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2534 pci_read_config_byte(rme96->pci, 8, &val);
2536 strcpy(card->shortname, "RME Digi96/8 PAD");
2538 strcpy(card->shortname, "RME Digi96/8 PST");
2542 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2543 rme96->port, rme96->irq);
2545 if ((err = snd_card_register(card)) < 0) {
2546 snd_card_free(card);
2549 pci_set_drvdata(pci, card);
2554 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2556 snd_card_free(pci_get_drvdata(pci));
2557 pci_set_drvdata(pci, NULL);
2560 static struct pci_driver driver = {
2561 .name = "RME Digi96",
2562 .id_table = snd_rme96_ids,
2563 .probe = snd_rme96_probe,
2564 .remove = __devexit_p(snd_rme96_remove),
2567 static int __init alsa_card_rme96_init(void)
2569 return pci_module_init(&driver);
2572 static void __exit alsa_card_rme96_exit(void)
2574 pci_unregister_driver(&driver);
2577 module_init(alsa_card_rme96_init)
2578 module_exit(alsa_card_rme96_exit)