2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <sound/driver.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/asoundef.h>
40 #include <sound/initval.h>
44 /* note, two last pcis should be equal, it is not a bug */
46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
49 MODULE_LICENSE("GPL");
50 MODULE_CLASSES("{sound}");
51 MODULE_DEVICES("{{RME,Digi96},"
55 "{RME,Digi96/8 PAD}}");
57 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
58 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
59 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
61 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
62 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
63 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
64 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
65 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
66 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
67 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
68 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
69 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
72 * Defines for RME Digi96 series, from internal RME reference documents
76 #define RME96_SPDIF_NCHANNELS 2
78 /* Playback and capture buffer size */
79 #define RME96_BUFFER_SIZE 0x10000
82 #define RME96_IO_SIZE 0x60000
85 #define RME96_IO_PLAY_BUFFER 0x0
86 #define RME96_IO_REC_BUFFER 0x10000
87 #define RME96_IO_CONTROL_REGISTER 0x20000
88 #define RME96_IO_ADDITIONAL_REG 0x20004
89 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
90 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
91 #define RME96_IO_SET_PLAY_POS 0x40000
92 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
93 #define RME96_IO_SET_REC_POS 0x50000
94 #define RME96_IO_RESET_REC_POS 0x5FFFC
95 #define RME96_IO_GET_PLAY_POS 0x20000
96 #define RME96_IO_GET_REC_POS 0x30000
98 /* Write control register bits */
99 #define RME96_WCR_START (1 << 0)
100 #define RME96_WCR_START_2 (1 << 1)
101 #define RME96_WCR_GAIN_0 (1 << 2)
102 #define RME96_WCR_GAIN_1 (1 << 3)
103 #define RME96_WCR_MODE24 (1 << 4)
104 #define RME96_WCR_MODE24_2 (1 << 5)
105 #define RME96_WCR_BM (1 << 6)
106 #define RME96_WCR_BM_2 (1 << 7)
107 #define RME96_WCR_ADAT (1 << 8)
108 #define RME96_WCR_FREQ_0 (1 << 9)
109 #define RME96_WCR_FREQ_1 (1 << 10)
110 #define RME96_WCR_DS (1 << 11)
111 #define RME96_WCR_PRO (1 << 12)
112 #define RME96_WCR_EMP (1 << 13)
113 #define RME96_WCR_SEL (1 << 14)
114 #define RME96_WCR_MASTER (1 << 15)
115 #define RME96_WCR_PD (1 << 16)
116 #define RME96_WCR_INP_0 (1 << 17)
117 #define RME96_WCR_INP_1 (1 << 18)
118 #define RME96_WCR_THRU_0 (1 << 19)
119 #define RME96_WCR_THRU_1 (1 << 20)
120 #define RME96_WCR_THRU_2 (1 << 21)
121 #define RME96_WCR_THRU_3 (1 << 22)
122 #define RME96_WCR_THRU_4 (1 << 23)
123 #define RME96_WCR_THRU_5 (1 << 24)
124 #define RME96_WCR_THRU_6 (1 << 25)
125 #define RME96_WCR_THRU_7 (1 << 26)
126 #define RME96_WCR_DOLBY (1 << 27)
127 #define RME96_WCR_MONITOR_0 (1 << 28)
128 #define RME96_WCR_MONITOR_1 (1 << 29)
129 #define RME96_WCR_ISEL (1 << 30)
130 #define RME96_WCR_IDIS (1 << 31)
132 #define RME96_WCR_BITPOS_GAIN_0 2
133 #define RME96_WCR_BITPOS_GAIN_1 3
134 #define RME96_WCR_BITPOS_FREQ_0 9
135 #define RME96_WCR_BITPOS_FREQ_1 10
136 #define RME96_WCR_BITPOS_INP_0 17
137 #define RME96_WCR_BITPOS_INP_1 18
138 #define RME96_WCR_BITPOS_MONITOR_0 28
139 #define RME96_WCR_BITPOS_MONITOR_1 29
141 /* Read control register bits */
142 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
143 #define RME96_RCR_IRQ_2 (1 << 16)
144 #define RME96_RCR_T_OUT (1 << 17)
145 #define RME96_RCR_DEV_ID_0 (1 << 21)
146 #define RME96_RCR_DEV_ID_1 (1 << 22)
147 #define RME96_RCR_LOCK (1 << 23)
148 #define RME96_RCR_VERF (1 << 26)
149 #define RME96_RCR_F0 (1 << 27)
150 #define RME96_RCR_F1 (1 << 28)
151 #define RME96_RCR_F2 (1 << 29)
152 #define RME96_RCR_AUTOSYNC (1 << 30)
153 #define RME96_RCR_IRQ (1 << 31)
155 #define RME96_RCR_BITPOS_F0 27
156 #define RME96_RCR_BITPOS_F1 28
157 #define RME96_RCR_BITPOS_F2 29
159 /* Additonal register bits */
160 #define RME96_AR_WSEL (1 << 0)
161 #define RME96_AR_ANALOG (1 << 1)
162 #define RME96_AR_FREQPAD_0 (1 << 2)
163 #define RME96_AR_FREQPAD_1 (1 << 3)
164 #define RME96_AR_FREQPAD_2 (1 << 4)
165 #define RME96_AR_PD2 (1 << 5)
166 #define RME96_AR_DAC_EN (1 << 6)
167 #define RME96_AR_CLATCH (1 << 7)
168 #define RME96_AR_CCLK (1 << 8)
169 #define RME96_AR_CDATA (1 << 9)
171 #define RME96_AR_BITPOS_F0 2
172 #define RME96_AR_BITPOS_F1 3
173 #define RME96_AR_BITPOS_F2 4
176 #define RME96_MONITOR_TRACKS_1_2 0
177 #define RME96_MONITOR_TRACKS_3_4 1
178 #define RME96_MONITOR_TRACKS_5_6 2
179 #define RME96_MONITOR_TRACKS_7_8 3
182 #define RME96_ATTENUATION_0 0
183 #define RME96_ATTENUATION_6 1
184 #define RME96_ATTENUATION_12 2
185 #define RME96_ATTENUATION_18 3
188 #define RME96_INPUT_OPTICAL 0
189 #define RME96_INPUT_COAXIAL 1
190 #define RME96_INPUT_INTERNAL 2
191 #define RME96_INPUT_XLR 3
192 #define RME96_INPUT_ANALOG 4
195 #define RME96_CLOCKMODE_SLAVE 0
196 #define RME96_CLOCKMODE_MASTER 1
197 #define RME96_CLOCKMODE_WORDCLOCK 2
199 /* Block sizes in bytes */
200 #define RME96_SMALL_BLOCK_SIZE 2048
201 #define RME96_LARGE_BLOCK_SIZE 8192
204 #define RME96_AD1852_VOL_BITS 14
205 #define RME96_AD1855_VOL_BITS 10
208 * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
209 * therefore #ifndef is used.
211 #ifndef PCI_VENDOR_ID_XILINX
212 #define PCI_VENDOR_ID_XILINX 0x10ee
214 #ifndef PCI_DEVICE_ID_DIGI96
215 #define PCI_DEVICE_ID_DIGI96 0x3fc0
217 #ifndef PCI_DEVICE_ID_DIGI96_8
218 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1
220 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO
221 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
223 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
224 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
227 typedef struct snd_rme96 {
231 struct resource *res_port;
232 unsigned long iobase;
234 u32 wcreg; /* cached write control register value */
235 u32 wcreg_spdif; /* S/PDIF setup */
236 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
237 u32 rcreg; /* cached read control register value */
238 u32 areg; /* cached additional register value */
239 u16 vol[2]; /* cached volume of analog output */
241 u8 rev; /* card revision number */
243 snd_pcm_substream_t *playback_substream;
244 snd_pcm_substream_t *capture_substream;
246 int playback_frlog; /* log2 of framesize */
249 size_t playback_periodsize; /* in bytes, zero if not used */
250 size_t capture_periodsize; /* in bytes, zero if not used */
252 snd_pcm_uframes_t playback_last_appl_ptr;
257 snd_pcm_t *spdif_pcm;
260 snd_kcontrol_t *spdif_ctl;
263 static struct pci_device_id snd_rme96_ids[] = {
264 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
266 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
268 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
270 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
275 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
277 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
278 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
279 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
280 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
281 (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
282 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
283 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
284 ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
285 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
288 snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
291 snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
294 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
298 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
301 static snd_pcm_uframes_t
302 snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
304 static snd_pcm_uframes_t
305 snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
307 static void __devinit
308 snd_rme96_proc_init(rme96_t *rme96);
311 snd_rme96_create_switches(snd_card_t *card,
315 snd_rme96_getinputtype(rme96_t *rme96);
317 static inline unsigned int
318 snd_rme96_playback_ptr(rme96_t *rme96)
320 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
321 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
324 static inline unsigned int
325 snd_rme96_capture_ptr(rme96_t *rme96)
327 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
328 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
332 snd_rme96_ratecode(int rate)
335 case 32000: return SNDRV_PCM_RATE_32000;
336 case 44100: return SNDRV_PCM_RATE_44100;
337 case 48000: return SNDRV_PCM_RATE_48000;
338 case 64000: return SNDRV_PCM_RATE_64000;
339 case 88200: return SNDRV_PCM_RATE_88200;
340 case 96000: return SNDRV_PCM_RATE_96000;
346 snd_rme96_playback_silence(snd_pcm_substream_t *substream,
347 int channel, /* not used (interleaved data) */
348 snd_pcm_uframes_t pos,
349 snd_pcm_uframes_t count)
351 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
352 count <<= rme96->playback_frlog;
353 pos <<= rme96->playback_frlog;
354 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
360 snd_rme96_playback_copy(snd_pcm_substream_t *substream,
361 int channel, /* not used (interleaved data) */
362 snd_pcm_uframes_t pos,
364 snd_pcm_uframes_t count)
366 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
367 count <<= rme96->playback_frlog;
368 pos <<= rme96->playback_frlog;
369 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
375 snd_rme96_capture_copy(snd_pcm_substream_t *substream,
376 int channel, /* not used (interleaved data) */
377 snd_pcm_uframes_t pos,
379 snd_pcm_uframes_t count)
381 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
382 count <<= rme96->capture_frlog;
383 pos <<= rme96->capture_frlog;
384 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
390 * Digital output capabilites (S/PDIF)
392 static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
394 .info = (SNDRV_PCM_INFO_MMAP |
395 SNDRV_PCM_INFO_MMAP_VALID |
396 SNDRV_PCM_INFO_INTERLEAVED |
397 SNDRV_PCM_INFO_PAUSE),
398 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
399 SNDRV_PCM_FMTBIT_S32_LE),
400 .rates = (SNDRV_PCM_RATE_32000 |
401 SNDRV_PCM_RATE_44100 |
402 SNDRV_PCM_RATE_48000 |
403 SNDRV_PCM_RATE_64000 |
404 SNDRV_PCM_RATE_88200 |
405 SNDRV_PCM_RATE_96000),
410 .buffer_bytes_max = RME96_BUFFER_SIZE,
411 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
412 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
413 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
414 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
419 * Digital input capabilites (S/PDIF)
421 static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
423 .info = (SNDRV_PCM_INFO_MMAP |
424 SNDRV_PCM_INFO_MMAP_VALID |
425 SNDRV_PCM_INFO_INTERLEAVED |
426 SNDRV_PCM_INFO_PAUSE),
427 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
428 SNDRV_PCM_FMTBIT_S32_LE),
429 .rates = (SNDRV_PCM_RATE_32000 |
430 SNDRV_PCM_RATE_44100 |
431 SNDRV_PCM_RATE_48000 |
432 SNDRV_PCM_RATE_64000 |
433 SNDRV_PCM_RATE_88200 |
434 SNDRV_PCM_RATE_96000),
439 .buffer_bytes_max = RME96_BUFFER_SIZE,
440 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
441 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
442 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
443 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
448 * Digital output capabilites (ADAT)
450 static snd_pcm_hardware_t snd_rme96_playback_adat_info =
452 .info = (SNDRV_PCM_INFO_MMAP |
453 SNDRV_PCM_INFO_MMAP_VALID |
454 SNDRV_PCM_INFO_INTERLEAVED |
455 SNDRV_PCM_INFO_PAUSE),
456 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
457 SNDRV_PCM_FMTBIT_S32_LE),
458 .rates = (SNDRV_PCM_RATE_44100 |
459 SNDRV_PCM_RATE_48000),
464 .buffer_bytes_max = RME96_BUFFER_SIZE,
465 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
466 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
467 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
468 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
473 * Digital input capabilites (ADAT)
475 static snd_pcm_hardware_t snd_rme96_capture_adat_info =
477 .info = (SNDRV_PCM_INFO_MMAP |
478 SNDRV_PCM_INFO_MMAP_VALID |
479 SNDRV_PCM_INFO_INTERLEAVED |
480 SNDRV_PCM_INFO_PAUSE),
481 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
482 SNDRV_PCM_FMTBIT_S32_LE),
483 .rates = (SNDRV_PCM_RATE_44100 |
484 SNDRV_PCM_RATE_48000),
489 .buffer_bytes_max = RME96_BUFFER_SIZE,
490 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
491 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
492 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
493 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
498 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
499 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
500 * on the falling edge of CCLK and be stable on the rising edge. The rising
501 * edge of CLATCH after the last data bit clocks in the whole data word.
502 * A fast processor could probably drive the SPI interface faster than the
503 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
504 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
506 * NOTE: increased delay from 1 to 10, since there where problems setting
510 snd_rme96_write_SPI(rme96_t *rme96, u16 val)
514 for (i = 0; i < 16; i++) {
516 rme96->areg |= RME96_AR_CDATA;
518 rme96->areg &= ~RME96_AR_CDATA;
520 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
521 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
523 rme96->areg |= RME96_AR_CCLK;
524 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
528 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
529 rme96->areg |= RME96_AR_CLATCH;
530 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
532 rme96->areg &= ~RME96_AR_CLATCH;
533 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
537 snd_rme96_apply_dac_volume(rme96_t *rme96)
539 if (RME96_DAC_IS_1852(rme96)) {
540 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
541 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
542 } else if (RME96_DAC_IS_1855(rme96)) {
543 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
544 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
549 snd_rme96_reset_dac(rme96_t *rme96)
551 writel(rme96->wcreg | RME96_WCR_PD,
552 rme96->iobase + RME96_IO_CONTROL_REGISTER);
553 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
557 snd_rme96_getmontracks(rme96_t *rme96)
559 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
560 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
564 snd_rme96_setmontracks(rme96_t *rme96,
568 rme96->wcreg |= RME96_WCR_MONITOR_0;
570 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
573 rme96->wcreg |= RME96_WCR_MONITOR_1;
575 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
577 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
582 snd_rme96_getattenuation(rme96_t *rme96)
584 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
585 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
589 snd_rme96_setattenuation(rme96_t *rme96,
592 switch (attenuation) {
594 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
598 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
602 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
606 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
612 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
617 snd_rme96_capture_getrate(rme96_t *rme96,
623 if (rme96->areg & RME96_AR_ANALOG) {
624 /* Analog input, overrides S/PDIF setting */
625 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
626 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
640 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
643 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
644 if (rme96->rcreg & RME96_RCR_LOCK) {
647 if (rme96->rcreg & RME96_RCR_T_OUT) {
653 if (rme96->rcreg & RME96_RCR_VERF) {
658 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
659 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
660 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
664 if (rme96->rcreg & RME96_RCR_T_OUT) {
668 case 3: return 96000;
669 case 4: return 88200;
670 case 5: return 48000;
671 case 6: return 44100;
672 case 7: return 32000;
680 snd_rme96_playback_getrate(rme96_t *rme96)
684 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
685 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
686 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
691 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
692 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
706 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
710 snd_rme96_playback_setrate(rme96_t *rme96,
715 ds = rme96->wcreg & RME96_WCR_DS;
718 rme96->wcreg &= ~RME96_WCR_DS;
719 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
723 rme96->wcreg &= ~RME96_WCR_DS;
724 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
728 rme96->wcreg &= ~RME96_WCR_DS;
729 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
733 rme96->wcreg |= RME96_WCR_DS;
734 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
738 rme96->wcreg |= RME96_WCR_DS;
739 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
743 rme96->wcreg |= RME96_WCR_DS;
744 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
750 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
751 (ds && !(rme96->wcreg & RME96_WCR_DS)))
753 /* change to/from double-speed: reset the DAC (if available) */
754 snd_rme96_reset_dac(rme96);
756 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
762 snd_rme96_capture_analog_setrate(rme96_t *rme96,
767 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
768 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
771 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
772 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
775 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
776 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
779 if (rme96->rev < 4) {
782 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
783 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
786 if (rme96->rev < 4) {
789 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
790 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
793 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
794 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
799 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
804 snd_rme96_setclockmode(rme96_t *rme96,
808 case RME96_CLOCKMODE_SLAVE:
810 rme96->wcreg &= ~RME96_WCR_MASTER;
811 rme96->areg &= ~RME96_AR_WSEL;
813 case RME96_CLOCKMODE_MASTER:
815 rme96->wcreg |= RME96_WCR_MASTER;
816 rme96->areg &= ~RME96_AR_WSEL;
818 case RME96_CLOCKMODE_WORDCLOCK:
819 /* Word clock is a master mode */
820 rme96->wcreg |= RME96_WCR_MASTER;
821 rme96->areg |= RME96_AR_WSEL;
826 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
827 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
832 snd_rme96_getclockmode(rme96_t *rme96)
834 if (rme96->areg & RME96_AR_WSEL) {
835 return RME96_CLOCKMODE_WORDCLOCK;
837 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
838 RME96_CLOCKMODE_SLAVE;
842 snd_rme96_setinputtype(rme96_t *rme96,
848 case RME96_INPUT_OPTICAL:
849 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
852 case RME96_INPUT_COAXIAL:
853 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
856 case RME96_INPUT_INTERNAL:
857 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
860 case RME96_INPUT_XLR:
861 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
862 rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) ||
863 (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
866 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
869 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
872 case RME96_INPUT_ANALOG:
873 if (!RME96_HAS_ANALOG_IN(rme96)) {
876 rme96->areg |= RME96_AR_ANALOG;
877 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
878 if (rme96->rev < 4) {
880 * Revision less than 004 does not support 64 and
883 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
884 snd_rme96_capture_analog_setrate(rme96, 44100);
886 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
887 snd_rme96_capture_analog_setrate(rme96, 32000);
894 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
895 rme96->areg &= ~RME96_AR_ANALOG;
896 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
898 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
903 snd_rme96_getinputtype(rme96_t *rme96)
905 if (rme96->areg & RME96_AR_ANALOG) {
906 return RME96_INPUT_ANALOG;
908 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
909 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
913 snd_rme96_setframelog(rme96_t *rme96,
919 if (n_channels == 2) {
922 /* assume 8 channels */
926 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
927 rme96->playback_frlog = frlog;
929 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
930 rme96->capture_frlog = frlog;
935 snd_rme96_playback_setformat(rme96_t *rme96,
939 case SNDRV_PCM_FORMAT_S16_LE:
940 rme96->wcreg &= ~RME96_WCR_MODE24;
942 case SNDRV_PCM_FORMAT_S32_LE:
943 rme96->wcreg |= RME96_WCR_MODE24;
948 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
953 snd_rme96_capture_setformat(rme96_t *rme96,
957 case SNDRV_PCM_FORMAT_S16_LE:
958 rme96->wcreg &= ~RME96_WCR_MODE24_2;
960 case SNDRV_PCM_FORMAT_S32_LE:
961 rme96->wcreg |= RME96_WCR_MODE24_2;
966 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
971 snd_rme96_set_period_properties(rme96_t *rme96,
974 switch (period_bytes) {
975 case RME96_LARGE_BLOCK_SIZE:
976 rme96->wcreg &= ~RME96_WCR_ISEL;
978 case RME96_SMALL_BLOCK_SIZE:
979 rme96->wcreg |= RME96_WCR_ISEL;
985 rme96->wcreg &= ~RME96_WCR_IDIS;
986 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
990 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
991 snd_pcm_hw_params_t *params)
994 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
995 int err, rate, dummy;
997 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
999 spin_lock_irqsave(&rme96->lock, flags);
1000 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1001 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1002 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1005 if ((int)params_rate(params) != rate) {
1006 spin_unlock_irqrestore(&rme96->lock, flags);
1009 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1010 spin_unlock_irqrestore(&rme96->lock, flags);
1013 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1014 spin_unlock_irqrestore(&rme96->lock, flags);
1017 snd_rme96_setframelog(rme96, params_channels(params), 1);
1018 if (rme96->capture_periodsize != 0) {
1019 if (params_period_size(params) << rme96->playback_frlog !=
1020 rme96->capture_periodsize)
1022 spin_unlock_irqrestore(&rme96->lock, flags);
1026 rme96->playback_periodsize =
1027 params_period_size(params) << rme96->playback_frlog;
1028 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1030 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1031 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1032 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1034 spin_unlock_irqrestore(&rme96->lock, flags);
1040 snd_rme96_playback_hw_free(snd_pcm_substream_t *substream)
1042 snd_pcm_lib_free_pages(substream);
1047 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
1048 snd_pcm_hw_params_t *params)
1050 unsigned long flags;
1051 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1052 snd_pcm_runtime_t *runtime = substream->runtime;
1053 int err, isadat, rate;
1055 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
1057 spin_lock_irqsave(&rme96->lock, flags);
1058 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1059 spin_unlock_irqrestore(&rme96->lock, flags);
1062 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1063 if ((err = snd_rme96_capture_analog_setrate(rme96,
1064 params_rate(params))) < 0)
1066 spin_unlock_irqrestore(&rme96->lock, flags);
1069 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1070 if ((int)params_rate(params) != rate) {
1071 spin_unlock_irqrestore(&rme96->lock, flags);
1074 if ((isadat && runtime->hw.channels_min == 2) ||
1075 (!isadat && runtime->hw.channels_min == 8))
1077 spin_unlock_irqrestore(&rme96->lock, flags);
1081 snd_rme96_setframelog(rme96, params_channels(params), 0);
1082 if (rme96->playback_periodsize != 0) {
1083 if (params_period_size(params) << rme96->capture_frlog !=
1084 rme96->playback_periodsize)
1086 spin_unlock_irqrestore(&rme96->lock, flags);
1090 rme96->capture_periodsize =
1091 params_period_size(params) << rme96->capture_frlog;
1092 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1093 spin_unlock_irqrestore(&rme96->lock, flags);
1099 snd_rme96_capture_hw_free(snd_pcm_substream_t *substream)
1101 snd_pcm_lib_free_pages(substream);
1106 snd_rme96_playback_start(rme96_t *rme96,
1110 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1111 rme96->playback_last_appl_ptr = 0;
1112 rme96->playback_ptr = 0;
1115 rme96->wcreg |= RME96_WCR_START;
1116 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1120 snd_rme96_capture_start(rme96_t *rme96,
1124 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1125 rme96->capture_ptr = 0;
1128 rme96->wcreg |= RME96_WCR_START_2;
1129 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1133 snd_rme96_playback_stop(rme96_t *rme96)
1136 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1137 * the hardware will not stop generating interrupts
1139 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1140 if (rme96->rcreg & RME96_RCR_IRQ) {
1141 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1143 rme96->wcreg &= ~RME96_WCR_START;
1144 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1148 snd_rme96_capture_stop(rme96_t *rme96)
1150 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1151 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1152 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1154 rme96->wcreg &= ~RME96_WCR_START_2;
1155 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1159 snd_rme96_interrupt(int irq,
1161 struct pt_regs *regs)
1163 rme96_t *rme96 = (rme96_t *)dev_id;
1165 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1166 /* fastpath out, to ease interrupt sharing */
1167 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1168 (rme96->rcreg & RME96_RCR_IRQ_2)))
1173 if (rme96->rcreg & RME96_RCR_IRQ) {
1175 snd_pcm_period_elapsed(rme96->playback_substream);
1176 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1178 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1180 snd_pcm_period_elapsed(rme96->capture_substream);
1181 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1186 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1188 #define PERIOD_BYTES sizeof(period_bytes) / sizeof(period_bytes[0])
1190 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1191 .count = PERIOD_BYTES,
1192 .list = period_bytes,
1197 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1199 unsigned long flags;
1201 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1202 snd_pcm_runtime_t *runtime = substream->runtime;
1204 snd_pcm_set_sync(substream);
1206 spin_lock_irqsave(&rme96->lock, flags);
1207 if (rme96->playback_substream != NULL) {
1208 spin_unlock_irqrestore(&rme96->lock, flags);
1211 rme96->wcreg &= ~RME96_WCR_ADAT;
1212 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1213 rme96->playback_substream = substream;
1214 rme96->playback_last_appl_ptr = 0;
1215 rme96->playback_ptr = 0;
1216 spin_unlock_irqrestore(&rme96->lock, flags);
1218 runtime->hw = snd_rme96_playback_spdif_info;
1219 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1220 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1221 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1224 runtime->hw.rates = snd_rme96_ratecode(rate);
1225 runtime->hw.rate_min = rate;
1226 runtime->hw.rate_max = rate;
1228 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1229 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1231 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1232 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1233 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1234 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1239 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1241 unsigned long flags;
1243 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1244 snd_pcm_runtime_t *runtime = substream->runtime;
1246 snd_pcm_set_sync(substream);
1248 runtime->hw = snd_rme96_capture_spdif_info;
1249 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1250 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1255 runtime->hw.rates = snd_rme96_ratecode(rate);
1256 runtime->hw.rate_min = rate;
1257 runtime->hw.rate_max = rate;
1260 spin_lock_irqsave(&rme96->lock, flags);
1261 if (rme96->capture_substream != NULL) {
1262 spin_unlock_irqrestore(&rme96->lock, flags);
1265 rme96->capture_substream = substream;
1266 rme96->capture_ptr = 0;
1267 spin_unlock_irqrestore(&rme96->lock, flags);
1269 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1270 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1276 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1278 unsigned long flags;
1280 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1281 snd_pcm_runtime_t *runtime = substream->runtime;
1283 snd_pcm_set_sync(substream);
1285 spin_lock_irqsave(&rme96->lock, flags);
1286 if (rme96->playback_substream != NULL) {
1287 spin_unlock_irqrestore(&rme96->lock, flags);
1290 rme96->wcreg |= RME96_WCR_ADAT;
1291 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1292 rme96->playback_substream = substream;
1293 rme96->playback_last_appl_ptr = 0;
1294 rme96->playback_ptr = 0;
1295 spin_unlock_irqrestore(&rme96->lock, flags);
1297 runtime->hw = snd_rme96_playback_adat_info;
1298 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1299 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1300 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1303 runtime->hw.rates = snd_rme96_ratecode(rate);
1304 runtime->hw.rate_min = rate;
1305 runtime->hw.rate_max = rate;
1307 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1308 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1313 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1315 unsigned long flags;
1317 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1318 snd_pcm_runtime_t *runtime = substream->runtime;
1320 snd_pcm_set_sync(substream);
1322 runtime->hw = snd_rme96_capture_adat_info;
1323 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1324 /* makes no sense to use analog input. Note that analog
1325 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1328 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1332 runtime->hw.rates = snd_rme96_ratecode(rate);
1333 runtime->hw.rate_min = rate;
1334 runtime->hw.rate_max = rate;
1337 spin_lock_irqsave(&rme96->lock, flags);
1338 if (rme96->capture_substream != NULL) {
1339 spin_unlock_irqrestore(&rme96->lock, flags);
1342 rme96->capture_substream = substream;
1343 rme96->capture_ptr = 0;
1344 spin_unlock_irqrestore(&rme96->lock, flags);
1346 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1347 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1352 snd_rme96_playback_close(snd_pcm_substream_t *substream)
1354 unsigned long flags;
1355 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1358 spin_lock_irqsave(&rme96->lock, flags);
1359 if (RME96_ISPLAYING(rme96)) {
1360 snd_rme96_playback_stop(rme96);
1362 rme96->playback_substream = NULL;
1363 rme96->playback_periodsize = 0;
1364 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1365 spin_unlock_irqrestore(&rme96->lock, flags);
1367 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1368 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1369 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1375 snd_rme96_capture_close(snd_pcm_substream_t *substream)
1377 unsigned long flags;
1378 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1380 spin_lock_irqsave(&rme96->lock, flags);
1381 if (RME96_ISRECORDING(rme96)) {
1382 snd_rme96_capture_stop(rme96);
1384 rme96->capture_substream = NULL;
1385 rme96->capture_periodsize = 0;
1386 spin_unlock_irqrestore(&rme96->lock, flags);
1391 snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1393 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1394 unsigned long flags;
1396 spin_lock_irqsave(&rme96->lock, flags);
1397 if (RME96_ISPLAYING(rme96)) {
1398 snd_rme96_playback_stop(rme96);
1400 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1401 spin_unlock_irqrestore(&rme96->lock, flags);
1406 snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1408 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1409 unsigned long flags;
1411 spin_lock_irqsave(&rme96->lock, flags);
1412 if (RME96_ISRECORDING(rme96)) {
1413 snd_rme96_capture_stop(rme96);
1415 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1416 spin_unlock_irqrestore(&rme96->lock, flags);
1421 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1424 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1427 case SNDRV_PCM_TRIGGER_START:
1428 if (!RME96_ISPLAYING(rme96)) {
1429 if (substream != rme96->playback_substream) {
1432 snd_rme96_playback_start(rme96, 0);
1436 case SNDRV_PCM_TRIGGER_STOP:
1437 if (RME96_ISPLAYING(rme96)) {
1438 if (substream != rme96->playback_substream) {
1441 snd_rme96_playback_stop(rme96);
1445 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1446 if (RME96_ISPLAYING(rme96)) {
1447 snd_rme96_playback_stop(rme96);
1451 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1452 if (!RME96_ISPLAYING(rme96)) {
1453 snd_rme96_playback_start(rme96, 1);
1464 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1467 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1470 case SNDRV_PCM_TRIGGER_START:
1471 if (!RME96_ISRECORDING(rme96)) {
1472 if (substream != rme96->capture_substream) {
1475 snd_rme96_capture_start(rme96, 0);
1479 case SNDRV_PCM_TRIGGER_STOP:
1480 if (RME96_ISRECORDING(rme96)) {
1481 if (substream != rme96->capture_substream) {
1484 snd_rme96_capture_stop(rme96);
1488 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1489 if (RME96_ISRECORDING(rme96)) {
1490 snd_rme96_capture_stop(rme96);
1494 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1495 if (!RME96_ISRECORDING(rme96)) {
1496 snd_rme96_capture_start(rme96, 1);
1507 static snd_pcm_uframes_t
1508 snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1510 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1511 snd_pcm_runtime_t *runtime = substream->runtime;
1512 snd_pcm_sframes_t diff;
1515 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1516 diff = runtime->control->appl_ptr -
1517 rme96->playback_last_appl_ptr;
1518 rme96->playback_last_appl_ptr = runtime->control->appl_ptr;
1520 diff < -(snd_pcm_sframes_t)(runtime->boundary >> 1))
1522 diff += runtime->boundary;
1524 bytes = diff << rme96->playback_frlog;
1526 if (bytes > RME96_BUFFER_SIZE - rme96->playback_ptr) {
1527 memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER +
1528 rme96->playback_ptr),
1529 runtime->dma_area + rme96->playback_ptr,
1530 RME96_BUFFER_SIZE - rme96->playback_ptr);
1531 bytes -= RME96_BUFFER_SIZE - rme96->playback_ptr;
1532 if (bytes > RME96_BUFFER_SIZE) {
1533 bytes = RME96_BUFFER_SIZE;
1535 memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER),
1538 rme96->playback_ptr = bytes;
1539 } else if (bytes != 0) {
1540 memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER +
1541 rme96->playback_ptr),
1542 runtime->dma_area + rme96->playback_ptr,
1544 rme96->playback_ptr += bytes;
1547 return snd_rme96_playback_ptr(rme96);
1550 static snd_pcm_uframes_t
1551 snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1553 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1554 snd_pcm_runtime_t *runtime = substream->runtime;
1555 snd_pcm_uframes_t frameptr;
1558 frameptr = snd_rme96_capture_ptr(rme96);
1559 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1560 ptr = frameptr << rme96->capture_frlog;
1561 if (ptr > rme96->capture_ptr) {
1562 memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1563 (void *)(rme96->iobase + RME96_IO_REC_BUFFER +
1564 rme96->capture_ptr),
1565 ptr - rme96->capture_ptr);
1566 rme96->capture_ptr += ptr - rme96->capture_ptr;
1567 } else if (ptr < rme96->capture_ptr) {
1568 memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1569 (void *)(rme96->iobase + RME96_IO_REC_BUFFER +
1570 rme96->capture_ptr),
1571 RME96_BUFFER_SIZE - rme96->capture_ptr);
1572 memcpy_fromio(runtime->dma_area,
1573 (void *)(rme96->iobase + RME96_IO_REC_BUFFER),
1575 rme96->capture_ptr = ptr;
1581 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1582 .open = snd_rme96_playback_spdif_open,
1583 .close = snd_rme96_playback_close,
1584 .ioctl = snd_pcm_lib_ioctl,
1585 .hw_params = snd_rme96_playback_hw_params,
1586 .hw_free = snd_rme96_playback_hw_free,
1587 .prepare = snd_rme96_playback_prepare,
1588 .trigger = snd_rme96_playback_trigger,
1589 .pointer = snd_rme96_playback_pointer,
1590 .copy = snd_rme96_playback_copy,
1591 .silence = snd_rme96_playback_silence,
1594 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1595 .open = snd_rme96_capture_spdif_open,
1596 .close = snd_rme96_capture_close,
1597 .ioctl = snd_pcm_lib_ioctl,
1598 .hw_params = snd_rme96_capture_hw_params,
1599 .hw_free = snd_rme96_capture_hw_free,
1600 .prepare = snd_rme96_capture_prepare,
1601 .trigger = snd_rme96_capture_trigger,
1602 .pointer = snd_rme96_capture_pointer,
1603 .copy = snd_rme96_capture_copy,
1606 static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1607 .open = snd_rme96_playback_adat_open,
1608 .close = snd_rme96_playback_close,
1609 .ioctl = snd_pcm_lib_ioctl,
1610 .hw_params = snd_rme96_playback_hw_params,
1611 .hw_free = snd_rme96_playback_hw_free,
1612 .prepare = snd_rme96_playback_prepare,
1613 .trigger = snd_rme96_playback_trigger,
1614 .pointer = snd_rme96_playback_pointer,
1615 .copy = snd_rme96_playback_copy,
1616 .silence = snd_rme96_playback_silence,
1619 static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1620 .open = snd_rme96_capture_adat_open,
1621 .close = snd_rme96_capture_close,
1622 .ioctl = snd_pcm_lib_ioctl,
1623 .hw_params = snd_rme96_capture_hw_params,
1624 .hw_free = snd_rme96_capture_hw_free,
1625 .prepare = snd_rme96_capture_prepare,
1626 .trigger = snd_rme96_capture_trigger,
1627 .pointer = snd_rme96_capture_pointer,
1628 .copy = snd_rme96_capture_copy,
1632 snd_rme96_free(void *private_data)
1634 rme96_t *rme96 = (rme96_t *)private_data;
1636 if (rme96 == NULL) {
1639 if (rme96->irq >= 0) {
1640 snd_rme96_playback_stop(rme96);
1641 snd_rme96_capture_stop(rme96);
1642 rme96->areg &= ~RME96_AR_DAC_EN;
1643 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1644 free_irq(rme96->irq, (void *)rme96);
1647 if (rme96->iobase) {
1648 iounmap((void *)rme96->iobase);
1651 if (rme96->res_port != NULL) {
1652 release_resource(rme96->res_port);
1653 kfree_nocheck(rme96->res_port);
1654 rme96->res_port = NULL;
1659 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1661 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1662 rme96->spdif_pcm = NULL;
1663 snd_pcm_lib_preallocate_free_for_all(pcm);
1667 snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1669 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1670 rme96->adat_pcm = NULL;
1671 snd_pcm_lib_preallocate_free_for_all(pcm);
1674 static int __devinit
1675 snd_rme96_create(rme96_t *rme96)
1677 struct pci_dev *pci = rme96->pci;
1682 if ((err = pci_enable_device(pci)) < 0)
1685 rme96->port = pci_resource_start(rme96->pci, 0);
1687 if ((rme96->res_port = request_mem_region(rme96->port, RME96_IO_SIZE, "RME96")) == NULL) {
1688 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1692 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1693 snd_printk("unable to grab IRQ %d\n", pci->irq);
1696 rme96->irq = pci->irq;
1698 spin_lock_init(&rme96->lock);
1699 if ((rme96->iobase = (unsigned long) ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1700 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1704 /* read the card's revision number */
1705 pci_read_config_byte(pci, 8, &rme96->rev);
1707 /* set up ALSA pcm device for S/PDIF */
1708 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1709 1, 1, &rme96->spdif_pcm)) < 0)
1713 rme96->spdif_pcm->private_data = rme96;
1714 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1715 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1716 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1717 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1719 rme96->spdif_pcm->info_flags = 0;
1721 snd_pcm_lib_preallocate_pages_for_all(rme96->spdif_pcm,
1722 SNDRV_DMA_TYPE_CONTINUOUS,
1723 snd_dma_continuous_data(GFP_KERNEL),
1727 /* set up ALSA pcm device for ADAT */
1728 if (pci->device == PCI_DEVICE_ID_DIGI96) {
1729 /* ADAT is not available on the base model */
1730 rme96->adat_pcm = NULL;
1732 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1733 1, 1, &rme96->adat_pcm)) < 0)
1737 rme96->adat_pcm->private_data = rme96;
1738 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1739 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1740 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1741 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1743 rme96->adat_pcm->info_flags = 0;
1745 snd_pcm_lib_preallocate_pages_for_all(rme96->adat_pcm,
1746 SNDRV_DMA_TYPE_CONTINUOUS,
1747 snd_dma_continuous_data(GFP_KERNEL),
1752 rme96->playback_periodsize = 0;
1753 rme96->capture_periodsize = 0;
1755 /* make sure playback/capture is stopped, if by some reason active */
1756 snd_rme96_playback_stop(rme96);
1757 snd_rme96_capture_stop(rme96);
1759 /* set default values in registers */
1761 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1762 RME96_WCR_SEL | /* normal playback */
1763 RME96_WCR_MASTER | /* set to master clock mode */
1764 RME96_WCR_INP_0; /* set coaxial input */
1766 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1768 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1769 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1772 writel(rme96->areg | RME96_AR_PD2,
1773 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1774 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1776 /* reset and enable the DAC (order is important). */
1777 snd_rme96_reset_dac(rme96);
1778 rme96->areg |= RME96_AR_DAC_EN;
1779 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1781 /* reset playback and record buffer pointers */
1782 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1783 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1786 rme96->vol[0] = rme96->vol[1] = 0;
1787 if (RME96_HAS_ANALOG_OUT(rme96)) {
1788 snd_rme96_apply_dac_volume(rme96);
1791 /* init switch interface */
1792 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1796 /* init proc interface */
1797 snd_rme96_proc_init(rme96);
1807 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1810 rme96_t *rme96 = (rme96_t *)entry->private_data;
1812 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1814 snd_iprintf(buffer, rme96->card->longname);
1815 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1817 snd_iprintf(buffer, "\nGeneral settings\n");
1818 if (rme96->wcreg & RME96_WCR_IDIS) {
1819 snd_iprintf(buffer, " period size: N/A (interrupts "
1821 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1822 snd_iprintf(buffer, " period size: 2048 bytes\n");
1824 snd_iprintf(buffer, " period size: 8192 bytes\n");
1826 snd_iprintf(buffer, "\nInput settings\n");
1827 switch (snd_rme96_getinputtype(rme96)) {
1828 case RME96_INPUT_OPTICAL:
1829 snd_iprintf(buffer, " input: optical");
1831 case RME96_INPUT_COAXIAL:
1832 snd_iprintf(buffer, " input: coaxial");
1834 case RME96_INPUT_INTERNAL:
1835 snd_iprintf(buffer, " input: internal");
1837 case RME96_INPUT_XLR:
1838 snd_iprintf(buffer, " input: XLR");
1840 case RME96_INPUT_ANALOG:
1841 snd_iprintf(buffer, " input: analog");
1844 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1845 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1848 snd_iprintf(buffer, " (8 channels)\n");
1850 snd_iprintf(buffer, " (2 channels)\n");
1852 snd_iprintf(buffer, " sample rate: %d Hz\n",
1853 snd_rme96_capture_getrate(rme96, &n));
1855 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1856 snd_iprintf(buffer, " sample format: 24 bit\n");
1858 snd_iprintf(buffer, " sample format: 16 bit\n");
1861 snd_iprintf(buffer, "\nOutput settings\n");
1862 if (rme96->wcreg & RME96_WCR_SEL) {
1863 snd_iprintf(buffer, " output signal: normal playback\n");
1865 snd_iprintf(buffer, " output signal: same as input\n");
1867 snd_iprintf(buffer, " sample rate: %d Hz\n",
1868 snd_rme96_playback_getrate(rme96));
1869 if (rme96->wcreg & RME96_WCR_MODE24) {
1870 snd_iprintf(buffer, " sample format: 24 bit\n");
1872 snd_iprintf(buffer, " sample format: 16 bit\n");
1874 if (rme96->areg & RME96_AR_WSEL) {
1875 snd_iprintf(buffer, " sample clock source: word clock\n");
1876 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1877 snd_iprintf(buffer, " sample clock source: internal\n");
1878 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1879 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1880 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1881 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1883 snd_iprintf(buffer, " sample clock source: autosync\n");
1885 if (rme96->wcreg & RME96_WCR_PRO) {
1886 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1888 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1890 if (rme96->wcreg & RME96_WCR_EMP) {
1891 snd_iprintf(buffer, " emphasis: on\n");
1893 snd_iprintf(buffer, " emphasis: off\n");
1895 if (rme96->wcreg & RME96_WCR_DOLBY) {
1896 snd_iprintf(buffer, " non-audio (dolby): on\n");
1898 snd_iprintf(buffer, " non-audio (dolby): off\n");
1900 if (RME96_HAS_ANALOG_IN(rme96)) {
1901 snd_iprintf(buffer, "\nAnalog output settings\n");
1902 switch (snd_rme96_getmontracks(rme96)) {
1903 case RME96_MONITOR_TRACKS_1_2:
1904 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1906 case RME96_MONITOR_TRACKS_3_4:
1907 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1909 case RME96_MONITOR_TRACKS_5_6:
1910 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1912 case RME96_MONITOR_TRACKS_7_8:
1913 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1916 switch (snd_rme96_getattenuation(rme96)) {
1917 case RME96_ATTENUATION_0:
1918 snd_iprintf(buffer, " attenuation: 0 dB\n");
1920 case RME96_ATTENUATION_6:
1921 snd_iprintf(buffer, " attenuation: -6 dB\n");
1923 case RME96_ATTENUATION_12:
1924 snd_iprintf(buffer, " attenuation: -12 dB\n");
1926 case RME96_ATTENUATION_18:
1927 snd_iprintf(buffer, " attenuation: -18 dB\n");
1930 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1931 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1935 static void __devinit
1936 snd_rme96_proc_init(rme96_t *rme96)
1938 snd_info_entry_t *entry;
1940 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1941 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1949 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1951 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1953 uinfo->value.integer.min = 0;
1954 uinfo->value.integer.max = 1;
1958 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1960 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1961 unsigned long flags;
1963 spin_lock_irqsave(&rme96->lock, flags);
1964 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1965 spin_unlock_irqrestore(&rme96->lock, flags);
1969 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1971 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1972 unsigned long flags;
1976 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1977 spin_lock_irqsave(&rme96->lock, flags);
1978 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1979 change = val != rme96->wcreg;
1980 writel(rme96->wcreg = val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1981 spin_unlock_irqrestore(&rme96->lock, flags);
1986 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1988 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1989 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1990 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1992 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1994 switch (rme96->pci->device) {
1995 case PCI_DEVICE_ID_DIGI96:
1996 case PCI_DEVICE_ID_DIGI96_8:
1997 uinfo->value.enumerated.items = 3;
1999 case PCI_DEVICE_ID_DIGI96_8_PRO:
2000 uinfo->value.enumerated.items = 4;
2002 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2003 if (rme96->rev > 4) {
2005 uinfo->value.enumerated.items = 4;
2006 texts[3] = _texts[4]; /* Analog instead of XLR */
2009 uinfo->value.enumerated.items = 5;
2016 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
2017 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2019 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2023 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2025 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2026 unsigned long flags;
2027 unsigned int items = 3;
2029 spin_lock_irqsave(&rme96->lock, flags);
2030 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
2032 switch (rme96->pci->device) {
2033 case PCI_DEVICE_ID_DIGI96:
2034 case PCI_DEVICE_ID_DIGI96_8:
2037 case PCI_DEVICE_ID_DIGI96_8_PRO:
2040 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2041 if (rme96->rev > 4) {
2042 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
2043 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
2044 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
2055 if (ucontrol->value.enumerated.item[0] >= items) {
2056 ucontrol->value.enumerated.item[0] = items - 1;
2059 spin_unlock_irqrestore(&rme96->lock, flags);
2063 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2065 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2066 unsigned long flags;
2068 int change, items = 3;
2070 switch (rme96->pci->device) {
2071 case PCI_DEVICE_ID_DIGI96:
2072 case PCI_DEVICE_ID_DIGI96_8:
2075 case PCI_DEVICE_ID_DIGI96_8_PRO:
2078 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2079 if (rme96->rev > 4) {
2089 val = ucontrol->value.enumerated.item[0] % items;
2091 /* special case for PST */
2092 if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
2093 if (val == RME96_INPUT_XLR) {
2094 val = RME96_INPUT_ANALOG;
2098 spin_lock_irqsave(&rme96->lock, flags);
2099 change = (int)val != snd_rme96_getinputtype(rme96);
2100 snd_rme96_setinputtype(rme96, val);
2101 spin_unlock_irqrestore(&rme96->lock, flags);
2106 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2108 static char *texts[3] = { "AutoSync", "Internal", "Word" };
2110 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2112 uinfo->value.enumerated.items = 3;
2113 if (uinfo->value.enumerated.item > 2) {
2114 uinfo->value.enumerated.item = 2;
2116 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2120 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2122 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2123 unsigned long flags;
2125 spin_lock_irqsave(&rme96->lock, flags);
2126 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2127 spin_unlock_irqrestore(&rme96->lock, flags);
2131 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2133 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2134 unsigned long flags;
2138 val = ucontrol->value.enumerated.item[0] % 3;
2139 spin_lock_irqsave(&rme96->lock, flags);
2140 change = (int)val != snd_rme96_getclockmode(rme96);
2141 snd_rme96_setclockmode(rme96, val);
2142 spin_unlock_irqrestore(&rme96->lock, flags);
2147 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2149 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2151 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2153 uinfo->value.enumerated.items = 4;
2154 if (uinfo->value.enumerated.item > 3) {
2155 uinfo->value.enumerated.item = 3;
2157 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2161 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2163 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2164 unsigned long flags;
2166 spin_lock_irqsave(&rme96->lock, flags);
2167 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2168 spin_unlock_irqrestore(&rme96->lock, flags);
2172 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2174 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2175 unsigned long flags;
2179 val = ucontrol->value.enumerated.item[0] % 4;
2180 spin_lock_irqsave(&rme96->lock, flags);
2182 change = (int)val != snd_rme96_getattenuation(rme96);
2183 snd_rme96_setattenuation(rme96, val);
2184 spin_unlock_irqrestore(&rme96->lock, flags);
2189 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2191 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2193 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2195 uinfo->value.enumerated.items = 4;
2196 if (uinfo->value.enumerated.item > 3) {
2197 uinfo->value.enumerated.item = 3;
2199 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2203 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2205 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2206 unsigned long flags;
2208 spin_lock_irqsave(&rme96->lock, flags);
2209 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2210 spin_unlock_irqrestore(&rme96->lock, flags);
2214 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2216 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2217 unsigned long flags;
2221 val = ucontrol->value.enumerated.item[0] % 4;
2222 spin_lock_irqsave(&rme96->lock, flags);
2223 change = (int)val != snd_rme96_getmontracks(rme96);
2224 snd_rme96_setmontracks(rme96, val);
2225 spin_unlock_irqrestore(&rme96->lock, flags);
2229 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2232 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2233 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2234 if (val & RME96_WCR_PRO)
2235 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2237 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2241 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2243 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2244 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2245 if (val & RME96_WCR_PRO)
2246 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2248 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2251 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2253 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2258 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2260 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2262 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2266 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2268 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2269 unsigned long flags;
2273 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2274 spin_lock_irqsave(&rme96->lock, flags);
2275 change = val != rme96->wcreg_spdif;
2276 rme96->wcreg_spdif = val;
2277 spin_unlock_irqrestore(&rme96->lock, flags);
2281 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2283 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2288 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2290 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2292 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2296 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2298 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2299 unsigned long flags;
2303 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2304 spin_lock_irqsave(&rme96->lock, flags);
2305 change = val != rme96->wcreg_spdif_stream;
2306 rme96->wcreg_spdif_stream = val;
2307 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2308 writel(rme96->wcreg |= val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2309 spin_unlock_irqrestore(&rme96->lock, flags);
2313 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2315 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2320 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2322 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2327 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2329 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2331 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2333 uinfo->value.integer.min = 0;
2334 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2339 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2341 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2342 unsigned long flags;
2344 spin_lock_irqsave(&rme96->lock, flags);
2345 u->value.integer.value[0] = rme96->vol[0];
2346 u->value.integer.value[1] = rme96->vol[1];
2347 spin_unlock_irqrestore(&rme96->lock, flags);
2353 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2355 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2356 unsigned long flags;
2359 if (!RME96_HAS_ANALOG_OUT(rme96)) {
2362 spin_lock_irqsave(&rme96->lock, flags);
2363 if (u->value.integer.value[0] != rme96->vol[0]) {
2364 rme96->vol[0] = u->value.integer.value[0];
2367 if (u->value.integer.value[1] != rme96->vol[1]) {
2368 rme96->vol[1] = u->value.integer.value[1];
2372 snd_rme96_apply_dac_volume(rme96);
2374 spin_unlock_irqrestore(&rme96->lock, flags);
2379 static snd_kcontrol_new_t snd_rme96_controls[] = {
2381 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2382 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2383 .info = snd_rme96_control_spdif_info,
2384 .get = snd_rme96_control_spdif_get,
2385 .put = snd_rme96_control_spdif_put
2388 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2389 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2390 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2391 .info = snd_rme96_control_spdif_stream_info,
2392 .get = snd_rme96_control_spdif_stream_get,
2393 .put = snd_rme96_control_spdif_stream_put
2396 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2397 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2398 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2399 .info = snd_rme96_control_spdif_mask_info,
2400 .get = snd_rme96_control_spdif_mask_get,
2401 .private_value = IEC958_AES0_NONAUDIO |
2402 IEC958_AES0_PROFESSIONAL |
2403 IEC958_AES0_CON_EMPHASIS
2406 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2407 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2408 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2409 .info = snd_rme96_control_spdif_mask_info,
2410 .get = snd_rme96_control_spdif_mask_get,
2411 .private_value = IEC958_AES0_NONAUDIO |
2412 IEC958_AES0_PROFESSIONAL |
2413 IEC958_AES0_PRO_EMPHASIS
2416 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2417 .name = "Input Connector",
2418 .info = snd_rme96_info_inputtype_control,
2419 .get = snd_rme96_get_inputtype_control,
2420 .put = snd_rme96_put_inputtype_control
2423 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2424 .name = "Loopback Input",
2425 .info = snd_rme96_info_loopback_control,
2426 .get = snd_rme96_get_loopback_control,
2427 .put = snd_rme96_put_loopback_control
2430 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2431 .name = "Sample Clock Source",
2432 .info = snd_rme96_info_clockmode_control,
2433 .get = snd_rme96_get_clockmode_control,
2434 .put = snd_rme96_put_clockmode_control
2437 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2438 .name = "Monitor Tracks",
2439 .info = snd_rme96_info_montracks_control,
2440 .get = snd_rme96_get_montracks_control,
2441 .put = snd_rme96_put_montracks_control
2444 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2445 .name = "Attenuation",
2446 .info = snd_rme96_info_attenuation_control,
2447 .get = snd_rme96_get_attenuation_control,
2448 .put = snd_rme96_put_attenuation_control
2451 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2452 .name = "DAC Playback Volume",
2453 .info = snd_rme96_dac_volume_info,
2454 .get = snd_rme96_dac_volume_get,
2455 .put = snd_rme96_dac_volume_put
2460 snd_rme96_create_switches(snd_card_t *card,
2464 snd_kcontrol_t *kctl;
2466 for (idx = 0; idx < 7; idx++) {
2467 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2469 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2470 rme96->spdif_ctl = kctl;
2473 if (RME96_HAS_ANALOG_OUT(rme96)) {
2474 for (idx = 7; idx < 10; idx++)
2475 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2483 * Card initialisation
2486 static void snd_rme96_card_free(snd_card_t *card)
2488 snd_rme96_free(card->private_data);
2491 static int __devinit
2492 snd_rme96_probe(struct pci_dev *pci,
2493 const struct pci_device_id *pci_id)
2501 if (dev >= SNDRV_CARDS) {
2508 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2509 sizeof(rme96_t))) == NULL)
2511 card->private_free = snd_rme96_card_free;
2512 rme96 = (rme96_t *)card->private_data;
2515 snd_card_set_dev(card, &pci->dev);
2516 if ((err = snd_rme96_create(rme96)) < 0) {
2517 snd_card_free(card);
2521 strcpy(card->driver, "Digi96");
2522 switch (rme96->pci->device) {
2523 case PCI_DEVICE_ID_DIGI96:
2524 strcpy(card->shortname, "RME Digi96");
2526 case PCI_DEVICE_ID_DIGI96_8:
2527 strcpy(card->shortname, "RME Digi96/8");
2529 case PCI_DEVICE_ID_DIGI96_8_PRO:
2530 strcpy(card->shortname, "RME Digi96/8 PRO");
2532 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2533 pci_read_config_byte(rme96->pci, 8, &val);
2535 strcpy(card->shortname, "RME Digi96/8 PAD");
2537 strcpy(card->shortname, "RME Digi96/8 PST");
2541 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2542 rme96->port, rme96->irq);
2544 if ((err = snd_card_register(card)) < 0) {
2545 snd_card_free(card);
2548 pci_set_drvdata(pci, card);
2553 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2555 snd_card_free(pci_get_drvdata(pci));
2556 pci_set_drvdata(pci, NULL);
2559 static struct pci_driver driver = {
2560 .name = "RME Digi96",
2561 .id_table = snd_rme96_ids,
2562 .probe = snd_rme96_probe,
2563 .remove = __devexit_p(snd_rme96_remove),
2566 static int __init alsa_card_rme96_init(void)
2570 if ((err = pci_module_init(&driver)) < 0) {
2572 printk(KERN_ERR "No RME Digi96 cards found\n");
2579 static void __exit alsa_card_rme96_exit(void)
2581 pci_unregister_driver(&driver);
2584 module_init(alsa_card_rme96_init)
2585 module_exit(alsa_card_rme96_exit)
2589 /* format is: snd-rme96=enable,index,id */
2591 static int __init alsa_card_rme96_setup(char *str)
2593 static unsigned __initdata nr_dev = 0;
2595 if (nr_dev >= SNDRV_CARDS)
2597 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2598 get_option(&str,&index[nr_dev]) == 2 &&
2599 get_id(&str,&id[nr_dev]) == 2);
2604 __setup("snd-rme96=", alsa_card_rme96_setup);
2606 #endif /* ifndef MODULE */