2 * ALSA driver for RME Hammerfall DSP audio interface(s)
4 * Copyright (c) 2002 Paul Davis
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/moduleparam.h>
32 #include <sound/core.h>
33 #include <sound/control.h>
34 #include <sound/pcm.h>
35 #include <sound/info.h>
36 #include <sound/asoundef.h>
37 #include <sound/rawmidi.h>
38 #include <sound/hwdep.h>
39 #include <sound/initval.h>
40 #include <sound/hdsp.h>
42 #include <asm/byteorder.h>
43 #include <asm/current.h>
46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
49 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
50 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
53 module_param_array(index, int, boot_devs, 0444);
54 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
55 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
56 module_param_array(id, charp, boot_devs, 0444);
57 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
58 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
59 module_param_array(enable, bool, boot_devs, 0444);
60 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
61 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
62 module_param_array(precise_ptr, bool, boot_devs, 0444);
63 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
64 MODULE_PARM_SYNTAX(precise_ptr, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
65 module_param_array(line_outs_monitor, bool, boot_devs, 0444);
66 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
67 MODULE_PARM_SYNTAX(line_outs_monitor, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
68 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
69 MODULE_DESCRIPTION("RME Hammerfall DSP");
70 MODULE_LICENSE("GPL");
71 MODULE_CLASSES("{sound}");
72 MODULE_DEVICES("{{RME Hammerfall-DSP},"
76 #define HDSP_MAX_CHANNELS 26
77 #define HDSP_MAX_DS_CHANNELS 14
78 #define HDSP_MAX_QS_CHANNELS 8
79 #define DIGIFACE_SS_CHANNELS 26
80 #define DIGIFACE_DS_CHANNELS 14
81 #define MULTIFACE_SS_CHANNELS 18
82 #define MULTIFACE_DS_CHANNELS 14
83 #define H9652_SS_CHANNELS 26
84 #define H9652_DS_CHANNELS 14
85 /* This does not include possible Analog Extension Boards
86 AEBs are detected at card initialization
88 #define H9632_SS_CHANNELS 12
89 #define H9632_DS_CHANNELS 8
90 #define H9632_QS_CHANNELS 4
92 /* Write registers. These are defined as byte-offsets from the iobase value.
94 #define HDSP_resetPointer 0
95 #define HDSP_outputBufferAddress 32
96 #define HDSP_inputBufferAddress 36
97 #define HDSP_controlRegister 64
98 #define HDSP_interruptConfirmation 96
99 #define HDSP_outputEnable 128
100 #define HDSP_control2Reg 256
101 #define HDSP_midiDataOut0 352
102 #define HDSP_midiDataOut1 356
103 #define HDSP_fifoData 368
104 #define HDSP_inputEnable 384
106 /* Read registers. These are defined as byte-offsets from the iobase value
109 #define HDSP_statusRegister 0
110 #define HDSP_timecode 128
111 #define HDSP_status2Register 192
112 #define HDSP_midiDataOut0 352
113 #define HDSP_midiDataOut1 356
114 #define HDSP_midiDataIn0 360
115 #define HDSP_midiDataIn1 364
116 #define HDSP_midiStatusOut0 384
117 #define HDSP_midiStatusOut1 388
118 #define HDSP_midiStatusIn0 392
119 #define HDSP_midiStatusIn1 396
120 #define HDSP_fifoStatus 400
122 /* the meters are regular i/o-mapped registers, but offset
123 considerably from the rest. the peak registers are reset
124 when read; the least-significant 4 bits are full-scale counters;
125 the actual peak value is in the most-significant 24 bits.
128 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
129 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
130 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
131 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
132 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
135 /* This is for H9652 cards
136 Peak values are read downward from the base
137 Rms values are read upward
138 There are rms values for the outputs too
139 26*3 values are read in ss mode
140 14*3 in ds mode, with no gap between values
142 #define HDSP_9652_peakBase 7164
143 #define HDSP_9652_rmsBase 4096
145 /* c.f. the hdsp_9632_meters_t struct */
146 #define HDSP_9632_metersBase 4096
148 #define HDSP_IO_EXTENT 7168
150 /* control2 register bits */
152 #define HDSP_TMS 0x01
153 #define HDSP_TCK 0x02
154 #define HDSP_TDI 0x04
155 #define HDSP_JTAG 0x08
156 #define HDSP_PWDN 0x10
157 #define HDSP_PROGRAM 0x020
158 #define HDSP_CONFIG_MODE_0 0x040
159 #define HDSP_CONFIG_MODE_1 0x080
160 #define HDSP_VERSION_BIT 0x100
161 #define HDSP_BIGENDIAN_MODE 0x200
162 #define HDSP_RD_MULTIPLE 0x400
163 #define HDSP_9652_ENABLE_MIXER 0x800
164 #define HDSP_TDO 0x10000000
166 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
167 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
169 /* Control Register bits */
171 #define HDSP_Start (1<<0) /* start engine */
172 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
173 #define HDSP_Latency1 (1<<2) /* [ see above ] */
174 #define HDSP_Latency2 (1<<3) /* [ see above ] */
175 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
176 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
177 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
178 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
179 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
180 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
181 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
182 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
183 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
184 #define HDSP_SyncRef2 (1<<13)
185 #define HDSP_SPDIFInputSelect0 (1<<14)
186 #define HDSP_SPDIFInputSelect1 (1<<15)
187 #define HDSP_SyncRef0 (1<<16)
188 #define HDSP_SyncRef1 (1<<17)
189 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
190 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
191 #define HDSP_Midi0InterruptEnable (1<<22)
192 #define HDSP_Midi1InterruptEnable (1<<23)
193 #define HDSP_LineOut (1<<24)
194 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
195 #define HDSP_ADGain1 (1<<26)
196 #define HDSP_DAGain0 (1<<27)
197 #define HDSP_DAGain1 (1<<28)
198 #define HDSP_PhoneGain0 (1<<29)
199 #define HDSP_PhoneGain1 (1<<30)
200 #define HDSP_QuadSpeed (1<<31)
202 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
203 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
204 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
205 #define HDSP_ADGainLowGain 0
207 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
208 #define HDSP_DAGainHighGain HDSP_DAGainMask
209 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
210 #define HDSP_DAGainMinus10dBV 0
212 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
213 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
214 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
215 #define HDSP_PhoneGainMinus12dB 0
217 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
218 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
220 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
221 #define HDSP_SPDIFInputADAT1 0
222 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
223 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
224 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
226 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
227 #define HDSP_SyncRef_ADAT1 0
228 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
229 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
230 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
231 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
232 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
234 /* Sample Clock Sources */
236 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
237 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
238 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
239 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
240 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
241 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
242 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
243 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
244 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
245 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
247 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
249 #define HDSP_SYNC_FROM_WORD 0
250 #define HDSP_SYNC_FROM_SPDIF 1
251 #define HDSP_SYNC_FROM_ADAT1 2
252 #define HDSP_SYNC_FROM_ADAT_SYNC 3
253 #define HDSP_SYNC_FROM_ADAT2 4
254 #define HDSP_SYNC_FROM_ADAT3 5
256 /* SyncCheck status */
258 #define HDSP_SYNC_CHECK_NO_LOCK 0
259 #define HDSP_SYNC_CHECK_LOCK 1
260 #define HDSP_SYNC_CHECK_SYNC 2
262 /* AutoSync references - used by "autosync_ref" control switch */
264 #define HDSP_AUTOSYNC_FROM_WORD 0
265 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
266 #define HDSP_AUTOSYNC_FROM_SPDIF 2
267 #define HDSP_AUTOSYNC_FROM_NONE 3
268 #define HDSP_AUTOSYNC_FROM_ADAT1 4
269 #define HDSP_AUTOSYNC_FROM_ADAT2 5
270 #define HDSP_AUTOSYNC_FROM_ADAT3 6
272 /* Possible sources of S/PDIF input */
274 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
275 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
276 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
277 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
279 #define HDSP_Frequency32KHz HDSP_Frequency0
280 #define HDSP_Frequency44_1KHz HDSP_Frequency1
281 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
282 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
283 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
284 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
285 /* For H9632 cards */
286 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
287 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
288 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
290 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
291 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
293 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
294 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
296 /* Status Register bits */
298 #define HDSP_audioIRQPending (1<<0)
299 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
300 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
301 #define HDSP_Lock1 (1<<2)
302 #define HDSP_Lock0 (1<<3)
303 #define HDSP_SPDIFSync (1<<4)
304 #define HDSP_TimecodeLock (1<<5)
305 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
306 #define HDSP_Sync2 (1<<16)
307 #define HDSP_Sync1 (1<<17)
308 #define HDSP_Sync0 (1<<18)
309 #define HDSP_DoubleSpeedStatus (1<<19)
310 #define HDSP_ConfigError (1<<20)
311 #define HDSP_DllError (1<<21)
312 #define HDSP_spdifFrequency0 (1<<22)
313 #define HDSP_spdifFrequency1 (1<<23)
314 #define HDSP_spdifFrequency2 (1<<24)
315 #define HDSP_SPDIFErrorFlag (1<<25)
316 #define HDSP_BufferID (1<<26)
317 #define HDSP_TimecodeSync (1<<27)
318 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
319 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
320 #define HDSP_midi0IRQPending (1<<30)
321 #define HDSP_midi1IRQPending (1<<31)
323 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
325 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
326 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
327 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
329 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
330 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
331 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
333 /* This is for H9632 cards */
334 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
335 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
336 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
338 /* Status2 Register bits */
340 #define HDSP_version0 (1<<0)
341 #define HDSP_version1 (1<<1)
342 #define HDSP_version2 (1<<2)
343 #define HDSP_wc_lock (1<<3)
344 #define HDSP_wc_sync (1<<4)
345 #define HDSP_inp_freq0 (1<<5)
346 #define HDSP_inp_freq1 (1<<6)
347 #define HDSP_inp_freq2 (1<<7)
348 #define HDSP_SelSyncRef0 (1<<8)
349 #define HDSP_SelSyncRef1 (1<<9)
350 #define HDSP_SelSyncRef2 (1<<10)
352 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
354 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
355 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
356 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
357 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
358 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
359 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
360 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
361 /* FIXME : more values for 9632 cards ? */
363 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
364 #define HDSP_SelSyncRef_ADAT1 0
365 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
366 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
367 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
368 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
369 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
371 /* Card state flags */
373 #define HDSP_InitializationComplete (1<<0)
374 #define HDSP_FirmwareLoaded (1<<1)
375 #define HDSP_FirmwareCached (1<<2)
377 /* FIFO wait times, defined in terms of 1/10ths of msecs */
379 #define HDSP_LONG_WAIT 5000
380 #define HDSP_SHORT_WAIT 30
382 #define UNITY_GAIN 32768
383 #define MINUS_INFINITY_GAIN 0
385 #ifndef PCI_VENDOR_ID_XILINX
386 #define PCI_VENDOR_ID_XILINX 0x10ee
388 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
389 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
392 /* the size of a substream (1 mono data stream) */
394 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
395 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
397 /* the size of the area we need to allocate for DMA transfers. the
398 size is the same regardless of the number of channels - the
399 Multiface still uses the same memory area.
401 Note that we allocate 1 more channel than is apparently needed
402 because the h/w seems to write 1 byte beyond the end of the last
406 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
407 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
409 typedef struct _hdsp hdsp_t;
410 typedef struct _hdsp_midi hdsp_midi_t;
411 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
413 struct _hdsp_9632_meters {
415 u32 playback_peak[16];
419 u32 input_rms_low[16];
420 u32 playback_rms_low[16];
421 u32 output_rms_low[16];
423 u32 input_rms_high[16];
424 u32 playback_rms_high[16];
425 u32 output_rms_high[16];
426 u32 xxx_rms_high[16];
432 snd_rawmidi_t *rmidi;
433 snd_rawmidi_substream_t *input;
434 snd_rawmidi_substream_t *output;
435 char istimer; /* timer in use */
436 struct timer_list timer;
443 snd_pcm_substream_t *capture_substream;
444 snd_pcm_substream_t *playback_substream;
446 struct tasklet_struct midi_tasklet;
448 u32 control_register; /* cached value */
449 u32 control2_register; /* cached value */
451 u32 creg_spdif_stream;
452 char *card_name; /* digiface/multiface */
453 HDSP_IO_Type io_type; /* ditto, but for code use */
454 unsigned short firmware_rev;
455 unsigned short state; /* stores state bits */
456 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
457 size_t period_bytes; /* guess what this is */
458 unsigned char max_channels;
459 unsigned char qs_in_channels; /* quad speed mode for H9632 */
460 unsigned char ds_in_channels;
461 unsigned char ss_in_channels; /* different for multiface/digiface */
462 unsigned char qs_out_channels;
463 unsigned char ds_out_channels;
464 unsigned char ss_out_channels;
465 void *capture_buffer_unaligned; /* original buffer addresses */
466 void *playback_buffer_unaligned; /* original buffer addresses */
467 unsigned char *capture_buffer; /* suitably aligned address */
468 unsigned char *playback_buffer; /* suitably aligned address */
469 dma_addr_t capture_buffer_addr;
470 dma_addr_t playback_buffer_addr;
474 int passthru; /* non-zero if doing pass-thru */
475 int system_sample_rate;
480 struct resource *res_port;
481 unsigned long iobase;
486 snd_kcontrol_t *spdif_ctl;
487 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
490 /* These tables map the ALSA channels 1..N to the channels that we
491 need to use in order to find the relevant channel buffer. RME
492 refer to this kind of mapping as between "the ADAT channel and
493 the DMA channel." We index it using the logical audio channel,
494 and the value is the DMA channel (i.e. channel buffer number)
495 where the data for that channel can be read/written from/to.
498 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
499 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
500 18, 19, 20, 21, 22, 23, 24, 25
503 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
505 0, 1, 2, 3, 4, 5, 6, 7,
507 16, 17, 18, 19, 20, 21, 22, 23,
510 -1, -1, -1, -1, -1, -1, -1, -1
513 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
514 /* ADAT channels are remapped */
515 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
516 /* channels 12 and 13 are S/PDIF */
518 /* others don't exist */
519 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
522 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
524 0, 1, 2, 3, 4, 5, 6, 7,
529 /* AO4S-192 and AI4S-192 extension boards */
531 /* others don't exist */
532 -1, -1, -1, -1, -1, -1, -1, -1,
536 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
543 /* AO4S-192 and AI4S-192 extension boards */
545 /* others don't exist */
546 -1, -1, -1, -1, -1, -1, -1, -1,
547 -1, -1, -1, -1, -1, -1
550 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
551 /* ADAT is disabled in this mode */
556 /* AO4S-192 and AI4S-192 extension boards */
558 /* others don't exist */
559 -1, -1, -1, -1, -1, -1, -1, -1,
560 -1, -1, -1, -1, -1, -1, -1, -1,
564 #define HDSP_PREALLOCATE_MEMORY /* via module snd-hdsp_mem */
566 #ifdef HDSP_PREALLOCATE_MEMORY
567 static void *snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size, dma_addr_t *addrp, int capture)
569 struct snd_dma_device pdev;
570 struct snd_dma_buffer dmbuf;
572 memset(&pdev, 0, sizeof(pdev));
573 pdev.type = SNDRV_DMA_TYPE_DEV;
574 pdev.dev = snd_dma_pci_data(pci);
577 if (! snd_dma_get_reserved(&pdev, &dmbuf)) {
578 if (snd_dma_alloc_pages(&pdev, size, &dmbuf) < 0)
580 snd_dma_set_reserved(&pdev, &dmbuf);
586 static void snd_hammerfall_free_buffer(struct pci_dev *pci, size_t size, void *ptr, dma_addr_t addr, int capture)
588 struct snd_dma_device pdev;
590 memset(&pdev, 0, sizeof(pdev));
591 pdev.type = SNDRV_DMA_TYPE_DEV;
592 pdev.dev = snd_dma_pci_data(pci);
594 snd_dma_free_reserved(&pdev);
598 static void *snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size, dma_addr_t *addrp, int capture)
600 return snd_malloc_pci_pages(pci, size, addrp);
603 static void snd_hammerfall_free_buffer(struct pci_dev *pci, size_t size, void *ptr, dma_addr_t addr, int capture)
605 snd_free_pci_pages(pci, size, ptr, addr);
609 static struct pci_device_id snd_hdsp_ids[] = {
611 .vendor = PCI_VENDOR_ID_XILINX,
612 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
613 .subvendor = PCI_ANY_ID,
614 .subdevice = PCI_ANY_ID,
615 }, /* RME Hammerfall-DSP */
619 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
622 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
623 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
624 static inline int snd_hdsp_enable_io (hdsp_t *hdsp);
625 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
626 static inline void snd_hdsp_initialize_channels (hdsp_t *hdsp);
627 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
628 static int hdsp_autosync_ref(hdsp_t *hdsp);
629 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
630 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
632 static inline int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
634 switch (hdsp->firmware_rev) {
636 return (64 * out) + (32 + (in));
639 return (32 * out) + (16 + (in));
641 return (52 * out) + (26 + (in));
645 static inline int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
647 switch (hdsp->firmware_rev) {
649 return (64 * out) + in;
652 return (32 * out) + in;
654 return (52 * out) + in;
658 static inline void hdsp_write(hdsp_t *hdsp, int reg, int val)
660 writel(val, hdsp->iobase + reg);
663 static inline unsigned int hdsp_read(hdsp_t *hdsp, int reg)
665 return readl (hdsp->iobase + reg);
668 static inline int hdsp_check_for_iobox (hdsp_t *hdsp)
671 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
672 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
673 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
674 hdsp->state &= ~HDSP_FirmwareLoaded;
681 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
686 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
688 snd_printk ("loading firmware\n");
690 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
691 hdsp_write (hdsp, HDSP_fifoData, 0);
693 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
694 snd_printk ("timeout waiting for download preparation\n");
698 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
700 for (i = 0; i < 24413; ++i) {
701 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
702 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
703 snd_printk ("timeout during firmware loading\n");
708 if ((1000 / HZ) < 3000) {
709 set_current_state(TASK_UNINTERRUPTIBLE);
710 schedule_timeout((3000 * HZ + 999) / 1000);
715 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
716 snd_printk ("timeout at end of firmware loading\n");
720 #ifdef SNDRV_BIG_ENDIAN
721 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
723 hdsp->control2_register = 0;
725 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
726 snd_printk ("finished firmware loading\n");
729 if (hdsp->state & HDSP_InitializationComplete) {
730 snd_printk("firmware loaded from cache, restoring defaults\n");
731 spin_lock_irqsave(&hdsp->lock, flags);
732 snd_hdsp_set_defaults(hdsp);
733 spin_unlock_irqrestore(&hdsp->lock, flags);
736 hdsp->state |= HDSP_FirmwareLoaded;
741 static inline int hdsp_get_iobox_version (hdsp_t *hdsp)
745 if (hdsp_check_for_iobox (hdsp)) {
749 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
753 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
755 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
756 hdsp_write (hdsp, HDSP_fifoData, 0);
757 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
761 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
762 hdsp_write (hdsp, HDSP_fifoData, 0);
764 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
765 hdsp->io_type = Multiface;
766 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
767 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
768 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
770 hdsp->io_type = Digiface;
773 /* firmware was already loaded, get iobox type */
774 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
775 hdsp->io_type = Multiface;
777 hdsp->io_type = Digiface;
784 static inline int hdsp_check_for_firmware (hdsp_t *hdsp)
786 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
787 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
788 snd_printk("firmware not present.\n");
789 hdsp->state &= ~HDSP_FirmwareLoaded;
796 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
800 /* the fifoStatus registers reports on how many words
801 are available in the command FIFO.
804 for (i = 0; i < timeout; i++) {
806 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
809 /* not very friendly, but we only do this during a firmware
810 load and changing the mixer, so we just put up with it.
816 snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
821 static inline int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
823 if (addr >= HDSP_MATRIX_MIXER_SIZE) {
826 return hdsp->mixer_matrix[addr];
829 static inline int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
833 if (addr >= HDSP_MATRIX_MIXER_SIZE)
836 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
838 /* from martin björnsen:
840 "You can only write dwords to the
841 mixer memory which contain two
842 mixer values in the low and high
843 word. So if you want to change
844 value 0 you have to read value 1
845 from the cache and write both to
846 the first dword in the mixer
850 if (hdsp->io_type == H9632 && addr >= 512) {
854 if (hdsp->io_type == H9652 && addr >= 1352) {
858 hdsp->mixer_matrix[addr] = data;
861 /* `addr' addresses a 16-bit wide address, but
862 the address space accessed via hdsp_write
863 uses byte offsets. put another way, addr
864 varies from 0 to 1351, but to access the
865 corresponding memory location, we need
866 to access 0 to 2703 ...
870 hdsp_write (hdsp, 4096 + (ad*4),
871 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
872 hdsp->mixer_matrix[addr&0x7fe]);
878 ad = (addr << 16) + data;
880 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
884 hdsp_write (hdsp, HDSP_fifoData, ad);
885 hdsp->mixer_matrix[addr] = data;
892 static inline int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
897 spin_lock_irqsave(&hdsp->lock, flags);
898 if ((hdsp->playback_pid != hdsp->capture_pid) &&
899 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
902 spin_unlock_irqrestore(&hdsp->lock, flags);
906 static inline int hdsp_external_sample_rate (hdsp_t *hdsp)
908 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
909 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
912 case HDSP_systemFrequency32: return 32000;
913 case HDSP_systemFrequency44_1: return 44100;
914 case HDSP_systemFrequency48: return 48000;
915 case HDSP_systemFrequency64: return 64000;
916 case HDSP_systemFrequency88_2: return 88200;
917 case HDSP_systemFrequency96: return 96000;
923 static inline int hdsp_spdif_sample_rate(hdsp_t *hdsp)
925 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
926 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
928 if (status & HDSP_SPDIFErrorFlag) {
933 case HDSP_spdifFrequency32KHz: return 32000;
934 case HDSP_spdifFrequency44_1KHz: return 44100;
935 case HDSP_spdifFrequency48KHz: return 48000;
936 case HDSP_spdifFrequency64KHz: return 64000;
937 case HDSP_spdifFrequency88_2KHz: return 88200;
938 case HDSP_spdifFrequency96KHz: return 96000;
939 case HDSP_spdifFrequency128KHz:
940 if (hdsp->io_type == H9632) return 128000;
942 case HDSP_spdifFrequency176_4KHz:
943 if (hdsp->io_type == H9632) return 176400;
945 case HDSP_spdifFrequency192KHz:
946 if (hdsp->io_type == H9632) return 192000;
951 snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
955 static inline void hdsp_compute_period_size(hdsp_t *hdsp)
957 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
960 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
964 position = hdsp_read(hdsp, HDSP_statusRegister);
966 if (!hdsp->precise_ptr) {
967 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
970 position &= HDSP_BufferPositionMask;
973 position &= (HDSP_CHANNEL_BUFFER_SAMPLES-1);
977 static inline void hdsp_reset_hw_pointer(hdsp_t *hdsp)
979 hdsp_write (hdsp, HDSP_resetPointer, 0);
982 static inline void hdsp_start_audio(hdsp_t *s)
984 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
985 hdsp_write(s, HDSP_controlRegister, s->control_register);
988 static inline void hdsp_stop_audio(hdsp_t *s)
990 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
991 hdsp_write(s, HDSP_controlRegister, s->control_register);
994 static inline void hdsp_silence_playback(hdsp_t *hdsp)
996 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
999 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
1003 spin_lock_irq(&s->lock);
1012 s->control_register &= ~HDSP_LatencyMask;
1013 s->control_register |= hdsp_encode_latency(n);
1015 hdsp_write(s, HDSP_controlRegister, s->control_register);
1017 hdsp_compute_period_size(s);
1019 spin_unlock_irq(&s->lock);
1024 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
1026 int reject_if_open = 0;
1030 /* ASSUMPTION: hdsp->lock is either held, or
1031 there is no need for it (e.g. during module
1035 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1036 if (called_internally) {
1037 /* request from ctl or card initialization */
1038 snd_printk("device is not running as a clock master: cannot set sample rate.\n");
1041 /* hw_param request while in AutoSync mode */
1042 int external_freq = hdsp_external_sample_rate(hdsp);
1043 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1045 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1046 snd_printk("Detected ADAT in double speed mode\n");
1047 } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1048 snd_printk("Detected ADAT in quad speed mode\n");
1049 } else if (rate != external_freq) {
1050 snd_printk("No AutoSync source for requested rate\n");
1056 current_rate = hdsp->system_sample_rate;
1058 /* Changing from a "single speed" to a "double speed" rate is
1059 not allowed if any substreams are open. This is because
1060 such a change causes a shift in the location of
1061 the DMA buffers and a reduction in the number of available
1064 Note that a similar but essentially insoluble problem
1065 exists for externally-driven rate changes. All we can do
1066 is to flag rate changes in the read/write routines. */
1068 if (rate > 96000 && hdsp->io_type != H9632) {
1074 if (current_rate > 48000) {
1077 rate_bits = HDSP_Frequency32KHz;
1080 if (current_rate > 48000) {
1083 rate_bits = HDSP_Frequency44_1KHz;
1086 if (current_rate > 48000) {
1089 rate_bits = HDSP_Frequency48KHz;
1092 if (current_rate <= 48000 || current_rate > 96000) {
1095 rate_bits = HDSP_Frequency64KHz;
1098 if (current_rate <= 48000 || current_rate > 96000) {
1101 rate_bits = HDSP_Frequency88_2KHz;
1104 if (current_rate <= 48000 || current_rate > 96000) {
1107 rate_bits = HDSP_Frequency96KHz;
1110 if (current_rate < 128000) {
1113 rate_bits = HDSP_Frequency128KHz;
1116 if (current_rate < 128000) {
1119 rate_bits = HDSP_Frequency176_4KHz;
1122 if (current_rate < 128000) {
1125 rate_bits = HDSP_Frequency192KHz;
1131 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1132 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1134 hdsp->playback_pid);
1138 hdsp->control_register &= ~HDSP_FrequencyMask;
1139 hdsp->control_register |= rate_bits;
1140 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1142 if (rate >= 128000) {
1143 hdsp->channel_map = channel_map_H9632_qs;
1144 } else if (rate > 48000) {
1145 if (hdsp->io_type == H9632) {
1146 hdsp->channel_map = channel_map_H9632_ds;
1148 hdsp->channel_map = channel_map_ds;
1151 switch (hdsp->io_type) {
1153 hdsp->channel_map = channel_map_mf_ss;
1157 hdsp->channel_map = channel_map_df_ss;
1160 hdsp->channel_map = channel_map_H9632_ss;
1163 /* should never happen */
1168 hdsp->system_sample_rate = rate;
1173 static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
1182 /* set thru for all channels */
1185 for (i = 0; i < hdsp->max_channels; i++) {
1186 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN);
1189 for (i = 0; i < hdsp->max_channels; i++) {
1190 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN);
1197 snd_assert(channel < hdsp->max_channels, return);
1199 mapped_channel = hdsp->channel_map[channel];
1201 snd_assert(mapped_channel > -1, return);
1204 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN);
1206 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN);
1211 static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
1214 hdsp_set_thru(hdsp, -1, 1);
1215 hdsp_reset_hw_pointer(hdsp);
1216 hdsp_silence_playback(hdsp);
1218 /* we don't want interrupts, so do a
1219 custom version of hdsp_start_audio().
1222 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
1224 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1227 hdsp_set_thru(hdsp, -1, 0);
1228 hdsp_stop_audio(hdsp);
1235 /*----------------------------------------------------------------------------
1237 ----------------------------------------------------------------------------*/
1239 static inline unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1241 /* the hardware already does the relevant bit-mask with 0xff */
1243 return hdsp_read(hdsp, HDSP_midiDataIn1);
1245 return hdsp_read(hdsp, HDSP_midiDataIn0);
1249 static inline void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1251 /* the hardware already does the relevant bit-mask with 0xff */
1253 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1255 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1259 static inline int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1262 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1264 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1268 static inline int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1270 int fifo_bytes_used;
1273 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1275 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1278 if (fifo_bytes_used < 128) {
1279 return 128 - fifo_bytes_used;
1285 static inline void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1287 while (snd_hdsp_midi_input_available (hdsp, id)) {
1288 snd_hdsp_midi_read_byte (hdsp, id);
1292 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1294 unsigned long flags;
1298 unsigned char buf[128];
1300 /* Output is not interrupt driven */
1302 spin_lock_irqsave (&hmidi->lock, flags);
1303 if (hmidi->output) {
1304 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1305 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1306 if (n_pending > (int)sizeof (buf))
1307 n_pending = sizeof (buf);
1309 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1310 for (i = 0; i < to_write; ++i)
1311 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1316 spin_unlock_irqrestore (&hmidi->lock, flags);
1320 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1322 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1323 unsigned long flags;
1327 spin_lock_irqsave (&hmidi->lock, flags);
1328 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1330 if (n_pending > (int)sizeof (buf)) {
1331 n_pending = sizeof (buf);
1333 for (i = 0; i < n_pending; ++i) {
1334 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1337 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1340 /* flush the MIDI input FIFO */
1341 while (--n_pending) {
1342 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1348 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1350 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1352 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1353 spin_unlock_irqrestore (&hmidi->lock, flags);
1354 return snd_hdsp_midi_output_write (hmidi);
1357 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1361 unsigned long flags;
1364 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1366 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1367 spin_lock_irqsave (&hdsp->lock, flags);
1369 if (!(hdsp->control_register & ie)) {
1370 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1371 hdsp->control_register |= ie;
1374 hdsp->control_register &= ~ie;
1377 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1378 spin_unlock_irqrestore (&hdsp->lock, flags);
1381 static void snd_hdsp_midi_output_timer(unsigned long data)
1383 hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1384 unsigned long flags;
1386 snd_hdsp_midi_output_write(hmidi);
1387 spin_lock_irqsave (&hmidi->lock, flags);
1389 /* this does not bump hmidi->istimer, because the
1390 kernel automatically removed the timer when it
1391 expired, and we are now adding it back, thus
1392 leaving istimer wherever it was set before.
1395 if (hmidi->istimer) {
1396 hmidi->timer.expires = 1 + jiffies;
1397 add_timer(&hmidi->timer);
1400 spin_unlock_irqrestore (&hmidi->lock, flags);
1403 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1406 unsigned long flags;
1408 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1409 spin_lock_irqsave (&hmidi->lock, flags);
1411 if (!hmidi->istimer) {
1412 init_timer(&hmidi->timer);
1413 hmidi->timer.function = snd_hdsp_midi_output_timer;
1414 hmidi->timer.data = (unsigned long) hmidi;
1415 hmidi->timer.expires = 1 + jiffies;
1416 add_timer(&hmidi->timer);
1420 if (hmidi->istimer && --hmidi->istimer <= 0) {
1421 del_timer (&hmidi->timer);
1424 spin_unlock_irqrestore (&hmidi->lock, flags);
1426 snd_hdsp_midi_output_write(hmidi);
1429 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1432 unsigned long flags;
1434 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1435 spin_lock_irqsave (&hmidi->lock, flags);
1436 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1437 hmidi->input = substream;
1438 spin_unlock_irqrestore (&hmidi->lock, flags);
1443 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1446 unsigned long flags;
1448 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1449 spin_lock_irqsave (&hmidi->lock, flags);
1450 hmidi->output = substream;
1451 spin_unlock_irqrestore (&hmidi->lock, flags);
1456 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1459 unsigned long flags;
1461 snd_hdsp_midi_input_trigger (substream, 0);
1463 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1464 spin_lock_irqsave (&hmidi->lock, flags);
1465 hmidi->input = NULL;
1466 spin_unlock_irqrestore (&hmidi->lock, flags);
1471 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1474 unsigned long flags;
1476 snd_hdsp_midi_output_trigger (substream, 0);
1478 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1479 spin_lock_irqsave (&hmidi->lock, flags);
1480 hmidi->output = NULL;
1481 spin_unlock_irqrestore (&hmidi->lock, flags);
1486 snd_rawmidi_ops_t snd_hdsp_midi_output =
1488 .open = snd_hdsp_midi_output_open,
1489 .close = snd_hdsp_midi_output_close,
1490 .trigger = snd_hdsp_midi_output_trigger,
1493 snd_rawmidi_ops_t snd_hdsp_midi_input =
1495 .open = snd_hdsp_midi_input_open,
1496 .close = snd_hdsp_midi_input_close,
1497 .trigger = snd_hdsp_midi_input_trigger,
1500 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1504 hdsp->midi[id].id = id;
1505 hdsp->midi[id].rmidi = NULL;
1506 hdsp->midi[id].input = NULL;
1507 hdsp->midi[id].output = NULL;
1508 hdsp->midi[id].hdsp = hdsp;
1509 hdsp->midi[id].istimer = 0;
1510 hdsp->midi[id].pending = 0;
1511 spin_lock_init (&hdsp->midi[id].lock);
1513 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1514 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1518 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1519 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1521 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1522 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1524 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1525 SNDRV_RAWMIDI_INFO_INPUT |
1526 SNDRV_RAWMIDI_INFO_DUPLEX;
1531 /*-----------------------------------------------------------------------------
1533 ----------------------------------------------------------------------------*/
1535 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1538 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1539 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1540 if (val & HDSP_SPDIFProfessional)
1541 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1543 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1547 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1549 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1550 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1551 if (val & HDSP_SPDIFProfessional)
1552 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1554 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1557 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1559 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1564 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1566 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1568 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1572 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1574 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1575 unsigned long flags;
1579 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1580 spin_lock_irqsave(&hdsp->lock, flags);
1581 change = val != hdsp->creg_spdif;
1582 hdsp->creg_spdif = val;
1583 spin_unlock_irqrestore(&hdsp->lock, flags);
1587 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1589 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1594 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1596 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1598 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1602 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1604 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1605 unsigned long flags;
1609 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1610 spin_lock_irqsave(&hdsp->lock, flags);
1611 change = val != hdsp->creg_spdif_stream;
1612 hdsp->creg_spdif_stream = val;
1613 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1614 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1615 spin_unlock_irqrestore(&hdsp->lock, flags);
1619 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1621 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1626 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1628 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1632 #define HDSP_SPDIF_IN(xname, xindex) \
1633 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1636 .info = snd_hdsp_info_spdif_in, \
1637 .get = snd_hdsp_get_spdif_in, \
1638 .put = snd_hdsp_put_spdif_in }
1640 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1642 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1645 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1647 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1648 hdsp->control_register |= hdsp_encode_spdif_in(in);
1649 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1653 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1655 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1656 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1658 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1660 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1661 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1662 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1663 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1667 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1669 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1671 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1675 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1677 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1678 unsigned long flags;
1682 if (!snd_hdsp_use_is_exclusive(hdsp))
1684 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1685 spin_lock_irqsave(&hdsp->lock, flags);
1686 change = val != hdsp_spdif_in(hdsp);
1688 hdsp_set_spdif_input(hdsp, val);
1689 spin_unlock_irqrestore(&hdsp->lock, flags);
1693 #define HDSP_SPDIF_OUT(xname, xindex) \
1694 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1695 .info = snd_hdsp_info_spdif_bits, \
1696 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1698 static int hdsp_spdif_out(hdsp_t *hdsp)
1700 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1703 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1706 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1708 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1710 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1714 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1716 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1718 uinfo->value.integer.min = 0;
1719 uinfo->value.integer.max = 1;
1723 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1725 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1727 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1731 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1733 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1734 unsigned long flags;
1738 if (!snd_hdsp_use_is_exclusive(hdsp))
1740 val = ucontrol->value.integer.value[0] & 1;
1741 spin_lock_irqsave(&hdsp->lock, flags);
1742 change = (int)val != hdsp_spdif_out(hdsp);
1743 hdsp_set_spdif_output(hdsp, val);
1744 spin_unlock_irqrestore(&hdsp->lock, flags);
1748 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1749 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1750 .info = snd_hdsp_info_spdif_bits, \
1751 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1753 static int hdsp_spdif_professional(hdsp_t *hdsp)
1755 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1758 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1761 hdsp->control_register |= HDSP_SPDIFProfessional;
1763 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1765 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1769 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1771 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1773 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1777 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1779 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1780 unsigned long flags;
1784 if (!snd_hdsp_use_is_exclusive(hdsp))
1786 val = ucontrol->value.integer.value[0] & 1;
1787 spin_lock_irqsave(&hdsp->lock, flags);
1788 change = (int)val != hdsp_spdif_professional(hdsp);
1789 hdsp_set_spdif_professional(hdsp, val);
1790 spin_unlock_irqrestore(&hdsp->lock, flags);
1794 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1795 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1796 .info = snd_hdsp_info_spdif_bits, \
1797 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1799 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1801 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1804 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1807 hdsp->control_register |= HDSP_SPDIFEmphasis;
1809 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1811 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1815 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1817 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1819 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1823 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1825 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1826 unsigned long flags;
1830 if (!snd_hdsp_use_is_exclusive(hdsp))
1832 val = ucontrol->value.integer.value[0] & 1;
1833 spin_lock_irqsave(&hdsp->lock, flags);
1834 change = (int)val != hdsp_spdif_emphasis(hdsp);
1835 hdsp_set_spdif_emphasis(hdsp, val);
1836 spin_unlock_irqrestore(&hdsp->lock, flags);
1840 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1841 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1842 .info = snd_hdsp_info_spdif_bits, \
1843 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1845 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1847 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1850 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1853 hdsp->control_register |= HDSP_SPDIFNonAudio;
1855 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1857 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1861 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1863 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1865 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1869 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1871 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1872 unsigned long flags;
1876 if (!snd_hdsp_use_is_exclusive(hdsp))
1878 val = ucontrol->value.integer.value[0] & 1;
1879 spin_lock_irqsave(&hdsp->lock, flags);
1880 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1881 hdsp_set_spdif_nonaudio(hdsp, val);
1882 spin_unlock_irqrestore(&hdsp->lock, flags);
1886 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1887 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1890 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1891 .info = snd_hdsp_info_spdif_sample_rate, \
1892 .get = snd_hdsp_get_spdif_sample_rate \
1895 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1897 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1898 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1900 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1902 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1903 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1904 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1905 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1909 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1911 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1913 switch (hdsp_spdif_sample_rate(hdsp)) {
1915 ucontrol->value.enumerated.item[0] = 0;
1918 ucontrol->value.enumerated.item[0] = 1;
1921 ucontrol->value.enumerated.item[0] = 2;
1924 ucontrol->value.enumerated.item[0] = 3;
1927 ucontrol->value.enumerated.item[0] = 4;
1930 ucontrol->value.enumerated.item[0] = 5;
1933 ucontrol->value.enumerated.item[0] = 7;
1936 ucontrol->value.enumerated.item[0] = 8;
1939 ucontrol->value.enumerated.item[0] = 9;
1942 ucontrol->value.enumerated.item[0] = 6;
1947 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1948 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1951 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1952 .info = snd_hdsp_info_system_sample_rate, \
1953 .get = snd_hdsp_get_system_sample_rate \
1956 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1958 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1963 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1965 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1967 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1971 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1972 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1975 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1976 .info = snd_hdsp_info_autosync_sample_rate, \
1977 .get = snd_hdsp_get_autosync_sample_rate \
1980 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1982 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1983 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1984 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1986 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1987 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1988 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1989 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1993 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1995 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1997 switch (hdsp_external_sample_rate(hdsp)) {
1999 ucontrol->value.enumerated.item[0] = 0;
2002 ucontrol->value.enumerated.item[0] = 1;
2005 ucontrol->value.enumerated.item[0] = 2;
2008 ucontrol->value.enumerated.item[0] = 3;
2011 ucontrol->value.enumerated.item[0] = 4;
2014 ucontrol->value.enumerated.item[0] = 5;
2017 ucontrol->value.enumerated.item[0] = 7;
2020 ucontrol->value.enumerated.item[0] = 8;
2023 ucontrol->value.enumerated.item[0] = 9;
2026 ucontrol->value.enumerated.item[0] = 6;
2031 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
2032 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2035 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2036 .info = snd_hdsp_info_system_clock_mode, \
2037 .get = snd_hdsp_get_system_clock_mode \
2040 static int hdsp_system_clock_mode(hdsp_t *hdsp)
2042 if (hdsp->control_register & HDSP_ClockModeMaster) {
2044 } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
2050 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2052 static char *texts[] = {"Master", "Slave" };
2054 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2056 uinfo->value.enumerated.items = 2;
2057 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2058 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2059 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2063 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2065 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2067 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2071 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2072 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
2075 .info = snd_hdsp_info_clock_source, \
2076 .get = snd_hdsp_get_clock_source, \
2077 .put = snd_hdsp_put_clock_source \
2080 static int hdsp_clock_source(hdsp_t *hdsp)
2082 if (hdsp->control_register & HDSP_ClockModeMaster) {
2083 switch (hdsp->system_sample_rate) {
2110 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2114 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2115 if (hdsp_external_sample_rate(hdsp) != 0) {
2116 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2117 hdsp->control_register &= ~HDSP_ClockModeMaster;
2118 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2123 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2126 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2129 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2132 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2135 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2138 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2141 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2144 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2147 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2153 hdsp->control_register |= HDSP_ClockModeMaster;
2154 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2155 hdsp_set_rate(hdsp, rate, 1);
2159 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2161 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2162 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2164 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2166 if (hdsp->io_type == H9632)
2167 uinfo->value.enumerated.items = 10;
2169 uinfo->value.enumerated.items = 7;
2170 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2171 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2172 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2176 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2178 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2180 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2184 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2186 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2187 unsigned long flags;
2191 if (!snd_hdsp_use_is_exclusive(hdsp))
2193 val = ucontrol->value.enumerated.item[0];
2194 if (val < 0) val = 0;
2195 if (hdsp->io_type == H9632) {
2196 if (val > 9) val = 9;
2198 if (val > 6) val = 6;
2200 spin_lock_irqsave(&hdsp->lock, flags);
2201 if (val != hdsp_clock_source(hdsp)) {
2202 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2206 spin_unlock_irqrestore(&hdsp->lock, flags);
2210 #define HDSP_DA_GAIN(xname, xindex) \
2211 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2214 .info = snd_hdsp_info_da_gain, \
2215 .get = snd_hdsp_get_da_gain, \
2216 .put = snd_hdsp_put_da_gain \
2219 static int hdsp_da_gain(hdsp_t *hdsp)
2221 switch (hdsp->control_register & HDSP_DAGainMask) {
2222 case HDSP_DAGainHighGain:
2224 case HDSP_DAGainPlus4dBu:
2226 case HDSP_DAGainMinus10dBV:
2233 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2235 hdsp->control_register &= ~HDSP_DAGainMask;
2238 hdsp->control_register |= HDSP_DAGainHighGain;
2241 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2244 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2250 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2254 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2256 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2258 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2260 uinfo->value.enumerated.items = 3;
2261 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2262 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2263 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2267 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2269 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2271 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2275 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2277 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2278 unsigned long flags;
2282 if (!snd_hdsp_use_is_exclusive(hdsp))
2284 val = ucontrol->value.enumerated.item[0];
2285 if (val < 0) val = 0;
2286 if (val > 2) val = 2;
2287 spin_lock_irqsave(&hdsp->lock, flags);
2288 if (val != hdsp_da_gain(hdsp)) {
2289 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2293 spin_unlock_irqrestore(&hdsp->lock, flags);
2297 #define HDSP_AD_GAIN(xname, xindex) \
2298 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2301 .info = snd_hdsp_info_ad_gain, \
2302 .get = snd_hdsp_get_ad_gain, \
2303 .put = snd_hdsp_put_ad_gain \
2306 static int hdsp_ad_gain(hdsp_t *hdsp)
2308 switch (hdsp->control_register & HDSP_ADGainMask) {
2309 case HDSP_ADGainMinus10dBV:
2311 case HDSP_ADGainPlus4dBu:
2313 case HDSP_ADGainLowGain:
2320 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2322 hdsp->control_register &= ~HDSP_ADGainMask;
2325 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2328 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2331 hdsp->control_register |= HDSP_ADGainLowGain;
2337 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2341 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2343 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2345 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2347 uinfo->value.enumerated.items = 3;
2348 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2349 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2350 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2354 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2356 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2358 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2362 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2364 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2365 unsigned long flags;
2369 if (!snd_hdsp_use_is_exclusive(hdsp))
2371 val = ucontrol->value.enumerated.item[0];
2372 if (val < 0) val = 0;
2373 if (val > 2) val = 2;
2374 spin_lock_irqsave(&hdsp->lock, flags);
2375 if (val != hdsp_ad_gain(hdsp)) {
2376 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2380 spin_unlock_irqrestore(&hdsp->lock, flags);
2384 #define HDSP_PHONE_GAIN(xname, xindex) \
2385 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2388 .info = snd_hdsp_info_phone_gain, \
2389 .get = snd_hdsp_get_phone_gain, \
2390 .put = snd_hdsp_put_phone_gain \
2393 static int hdsp_phone_gain(hdsp_t *hdsp)
2395 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2396 case HDSP_PhoneGain0dB:
2398 case HDSP_PhoneGainMinus6dB:
2400 case HDSP_PhoneGainMinus12dB:
2407 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2409 hdsp->control_register &= ~HDSP_PhoneGainMask;
2412 hdsp->control_register |= HDSP_PhoneGain0dB;
2415 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2418 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2424 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2428 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2430 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2432 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2434 uinfo->value.enumerated.items = 3;
2435 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2436 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2437 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2441 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2443 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2445 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2449 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2451 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2452 unsigned long flags;
2456 if (!snd_hdsp_use_is_exclusive(hdsp))
2458 val = ucontrol->value.enumerated.item[0];
2459 if (val < 0) val = 0;
2460 if (val > 2) val = 2;
2461 spin_lock_irqsave(&hdsp->lock, flags);
2462 if (val != hdsp_phone_gain(hdsp)) {
2463 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2467 spin_unlock_irqrestore(&hdsp->lock, flags);
2471 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2472 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2475 .info = snd_hdsp_info_xlr_breakout_cable, \
2476 .get = snd_hdsp_get_xlr_breakout_cable, \
2477 .put = snd_hdsp_put_xlr_breakout_cable \
2480 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2482 if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2488 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2491 hdsp->control_register |= HDSP_XLRBreakoutCable;
2493 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2495 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2499 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2501 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2503 uinfo->value.integer.min = 0;
2504 uinfo->value.integer.max = 1;
2508 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2510 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2512 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2516 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2518 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2519 unsigned long flags;
2523 if (!snd_hdsp_use_is_exclusive(hdsp))
2525 val = ucontrol->value.integer.value[0] & 1;
2526 spin_lock_irqsave(&hdsp->lock, flags);
2527 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2528 hdsp_set_xlr_breakout_cable(hdsp, val);
2529 spin_unlock_irqrestore(&hdsp->lock, flags);
2533 /* (De)activates old RME Analog Extension Board
2534 These are connected to the internal ADAT connector
2535 Switching this on desactivates external ADAT
2537 #define HDSP_AEB(xname, xindex) \
2538 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2541 .info = snd_hdsp_info_aeb, \
2542 .get = snd_hdsp_get_aeb, \
2543 .put = snd_hdsp_put_aeb \
2546 static int hdsp_aeb(hdsp_t *hdsp)
2548 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2554 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2557 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2559 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2561 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2565 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2567 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2569 uinfo->value.integer.min = 0;
2570 uinfo->value.integer.max = 1;
2574 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2576 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2578 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2582 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2584 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2585 unsigned long flags;
2589 if (!snd_hdsp_use_is_exclusive(hdsp))
2591 val = ucontrol->value.integer.value[0] & 1;
2592 spin_lock_irqsave(&hdsp->lock, flags);
2593 change = (int)val != hdsp_aeb(hdsp);
2594 hdsp_set_aeb(hdsp, val);
2595 spin_unlock_irqrestore(&hdsp->lock, flags);
2599 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2600 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2603 .info = snd_hdsp_info_pref_sync_ref, \
2604 .get = snd_hdsp_get_pref_sync_ref, \
2605 .put = snd_hdsp_put_pref_sync_ref \
2608 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2610 /* Notice that this looks at the requested sync source,
2611 not the one actually in use.
2614 switch (hdsp->control_register & HDSP_SyncRefMask) {
2615 case HDSP_SyncRef_ADAT1:
2616 return HDSP_SYNC_FROM_ADAT1;
2617 case HDSP_SyncRef_ADAT2:
2618 return HDSP_SYNC_FROM_ADAT2;
2619 case HDSP_SyncRef_ADAT3:
2620 return HDSP_SYNC_FROM_ADAT3;
2621 case HDSP_SyncRef_SPDIF:
2622 return HDSP_SYNC_FROM_SPDIF;
2623 case HDSP_SyncRef_WORD:
2624 return HDSP_SYNC_FROM_WORD;
2625 case HDSP_SyncRef_ADAT_SYNC:
2626 return HDSP_SYNC_FROM_ADAT_SYNC;
2628 return HDSP_SYNC_FROM_WORD;
2633 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2635 hdsp->control_register &= ~HDSP_SyncRefMask;
2637 case HDSP_SYNC_FROM_ADAT1:
2638 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2640 case HDSP_SYNC_FROM_ADAT2:
2641 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2643 case HDSP_SYNC_FROM_ADAT3:
2644 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2646 case HDSP_SYNC_FROM_SPDIF:
2647 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2649 case HDSP_SYNC_FROM_WORD:
2650 hdsp->control_register |= HDSP_SyncRef_WORD;
2652 case HDSP_SYNC_FROM_ADAT_SYNC:
2653 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2658 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2662 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2664 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2665 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2667 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2670 switch (hdsp->io_type) {
2673 uinfo->value.enumerated.items = 6;
2676 uinfo->value.enumerated.items = 4;
2679 uinfo->value.enumerated.items = 3;
2682 uinfo->value.enumerated.items = 0;
2686 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2687 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2688 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2692 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2694 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2696 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2700 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2702 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2703 unsigned long flags;
2707 if (!snd_hdsp_use_is_exclusive(hdsp))
2710 switch (hdsp->io_type) {
2725 val = ucontrol->value.enumerated.item[0] % max;
2726 spin_lock_irqsave(&hdsp->lock, flags);
2727 change = (int)val != hdsp_pref_sync_ref(hdsp);
2728 hdsp_set_pref_sync_ref(hdsp, val);
2729 spin_unlock_irqrestore(&hdsp->lock, flags);
2733 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2734 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2737 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2738 .info = snd_hdsp_info_autosync_ref, \
2739 .get = snd_hdsp_get_autosync_ref, \
2742 static int hdsp_autosync_ref(hdsp_t *hdsp)
2744 /* This looks at the autosync selected sync reference */
2745 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2747 switch (status2 & HDSP_SelSyncRefMask) {
2748 case HDSP_SelSyncRef_WORD:
2749 return HDSP_AUTOSYNC_FROM_WORD;
2750 case HDSP_SelSyncRef_ADAT_SYNC:
2751 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2752 case HDSP_SelSyncRef_SPDIF:
2753 return HDSP_AUTOSYNC_FROM_SPDIF;
2754 case HDSP_SelSyncRefMask:
2755 return HDSP_AUTOSYNC_FROM_NONE;
2756 case HDSP_SelSyncRef_ADAT1:
2757 return HDSP_AUTOSYNC_FROM_ADAT1;
2758 case HDSP_SelSyncRef_ADAT2:
2759 return HDSP_AUTOSYNC_FROM_ADAT2;
2760 case HDSP_SelSyncRef_ADAT3:
2761 return HDSP_AUTOSYNC_FROM_ADAT3;
2763 return HDSP_AUTOSYNC_FROM_WORD;
2768 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2770 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2772 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2774 uinfo->value.enumerated.items = 7;
2775 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2776 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2777 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2781 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2783 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2785 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2789 #define HDSP_PASSTHRU(xname, xindex) \
2790 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2793 .info = snd_hdsp_info_passthru, \
2794 .put = snd_hdsp_put_passthru, \
2795 .get = snd_hdsp_get_passthru \
2798 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
2800 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2802 uinfo->value.integer.min = 0;
2803 uinfo->value.integer.max = 1;
2807 static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2809 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2810 unsigned long flags;
2812 spin_lock_irqsave(&hdsp->lock, flags);
2813 ucontrol->value.integer.value[0] = hdsp->passthru;
2814 spin_unlock_irqrestore(&hdsp->lock, flags);
2818 static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2820 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2821 unsigned long flags;
2826 if (!snd_hdsp_use_is_exclusive(hdsp))
2829 val = ucontrol->value.integer.value[0] & 1;
2830 spin_lock_irqsave(&hdsp->lock, flags);
2831 change = (ucontrol->value.integer.value[0] != hdsp->passthru);
2833 err = hdsp_set_passthru(hdsp, val);
2834 spin_unlock_irqrestore(&hdsp->lock, flags);
2835 return err ? err : change;
2838 #define HDSP_LINE_OUT(xname, xindex) \
2839 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2842 .info = snd_hdsp_info_line_out, \
2843 .get = snd_hdsp_get_line_out, \
2844 .put = snd_hdsp_put_line_out \
2847 static int hdsp_line_out(hdsp_t *hdsp)
2849 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2852 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2855 hdsp->control_register |= HDSP_LineOut;
2857 hdsp->control_register &= ~HDSP_LineOut;
2859 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2863 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2865 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2867 uinfo->value.integer.min = 0;
2868 uinfo->value.integer.max = 1;
2872 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2874 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2875 unsigned long flags;
2877 spin_lock_irqsave(&hdsp->lock, flags);
2878 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2879 spin_unlock_irqrestore(&hdsp->lock, flags);
2883 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2885 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2886 unsigned long flags;
2890 if (!snd_hdsp_use_is_exclusive(hdsp))
2892 val = ucontrol->value.integer.value[0] & 1;
2893 spin_lock_irqsave(&hdsp->lock, flags);
2894 change = (int)val != hdsp_line_out(hdsp);
2895 hdsp_set_line_output(hdsp, val);
2896 spin_unlock_irqrestore(&hdsp->lock, flags);
2900 #define HDSP_MIXER(xname, xindex) \
2901 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2904 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2905 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2906 .info = snd_hdsp_info_mixer, \
2907 .get = snd_hdsp_get_mixer, \
2908 .put = snd_hdsp_put_mixer \
2911 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2913 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2915 uinfo->value.integer.min = 0;
2916 uinfo->value.integer.max = 65536;
2917 uinfo->value.integer.step = 1;
2921 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2923 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2924 unsigned long flags;
2929 source = ucontrol->value.integer.value[0];
2930 destination = ucontrol->value.integer.value[1];
2932 if (source >= hdsp->max_channels) {
2933 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2935 addr = hdsp_input_to_output_key(hdsp,source, destination);
2938 spin_lock_irqsave(&hdsp->lock, flags);
2939 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2940 spin_unlock_irqrestore(&hdsp->lock, flags);
2944 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2946 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2947 unsigned long flags;
2954 if (!snd_hdsp_use_is_exclusive(hdsp))
2957 source = ucontrol->value.integer.value[0];
2958 destination = ucontrol->value.integer.value[1];
2960 if (source >= hdsp->max_channels) {
2961 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2963 addr = hdsp_input_to_output_key(hdsp,source, destination);
2966 gain = ucontrol->value.integer.value[2];
2968 spin_lock_irqsave(&hdsp->lock, flags);
2969 change = gain != hdsp_read_gain(hdsp, addr);
2971 hdsp_write_gain(hdsp, addr, gain);
2972 spin_unlock_irqrestore(&hdsp->lock, flags);
2976 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2977 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2980 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2981 .info = snd_hdsp_info_sync_check, \
2982 .get = snd_hdsp_get_wc_sync_check \
2985 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2987 static char *texts[] = {"No Lock", "Lock", "Sync" };
2988 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2990 uinfo->value.enumerated.items = 3;
2991 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2992 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2993 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2997 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2999 int status2 = hdsp_read(hdsp, HDSP_status2Register);
3000 if (status2 & HDSP_wc_lock) {
3001 if (status2 & HDSP_wc_sync) {
3012 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3014 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3016 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
3020 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
3021 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3024 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3025 .info = snd_hdsp_info_sync_check, \
3026 .get = snd_hdsp_get_spdif_sync_check \
3029 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
3031 int status = hdsp_read(hdsp, HDSP_statusRegister);
3032 if (status & HDSP_SPDIFErrorFlag) {
3035 if (status & HDSP_SPDIFSync) {
3044 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3046 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3048 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3052 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3053 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3056 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3057 .info = snd_hdsp_info_sync_check, \
3058 .get = snd_hdsp_get_adatsync_sync_check \
3061 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3063 int status = hdsp_read(hdsp, HDSP_statusRegister);
3064 if (status & HDSP_TimecodeLock) {
3065 if (status & HDSP_TimecodeSync) {
3075 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3077 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3079 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3083 #define HDSP_ADAT_SYNC_CHECK \
3084 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3085 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3086 .info = snd_hdsp_info_sync_check, \
3087 .get = snd_hdsp_get_adat_sync_check \
3090 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3092 int status = hdsp_read(hdsp, HDSP_statusRegister);
3094 if (status & (HDSP_Lock0>>idx)) {
3095 if (status & (HDSP_Sync0>>idx)) {
3105 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3108 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3110 offset = ucontrol->id.index - 1;
3111 snd_assert(offset >= 0);
3113 switch (hdsp->io_type) {
3128 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3132 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3133 HDSP_DA_GAIN("DA Gain", 0),
3134 HDSP_AD_GAIN("AD Gain", 0),
3135 HDSP_PHONE_GAIN("Phones Gain", 0),
3136 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3139 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3141 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3142 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3143 .info = snd_hdsp_control_spdif_info,
3144 .get = snd_hdsp_control_spdif_get,
3145 .put = snd_hdsp_control_spdif_put,
3148 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3149 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3150 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3151 .info = snd_hdsp_control_spdif_stream_info,
3152 .get = snd_hdsp_control_spdif_stream_get,
3153 .put = snd_hdsp_control_spdif_stream_put,
3156 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3157 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3158 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3159 .info = snd_hdsp_control_spdif_mask_info,
3160 .get = snd_hdsp_control_spdif_mask_get,
3161 .private_value = IEC958_AES0_NONAUDIO |
3162 IEC958_AES0_PROFESSIONAL |
3163 IEC958_AES0_CON_EMPHASIS,
3166 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3167 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3168 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3169 .info = snd_hdsp_control_spdif_mask_info,
3170 .get = snd_hdsp_control_spdif_mask_get,
3171 .private_value = IEC958_AES0_NONAUDIO |
3172 IEC958_AES0_PROFESSIONAL |
3173 IEC958_AES0_PRO_EMPHASIS,
3175 HDSP_MIXER("Mixer", 0),
3176 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3177 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3178 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3179 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3180 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3181 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3182 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3183 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3184 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3185 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3186 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3187 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3188 /* 'External Rate' complies with the alsa control naming scheme */
3189 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3190 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3191 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3192 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3193 HDSP_PASSTHRU("Passthru", 0),
3194 HDSP_LINE_OUT("Line Out", 0),
3197 #define HDSP_CONTROLS (sizeof(snd_hdsp_controls)/sizeof(snd_kcontrol_new_t))
3199 #define HDSP_9632_CONTROLS (sizeof(snd_hdsp_9632_controls)/sizeof(snd_kcontrol_new_t))
3201 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3202 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3204 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3208 snd_kcontrol_t *kctl;
3210 for (idx = 0; idx < HDSP_CONTROLS; idx++) {
3211 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3214 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3215 hdsp->spdif_ctl = kctl;
3218 /* ADAT SyncCheck status */
3219 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3220 snd_hdsp_adat_sync_check.index = 1;
3221 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3224 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3225 for (idx = 1; idx < 3; ++idx) {
3226 snd_hdsp_adat_sync_check.index = idx+1;
3227 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3233 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3234 if (hdsp->io_type == H9632) {
3235 for (idx = 0; idx < HDSP_9632_CONTROLS; idx++) {
3236 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3242 /* AEB control for H96xx card */
3243 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3244 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3252 /*------------------------------------------------------------
3254 ------------------------------------------------------------*/
3257 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3259 hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3260 unsigned int status;
3261 unsigned int status2;
3262 char *pref_sync_ref;
3264 char *system_clock_mode;
3268 if (hdsp_check_for_iobox (hdsp)) {
3269 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3273 if (hdsp_check_for_firmware(hdsp)) {
3274 if (hdsp->state & HDSP_FirmwareCached) {
3275 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3276 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3280 snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3285 status = hdsp_read(hdsp, HDSP_statusRegister);
3286 status2 = hdsp_read(hdsp, HDSP_status2Register);
3288 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3289 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3290 hdsp->capture_buffer, hdsp->playback_buffer);
3291 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3292 hdsp->irq, hdsp->port, hdsp->iobase);
3293 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3294 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3295 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3296 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3297 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3299 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3300 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3301 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3302 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3304 snd_iprintf(buffer, "\n");
3306 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3308 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3309 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3310 snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
3311 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3313 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3315 snd_iprintf(buffer, "\n");
3318 switch (hdsp_clock_source(hdsp)) {
3319 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3320 clock_source = "AutoSync";
3322 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3323 clock_source = "Internal 32 kHz";
3325 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3326 clock_source = "Internal 44.1 kHz";
3328 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3329 clock_source = "Internal 48 kHz";
3331 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3332 clock_source = "Internal 64 kHz";
3334 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3335 clock_source = "Internal 88.2 kHz";
3337 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3338 clock_source = "Internal 96 kHz";
3340 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3341 clock_source = "Internal 128 kHz";
3343 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3344 clock_source = "Internal 176.4 kHz";
3346 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3347 clock_source = "Internal 192 kHz";
3350 clock_source = "Error";
3352 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3354 if (hdsp_system_clock_mode(hdsp)) {
3355 system_clock_mode = "Slave";
3357 system_clock_mode = "Master";
3360 switch (hdsp_pref_sync_ref (hdsp)) {
3361 case HDSP_SYNC_FROM_WORD:
3362 pref_sync_ref = "Word Clock";
3364 case HDSP_SYNC_FROM_ADAT_SYNC:
3365 pref_sync_ref = "ADAT Sync";
3367 case HDSP_SYNC_FROM_SPDIF:
3368 pref_sync_ref = "SPDIF";
3370 case HDSP_SYNC_FROM_ADAT1:
3371 pref_sync_ref = "ADAT1";
3373 case HDSP_SYNC_FROM_ADAT2:
3374 pref_sync_ref = "ADAT2";
3376 case HDSP_SYNC_FROM_ADAT3:
3377 pref_sync_ref = "ADAT3";
3380 pref_sync_ref = "Word Clock";
3383 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3385 switch (hdsp_autosync_ref (hdsp)) {
3386 case HDSP_AUTOSYNC_FROM_WORD:
3387 autosync_ref = "Word Clock";
3389 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3390 autosync_ref = "ADAT Sync";
3392 case HDSP_AUTOSYNC_FROM_SPDIF:
3393 autosync_ref = "SPDIF";
3395 case HDSP_AUTOSYNC_FROM_NONE:
3396 autosync_ref = "None";
3398 case HDSP_AUTOSYNC_FROM_ADAT1:
3399 autosync_ref = "ADAT1";
3401 case HDSP_AUTOSYNC_FROM_ADAT2:
3402 autosync_ref = "ADAT2";
3404 case HDSP_AUTOSYNC_FROM_ADAT3:
3405 autosync_ref = "ADAT3";
3408 autosync_ref = "---";
3411 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3413 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3415 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3417 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3419 snd_iprintf(buffer, "\n");
3421 switch (hdsp_spdif_in(hdsp)) {
3422 case HDSP_SPDIFIN_OPTICAL:
3423 snd_iprintf(buffer, "IEC958 input: Optical\n");
3425 case HDSP_SPDIFIN_COAXIAL:
3426 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3428 case HDSP_SPDIFIN_INTERNAL:
3429 snd_iprintf(buffer, "IEC958 input: Internal\n");
3431 case HDSP_SPDIFIN_AES:
3432 snd_iprintf(buffer, "IEC958 input: AES\n");
3435 snd_iprintf(buffer, "IEC958 input: ???\n");
3439 if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3440 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3442 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3445 if (hdsp->control_register & HDSP_SPDIFProfessional) {
3446 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3448 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3451 if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3452 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3454 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3457 if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3458 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3460 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3462 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3463 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3465 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3468 snd_iprintf(buffer, "\n");
3471 x = status & HDSP_Sync0;
3472 if (status & HDSP_Lock0) {
3473 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3475 snd_iprintf(buffer, "ADAT1: No Lock\n");
3478 switch (hdsp->io_type) {
3481 x = status & HDSP_Sync1;
3482 if (status & HDSP_Lock1) {
3483 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3485 snd_iprintf(buffer, "ADAT2: No Lock\n");
3487 x = status & HDSP_Sync2;
3488 if (status & HDSP_Lock2) {
3489 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3491 snd_iprintf(buffer, "ADAT3: No Lock\n");
3498 x = status & HDSP_SPDIFSync;
3499 if (status & HDSP_SPDIFErrorFlag) {
3500 snd_iprintf (buffer, "SPDIF: No Lock\n");
3502 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3505 x = status2 & HDSP_wc_sync;
3506 if (status2 & HDSP_wc_lock) {
3507 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3509 snd_iprintf (buffer, "Word Clock: No Lock\n");
3512 x = status & HDSP_TimecodeSync;
3513 if (status & HDSP_TimecodeLock) {
3514 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3516 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3519 snd_iprintf(buffer, "\n");
3521 /* Informations about H9632 specific controls */
3522 if (hdsp->io_type == H9632) {
3525 switch (hdsp_ad_gain(hdsp)) {
3536 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3538 switch (hdsp_da_gain(hdsp)) {
3549 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3551 switch (hdsp_phone_gain(hdsp)) {
3562 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3564 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3566 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3567 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3569 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3571 snd_iprintf(buffer, "\n");
3576 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3578 snd_info_entry_t *entry;
3580 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3581 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3584 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3586 if (hdsp->capture_buffer_unaligned) {
3587 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES,
3588 hdsp->capture_buffer_unaligned,
3589 hdsp->capture_buffer_addr, 1);
3592 if (hdsp->playback_buffer_unaligned) {
3593 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES,
3594 hdsp->playback_buffer_unaligned,
3595 hdsp->playback_buffer_addr, 0);
3599 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3602 dma_addr_t pb_addr, cb_addr;
3603 unsigned long pb_bus, cb_bus;
3605 cb = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, &cb_addr, 1);
3606 pb = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, &pb_addr, 0);
3608 if (cb == 0 || pb == 0) {
3610 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, cb, cb_addr, 1);
3613 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, pb, pb_addr, 0);
3616 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3620 /* save raw addresses for use when freeing memory later */
3622 hdsp->capture_buffer_unaligned = cb;
3623 hdsp->playback_buffer_unaligned = pb;
3624 hdsp->capture_buffer_addr = cb_addr;
3625 hdsp->playback_buffer_addr = pb_addr;
3627 /* Align to bus-space 64K boundary */
3629 cb_bus = (cb_addr + 0xFFFF) & ~0xFFFFl;
3630 pb_bus = (pb_addr + 0xFFFF) & ~0xFFFFl;
3632 /* Tell the card where it is */
3634 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3635 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3637 hdsp->capture_buffer = cb + (cb_bus - cb_addr);
3638 hdsp->playback_buffer = pb + (pb_bus - pb_addr);
3643 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3647 /* ASSUMPTION: hdsp->lock is either held, or
3648 there is no need to hold it (e.g. during module
3654 SPDIF Input via Coax
3656 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3657 which implies 2 4096 sample, 32Kbyte periods).
3661 hdsp->control_register = HDSP_ClockModeMaster |
3662 HDSP_SPDIFInputCoaxial |
3663 hdsp_encode_latency(7) |
3667 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3669 #ifdef SNDRV_BIG_ENDIAN
3670 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3672 hdsp->control2_register = 0;
3674 if (hdsp->io_type == H9652) {
3675 snd_hdsp_9652_enable_mixer (hdsp);
3677 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3680 hdsp_reset_hw_pointer(hdsp);
3681 hdsp_compute_period_size(hdsp);
3683 /* silence everything */
3685 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3686 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3689 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3690 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3695 if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) {
3699 snd_printk ("sending all inputs and playback streams to line outs.\n");
3701 /* route all inputs to the line outs for easy monitoring. send
3702 odd numbered channels to right, even to left.
3704 if (hdsp->io_type == H9632) {
3705 /* this is the phones/analog output */
3711 for (i = 0; i < hdsp->max_channels; i++) {
3713 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) ||
3714 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) {
3718 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) ||
3719 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) {
3729 /* H9632 specific defaults */
3730 if (hdsp->io_type == H9632) {
3731 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3732 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3735 /* set a default rate so that the channel map is set up.
3738 hdsp_set_rate(hdsp, 48000, 1);
3743 void hdsp_midi_tasklet(unsigned long arg)
3745 hdsp_t *hdsp = (hdsp_t *)arg;
3747 if (hdsp->midi[0].pending) {
3748 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3750 if (hdsp->midi[1].pending) {
3751 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3755 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3757 hdsp_t *hdsp = (hdsp_t *) dev_id;
3758 unsigned int status;
3762 unsigned int midi0status;
3763 unsigned int midi1status;
3766 status = hdsp_read(hdsp, HDSP_statusRegister);
3768 audio = status & HDSP_audioIRQPending;
3769 midi0 = status & HDSP_midi0IRQPending;
3770 midi1 = status & HDSP_midi1IRQPending;
3772 if (!audio && !midi0 && !midi1) {
3776 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3778 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3779 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3782 if (hdsp->capture_substream) {
3783 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3786 if (hdsp->playback_substream) {
3787 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3791 if (midi0 && midi0status) {
3792 /* we disable interrupts for this input until processing is done */
3793 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3794 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3795 hdsp->midi[0].pending = 1;
3798 if (midi1 && midi1status) {
3799 /* we disable interrupts for this input until processing is done */
3800 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3801 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3802 hdsp->midi[1].pending = 1;
3806 tasklet_hi_schedule(&hdsp->midi_tasklet);
3810 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3812 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3813 return hdsp_hw_pointer(hdsp);
3816 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3823 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3825 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3829 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3830 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3832 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3836 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3837 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3839 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3842 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3844 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3845 snd_assert(channel_buf != NULL, return -EIO);
3846 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3851 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3852 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3854 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3857 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3859 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3860 snd_assert(channel_buf != NULL, return -EIO);
3861 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3866 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3867 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3869 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3872 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3873 snd_assert(channel_buf != NULL, return -EIO);
3874 memset(channel_buf + pos * 4, 0, count * 4);
3878 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3880 snd_pcm_runtime_t *runtime = substream->runtime;
3881 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3882 snd_pcm_substream_t *other;
3883 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3884 other = hdsp->capture_substream;
3886 other = hdsp->playback_substream;
3888 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3890 runtime->status->hw_ptr = 0;
3892 struct list_head *pos;
3893 snd_pcm_substream_t *s;
3894 snd_pcm_runtime_t *oruntime = other->runtime;
3895 snd_pcm_group_for_each(pos, substream) {
3896 s = snd_pcm_group_substream_entry(pos);
3898 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3906 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3907 snd_pcm_hw_params_t *params)
3909 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3914 if (hdsp_check_for_iobox (hdsp)) {
3918 if (hdsp_check_for_firmware(hdsp)) {
3919 if (hdsp->state & HDSP_FirmwareCached) {
3920 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3921 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3924 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3929 spin_lock_irq(&hdsp->lock);
3931 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3932 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3933 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3934 this_pid = hdsp->playback_pid;
3935 other_pid = hdsp->capture_pid;
3937 this_pid = hdsp->capture_pid;
3938 other_pid = hdsp->playback_pid;
3941 if ((other_pid > 0) && (this_pid != other_pid)) {
3943 /* The other stream is open, and not by the same
3944 task as this one. Make sure that the parameters
3945 that matter are the same.
3948 if (params_rate(params) != hdsp->system_sample_rate) {
3949 spin_unlock_irq(&hdsp->lock);
3950 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3954 if (params_period_size(params) != hdsp->period_bytes / 4) {
3955 spin_unlock_irq(&hdsp->lock);
3956 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3962 spin_unlock_irq(&hdsp->lock);
3966 spin_unlock_irq(&hdsp->lock);
3969 /* how to make sure that the rate matches an externally-set one ?
3972 spin_lock_irq(&hdsp->lock);
3973 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3974 spin_unlock_irq(&hdsp->lock);
3975 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3978 spin_unlock_irq(&hdsp->lock);
3981 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3982 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3989 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3990 snd_pcm_channel_info_t *info)
3992 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3995 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3997 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
4001 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4007 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
4008 unsigned int cmd, void *arg)
4011 case SNDRV_PCM_IOCTL1_RESET:
4013 return snd_hdsp_reset(substream);
4015 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4017 snd_pcm_channel_info_t *info = arg;
4018 return snd_hdsp_channel_info(substream, info);
4024 return snd_pcm_lib_ioctl(substream, cmd, arg);
4027 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
4029 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4030 snd_pcm_substream_t *other;
4033 if (hdsp_check_for_iobox (hdsp)) {
4037 if (hdsp_check_for_firmware(hdsp)) {
4038 if (hdsp->state & HDSP_FirmwareCached) {
4039 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4040 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4043 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4048 spin_lock(&hdsp->lock);
4049 running = hdsp->running;
4051 case SNDRV_PCM_TRIGGER_START:
4052 running |= 1 << substream->stream;
4054 case SNDRV_PCM_TRIGGER_STOP:
4055 running &= ~(1 << substream->stream);
4059 spin_unlock(&hdsp->lock);
4062 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4063 other = hdsp->capture_substream;
4065 other = hdsp->playback_substream;
4068 struct list_head *pos;
4069 snd_pcm_substream_t *s;
4070 snd_pcm_group_for_each(pos, substream) {
4071 s = snd_pcm_group_substream_entry(pos);
4073 snd_pcm_trigger_done(s, substream);
4074 if (cmd == SNDRV_PCM_TRIGGER_START)
4075 running |= 1 << s->stream;
4077 running &= ~(1 << s->stream);
4081 if (cmd == SNDRV_PCM_TRIGGER_START) {
4082 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4083 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4084 hdsp_silence_playback(hdsp);
4087 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4088 hdsp_silence_playback(hdsp);
4091 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4092 hdsp_silence_playback(hdsp);
4095 snd_pcm_trigger_done(substream, substream);
4096 if (!hdsp->running && running)
4097 hdsp_start_audio(hdsp);
4098 else if (hdsp->running && !running)
4099 hdsp_stop_audio(hdsp);
4100 hdsp->running = running;
4101 spin_unlock(&hdsp->lock);
4106 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4108 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4111 if (hdsp_check_for_iobox (hdsp)) {
4115 if (hdsp_check_for_firmware(hdsp)) {
4116 if (hdsp->state & HDSP_FirmwareCached) {
4117 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4118 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4121 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4126 spin_lock(&hdsp->lock);
4128 hdsp_reset_hw_pointer(hdsp);
4129 spin_unlock(&hdsp->lock);
4133 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4135 .info = (SNDRV_PCM_INFO_MMAP |
4136 SNDRV_PCM_INFO_MMAP_VALID |
4137 SNDRV_PCM_INFO_NONINTERLEAVED |
4138 SNDRV_PCM_INFO_SYNC_START |
4139 SNDRV_PCM_INFO_DOUBLE),
4140 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4141 .rates = (SNDRV_PCM_RATE_32000 |
4142 SNDRV_PCM_RATE_44100 |
4143 SNDRV_PCM_RATE_48000 |
4144 SNDRV_PCM_RATE_64000 |
4145 SNDRV_PCM_RATE_88200 |
4146 SNDRV_PCM_RATE_96000),
4150 .channels_max = HDSP_MAX_CHANNELS,
4151 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4152 .period_bytes_min = (64 * 4) * 10,
4153 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4159 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4161 .info = (SNDRV_PCM_INFO_MMAP |
4162 SNDRV_PCM_INFO_MMAP_VALID |
4163 SNDRV_PCM_INFO_NONINTERLEAVED |
4164 SNDRV_PCM_INFO_SYNC_START),
4165 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4166 .rates = (SNDRV_PCM_RATE_32000 |
4167 SNDRV_PCM_RATE_44100 |
4168 SNDRV_PCM_RATE_48000 |
4169 SNDRV_PCM_RATE_64000 |
4170 SNDRV_PCM_RATE_88200 |
4171 SNDRV_PCM_RATE_96000),
4175 .channels_max = HDSP_MAX_CHANNELS,
4176 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4177 .period_bytes_min = (64 * 4) * 10,
4178 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4184 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4186 #define HDSP_PERIOD_SIZES sizeof(hdsp_period_sizes) / sizeof(hdsp_period_sizes[0])
4188 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4189 .count = HDSP_PERIOD_SIZES,
4190 .list = hdsp_period_sizes,
4194 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4196 #define HDSP_9632_SAMPLE_RATES sizeof(hdsp_9632_sample_rates) / sizeof(hdsp_9632_sample_rates[0])
4198 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4199 .count = HDSP_9632_SAMPLE_RATES,
4200 .list = hdsp_9632_sample_rates,
4204 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4205 snd_pcm_hw_rule_t *rule)
4207 hdsp_t *hdsp = rule->private;
4208 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4209 if (hdsp->io_type == H9632) {
4210 unsigned int list[3];
4211 list[0] = hdsp->qs_in_channels;
4212 list[1] = hdsp->ds_in_channels;
4213 list[2] = hdsp->ss_in_channels;
4214 return snd_interval_list(c, 3, list, 0);
4216 unsigned int list[2];
4217 list[0] = hdsp->ds_in_channels;
4218 list[1] = hdsp->ss_in_channels;
4219 return snd_interval_list(c, 2, list, 0);
4223 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4224 snd_pcm_hw_rule_t *rule)
4226 unsigned int list[3];
4227 hdsp_t *hdsp = rule->private;
4228 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4229 if (hdsp->io_type == H9632) {
4230 list[0] = hdsp->qs_out_channels;
4231 list[1] = hdsp->ds_out_channels;
4232 list[2] = hdsp->ss_out_channels;
4233 return snd_interval_list(c, 3, list, 0);
4235 list[0] = hdsp->ds_out_channels;
4236 list[1] = hdsp->ss_out_channels;
4238 return snd_interval_list(c, 2, list, 0);
4241 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4242 snd_pcm_hw_rule_t *rule)
4244 hdsp_t *hdsp = rule->private;
4245 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4246 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4247 if (r->min > 96000 && hdsp->io_type == H9632) {
4248 snd_interval_t t = {
4249 .min = hdsp->qs_in_channels,
4250 .max = hdsp->qs_in_channels,
4253 return snd_interval_refine(c, &t);
4254 } else if (r->min > 48000 && r->max <= 96000) {
4255 snd_interval_t t = {
4256 .min = hdsp->ds_in_channels,
4257 .max = hdsp->ds_in_channels,
4260 return snd_interval_refine(c, &t);
4261 } else if (r->max < 64000) {
4262 snd_interval_t t = {
4263 .min = hdsp->ss_in_channels,
4264 .max = hdsp->ss_in_channels,
4267 return snd_interval_refine(c, &t);
4272 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4273 snd_pcm_hw_rule_t *rule)
4275 hdsp_t *hdsp = rule->private;
4276 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4277 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4278 if (r->min > 96000 && hdsp->io_type == H9632) {
4279 snd_interval_t t = {
4280 .min = hdsp->qs_out_channels,
4281 .max = hdsp->qs_out_channels,
4284 return snd_interval_refine(c, &t);
4285 } else if (r->min > 48000 && r->max <= 96000) {
4286 snd_interval_t t = {
4287 .min = hdsp->ds_out_channels,
4288 .max = hdsp->ds_out_channels,
4291 return snd_interval_refine(c, &t);
4292 } else if (r->max < 64000) {
4293 snd_interval_t t = {
4294 .min = hdsp->ss_out_channels,
4295 .max = hdsp->ss_out_channels,
4298 return snd_interval_refine(c, &t);
4303 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4304 snd_pcm_hw_rule_t *rule)
4306 hdsp_t *hdsp = rule->private;
4307 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4309 if (c->min >= hdsp->ss_out_channels) {
4310 snd_interval_t t = {
4315 return snd_interval_refine(r, &t);
4316 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4317 snd_interval_t t = {
4322 return snd_interval_refine(r, &t);
4323 } else if (c->max <= hdsp->ds_out_channels) {
4324 snd_interval_t t = {
4329 return snd_interval_refine(r, &t);
4334 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4335 snd_pcm_hw_rule_t *rule)
4337 hdsp_t *hdsp = rule->private;
4338 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4339 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4340 if (c->min >= hdsp->ss_in_channels) {
4341 snd_interval_t t = {
4346 return snd_interval_refine(r, &t);
4347 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4348 snd_interval_t t = {
4353 return snd_interval_refine(r, &t);
4354 } else if (c->max <= hdsp->ds_in_channels) {
4355 snd_interval_t t = {
4360 return snd_interval_refine(r, &t);
4365 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4367 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4368 unsigned long flags;
4369 snd_pcm_runtime_t *runtime = substream->runtime;
4371 if (hdsp_check_for_iobox (hdsp)) {
4375 if (hdsp_check_for_firmware(hdsp)) {
4376 if (hdsp->state & HDSP_FirmwareCached) {
4377 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4378 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4381 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4386 spin_lock_irqsave(&hdsp->lock, flags);
4388 snd_pcm_set_sync(substream);
4390 runtime->hw = snd_hdsp_playback_subinfo;
4391 runtime->dma_area = hdsp->playback_buffer;
4392 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4394 if (hdsp->capture_substream == NULL) {
4395 hdsp_stop_audio(hdsp);
4396 hdsp_set_thru(hdsp, -1, 0);
4399 hdsp->playback_pid = current->pid;
4400 hdsp->playback_substream = substream;
4402 spin_unlock_irqrestore(&hdsp->lock, flags);
4404 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4405 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4406 if (hdsp->io_type == H9632) {
4407 runtime->hw.channels_min = hdsp->qs_out_channels;
4408 runtime->hw.channels_max = hdsp->ss_out_channels;
4409 runtime->hw.rate_max = 192000;
4410 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4411 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4414 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4415 snd_hdsp_hw_rule_out_channels, hdsp,
4416 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4417 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4418 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4419 SNDRV_PCM_HW_PARAM_RATE, -1);
4420 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4421 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4422 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4424 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4425 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4426 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4427 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4431 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4433 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4434 unsigned long flags;
4436 spin_lock_irqsave(&hdsp->lock, flags);
4438 hdsp->playback_pid = -1;
4439 hdsp->playback_substream = NULL;
4441 spin_unlock_irqrestore(&hdsp->lock, flags);
4443 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4444 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4445 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4450 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4452 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4453 unsigned long flags;
4454 snd_pcm_runtime_t *runtime = substream->runtime;
4456 if (hdsp_check_for_iobox (hdsp)) {
4460 if (hdsp_check_for_firmware(hdsp)) {
4461 if (hdsp->state & HDSP_FirmwareCached) {
4462 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4463 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4466 snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4471 spin_lock_irqsave(&hdsp->lock, flags);
4473 snd_pcm_set_sync(substream);
4475 runtime->hw = snd_hdsp_capture_subinfo;
4476 runtime->dma_area = hdsp->capture_buffer;
4477 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4479 if (hdsp->playback_substream == NULL) {
4480 hdsp_stop_audio(hdsp);
4481 hdsp_set_thru(hdsp, -1, 0);
4484 hdsp->capture_pid = current->pid;
4485 hdsp->capture_substream = substream;
4487 spin_unlock_irqrestore(&hdsp->lock, flags);
4489 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4490 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4491 if (hdsp->io_type == H9632) {
4492 runtime->hw.channels_min = hdsp->qs_in_channels;
4493 runtime->hw.channels_max = hdsp->ss_in_channels;
4494 runtime->hw.rate_max = 192000;
4495 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4496 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4498 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4499 snd_hdsp_hw_rule_in_channels, hdsp,
4500 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4501 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4502 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4503 SNDRV_PCM_HW_PARAM_RATE, -1);
4504 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4505 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4506 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4510 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4512 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4513 unsigned long flags;
4515 spin_lock_irqsave(&hdsp->lock, flags);
4517 hdsp->capture_pid = -1;
4518 hdsp->capture_substream = NULL;
4520 spin_unlock_irqrestore(&hdsp->lock, flags);
4524 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4526 /* we have nothing to initialize but the call is required */
4531 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4533 hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4534 void __user *argp = (void __user *)arg;
4537 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4538 hdsp_peak_rms_t __user *peak_rms;
4541 if (hdsp->io_type == H9652) {
4542 unsigned long rms_low, rms_high;
4543 int doublespeed = 0;
4544 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4546 peak_rms = (hdsp_peak_rms_t __user *)arg;
4547 for (i = 0; i < 26; ++i) {
4548 if (!(doublespeed && (i & 4))) {
4549 if (copy_to_user_fromio((void __user *)peak_rms->input_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-i*4, 4) != 0)
4551 if (copy_to_user_fromio((void __user *)peak_rms->playback_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4553 if (copy_to_user_fromio((void __user *)peak_rms->output_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-2*(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4555 rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8) & 0xFFFFFF00;
4556 rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8+4) & 0xFFFFFF00;
4557 rms_high += (rms_low >> 24);
4559 if (copy_to_user((void __user *)peak_rms->input_rms+i*8, &rms_low, 4) != 0)
4561 if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, &rms_high, 4) != 0)
4563 rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4564 rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4565 rms_high += (rms_low >> 24);
4567 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, &rms_low, 4) != 0)
4569 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, &rms_high, 4) != 0)
4571 rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4572 rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4573 rms_high += (rms_low >> 24);
4575 if (copy_to_user((void __user *)peak_rms->output_rms+i*8, &rms_low, 4) != 0)
4577 if (copy_to_user((void __user *)peak_rms->output_rms+i*8+4, &rms_high, 4) != 0)
4583 if (hdsp->io_type == H9632) {
4585 hdsp_9632_meters_t *m;
4586 int doublespeed = 0;
4587 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4589 m = (hdsp_9632_meters_t *)(hdsp->iobase+HDSP_9632_metersBase);
4590 peak_rms = (hdsp_peak_rms_t __user *)arg;
4591 for (i = 0, j = 0; i < 16; ++i, ++j) {
4592 if (copy_to_user((void __user *)peak_rms->input_peaks+i*4, &(m->input_peak[j]), 4) != 0)
4594 if (copy_to_user((void __user *)peak_rms->playback_peaks+i*4, &(m->playback_peak[j]), 4) != 0)
4596 if (copy_to_user((void __user *)peak_rms->output_peaks+i*4, &(m->output_peak[j]), 4) != 0)
4598 if (copy_to_user((void __user *)peak_rms->input_rms+i*8, &(m->input_rms_low[j]), 4) != 0)
4600 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, &(m->playback_rms_low[j]), 4) != 0)
4602 if (copy_to_user((void __user *)peak_rms->output_rms+i*8, &(m->output_rms_low[j]), 4) != 0)
4604 if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, &(m->input_rms_high[j]), 4) != 0)
4606 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, &(m->playback_rms_high[j]), 4) != 0)
4608 if (copy_to_user((void __user *)peak_rms->output_rms+i*8+4, &(m->output_rms_high[j]), 4) != 0)
4610 if (doublespeed && i == 3) i += 4;
4614 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4615 snd_printk("firmware needs to be uploaded to the card.\n");
4618 peak_rms = (hdsp_peak_rms_t __user *)arg;
4619 for (i = 0; i < 26; ++i) {
4620 if (copy_to_user((void __user *)peak_rms->playback_peaks+i*4, (void *)hdsp->iobase+HDSP_playbackPeakLevel+i*4, 4) != 0)
4622 if (copy_to_user((void __user *)peak_rms->input_peaks+i*4, (void *)hdsp->iobase+HDSP_inputPeakLevel+i*4, 4) != 0)
4625 for (i = 0; i < 26; ++i) {
4626 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8, 4) != 0)
4628 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8+4, 4) != 0)
4630 if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8, 4) != 0)
4632 if (copy_to_user((void __user *)peak_rms->input_rms+i*8, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8+4, 4) != 0)
4635 for (i = 0; i < 28; ++i) {
4636 if (copy_to_user((void __user *)peak_rms->output_peaks+i*4, (void *)hdsp->iobase+HDSP_outputPeakLevel+i*4, 4) != 0)
4641 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4642 hdsp_config_info_t info;
4643 unsigned long flags;
4646 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4647 snd_printk("Firmware needs to be uploaded to the card.\n");
4650 spin_lock_irqsave(&hdsp->lock, flags);
4651 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4652 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4653 if (hdsp->io_type != H9632) {
4654 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4656 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4657 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4658 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4660 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4661 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4662 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4663 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4664 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4665 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4666 info.system_sample_rate = hdsp->system_sample_rate;
4667 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4668 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4669 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4670 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4671 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4672 info.passthru = (unsigned char)hdsp->passthru;
4673 if (hdsp->io_type == H9632) {
4674 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4675 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4676 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4677 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4680 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4681 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4683 spin_unlock_irqrestore(&hdsp->lock, flags);
4684 if (copy_to_user(argp, &info, sizeof(info)))
4688 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4689 hdsp_9632_aeb_t h9632_aeb;
4691 if (hdsp->io_type != H9632) return -EINVAL;
4692 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4693 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4694 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4698 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4699 hdsp_version_t hdsp_version;
4702 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4703 if (hdsp->io_type == Undefined) {
4704 if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4708 hdsp_version.io_type = hdsp->io_type;
4709 hdsp_version.firmware_rev = hdsp->firmware_rev;
4710 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4715 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4716 hdsp_firmware_t __user *firmware;
4717 unsigned long __user *firmware_data;
4720 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4721 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4722 if (hdsp->io_type == Undefined) return -EINVAL;
4724 snd_printk("initializing firmware upload\n");
4725 firmware = (hdsp_firmware_t __user *)argp;
4727 if (get_user(firmware_data, &firmware->firmware_data)) {
4731 if (hdsp_check_for_iobox (hdsp)) {
4735 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(unsigned long)*24413) != 0) {
4739 hdsp->state |= HDSP_FirmwareCached;
4741 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4745 if (!(hdsp->state & HDSP_InitializationComplete)) {
4746 snd_hdsp_initialize_channels(hdsp);
4748 snd_hdsp_initialize_midi_flush(hdsp);
4750 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4751 snd_printk("error creating alsa devices\n");
4757 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4758 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4759 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4769 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4770 .open = snd_hdsp_playback_open,
4771 .close = snd_hdsp_playback_release,
4772 .ioctl = snd_hdsp_ioctl,
4773 .hw_params = snd_hdsp_hw_params,
4774 .prepare = snd_hdsp_prepare,
4775 .trigger = snd_hdsp_trigger,
4776 .pointer = snd_hdsp_hw_pointer,
4777 .copy = snd_hdsp_playback_copy,
4778 .silence = snd_hdsp_hw_silence,
4781 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4782 .open = snd_hdsp_capture_open,
4783 .close = snd_hdsp_capture_release,
4784 .ioctl = snd_hdsp_ioctl,
4785 .hw_params = snd_hdsp_hw_params,
4786 .prepare = snd_hdsp_prepare,
4787 .trigger = snd_hdsp_trigger,
4788 .pointer = snd_hdsp_hw_pointer,
4789 .copy = snd_hdsp_capture_copy,
4792 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4798 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4802 hw->private_data = hdsp;
4803 strcpy(hw->name, "HDSP hwdep interface");
4805 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4806 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4807 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4812 static int __devinit snd_hdsp_create_pcm(snd_card_t *card,
4818 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4822 pcm->private_data = hdsp;
4823 strcpy(pcm->name, hdsp->card_name);
4825 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4826 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4828 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4833 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4835 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4836 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4839 static inline void snd_hdsp_9652_disable_mixer (hdsp_t *hdsp)
4841 hdsp->control2_register &= ~HDSP_9652_ENABLE_MIXER;
4842 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4845 static inline int snd_hdsp_enable_io (hdsp_t *hdsp)
4849 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4853 for (i = 0; i < hdsp->max_channels; ++i) {
4854 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4855 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4861 static inline void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4863 int status, aebi_channels, aebo_channels;
4865 switch (hdsp->io_type) {
4867 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4868 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4869 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4873 hdsp->card_name = "RME Hammerfall HDSP 9652";
4874 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4875 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4879 status = hdsp_read(hdsp, HDSP_statusRegister);
4880 /* HDSP_AEBx bits are low when AEB are connected */
4881 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4882 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4883 hdsp->card_name = "RME Hammerfall HDSP 9632";
4884 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4885 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4886 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4887 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4888 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4889 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4893 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4894 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4895 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4899 /* should never get here */
4904 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4906 snd_hdsp_flush_midi_input (hdsp, 0);
4907 snd_hdsp_flush_midi_input (hdsp, 1);
4910 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4914 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4915 snd_printk("Error creating pcm interface\n");
4920 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4921 snd_printk("Error creating first midi interface\n");
4926 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4927 snd_printk("Error creating second midi interface\n");
4931 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4932 snd_printk("Error creating ctl interface\n");
4936 snd_hdsp_proc_init(hdsp);
4938 hdsp->system_sample_rate = -1;
4939 hdsp->playback_pid = -1;
4940 hdsp->capture_pid = -1;
4941 hdsp->capture_substream = NULL;
4942 hdsp->playback_substream = NULL;
4944 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4945 snd_printk("Error setting default values\n");
4949 if (!(hdsp->state & HDSP_InitializationComplete)) {
4950 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4951 hdsp->port, hdsp->irq);
4953 if ((err = snd_card_register(card)) < 0) {
4954 snd_printk("error registering card\n");
4957 hdsp->state |= HDSP_InitializationComplete;
4963 static int __devinit snd_hdsp_create(snd_card_t *card,
4967 struct pci_dev *pci = hdsp->pci;
4974 hdsp->midi[0].rmidi = NULL;
4975 hdsp->midi[1].rmidi = NULL;
4976 hdsp->midi[0].input = NULL;
4977 hdsp->midi[1].input = NULL;
4978 hdsp->midi[0].output = NULL;
4979 hdsp->midi[1].output = NULL;
4980 spin_lock_init(&hdsp->midi[0].lock);
4981 spin_lock_init(&hdsp->midi[1].lock);
4983 hdsp->res_port = NULL;
4984 hdsp->control_register = 0;
4985 hdsp->control2_register = 0;
4986 hdsp->io_type = Undefined;
4987 hdsp->max_channels = 26;
4991 spin_lock_init(&hdsp->lock);
4993 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4995 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4997 /* From Martin Bjoernsen :
4998 "It is important that the card's latency timer register in
4999 the PCI configuration space is set to a value much larger
5000 than 0 by the computer's BIOS or the driver.
5001 The windows driver always sets this 8 bit register [...]
5002 to its maximum 255 to avoid problems with some computers."
5004 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5006 strcpy(card->driver, "H-DSP");
5007 strcpy(card->mixername, "Xilinx FPGA");
5009 switch (hdsp->firmware_rev & 0xff) {
5013 hdsp->card_name = "RME Hammerfall DSP";
5019 hdsp->card_name = "RME HDSP 9652";
5024 hdsp->card_name = "RME HDSP 9632";
5025 hdsp->max_channels = 16;
5032 if ((err = pci_enable_device(pci)) < 0) {
5036 pci_set_master(hdsp->pci);
5038 hdsp->port = pci_resource_start(pci, 0);
5040 if ((hdsp->res_port = request_mem_region(hdsp->port, HDSP_IO_EXTENT, "hdsp")) == NULL) {
5041 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5045 if ((hdsp->iobase = (unsigned long) ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == 0) {
5046 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5050 if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5051 snd_printk("unable to use IRQ %d\n", pci->irq);
5055 hdsp->irq = pci->irq;
5056 hdsp->precise_ptr = precise_ptr;
5058 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5062 if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) {
5063 /* no iobox connected, we defer initialization */
5064 snd_printk("card initialization pending : waiting for firmware\n");
5065 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5071 if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5075 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5076 snd_printk("card initialization pending : waiting for firmware\n");
5077 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5083 snd_printk("Firmware already loaded, initializing card.\n");
5085 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5086 hdsp->io_type = Multiface;
5088 hdsp->io_type = Digiface;
5092 hdsp->io_type = H9652;
5096 hdsp->io_type = H9632;
5099 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5103 snd_hdsp_initialize_channels(hdsp);
5104 snd_hdsp_initialize_midi_flush(hdsp);
5106 hdsp->state |= HDSP_FirmwareLoaded;
5108 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5115 static int snd_hdsp_free(hdsp_t *hdsp)
5117 if (hdsp->res_port) {
5118 /* stop the audio, and cancel all interrupts */
5119 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5120 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5124 free_irq(hdsp->irq, (void *)hdsp);
5126 snd_hdsp_free_buffers(hdsp);
5129 iounmap((void *) hdsp->iobase);
5131 if (hdsp->res_port) {
5132 release_resource(hdsp->res_port);
5133 kfree_nocheck(hdsp->res_port);
5139 static void snd_hdsp_card_free(snd_card_t *card)
5141 hdsp_t *hdsp = (hdsp_t *) card->private_data;
5144 snd_hdsp_free(hdsp);
5147 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5148 const struct pci_device_id *pci_id)
5155 if (dev >= SNDRV_CARDS)
5162 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5165 hdsp = (hdsp_t *) card->private_data;
5166 card->private_free = snd_hdsp_card_free;
5169 snd_card_set_dev(card, &pci->dev);
5171 if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
5172 snd_card_free(card);
5176 strcpy(card->shortname, "Hammerfall DSP");
5177 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5178 hdsp->port, hdsp->irq);
5180 if ((err = snd_card_register(card)) < 0) {
5181 snd_card_free(card);
5184 pci_set_drvdata(pci, card);
5189 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5191 snd_card_free(pci_get_drvdata(pci));
5192 pci_set_drvdata(pci, NULL);
5195 static struct pci_driver driver = {
5196 .name = "RME Hammerfall DSP",
5197 .id_table = snd_hdsp_ids,
5198 .probe = snd_hdsp_probe,
5199 .remove = __devexit_p(snd_hdsp_remove),
5202 static int __init alsa_card_hdsp_init(void)
5204 return pci_module_init(&driver);
5207 static void __exit alsa_card_hdsp_exit(void)
5209 pci_unregister_driver(&driver);
5212 module_init(alsa_card_hdsp_init)
5213 module_exit(alsa_card_hdsp_exit)