2 * Driver for Digigram VXpocket soundcards
4 * lowlevel routines for VXpocket soundcards
6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <sound/driver.h>
24 #include <linux/delay.h>
25 #include <sound/core.h>
29 #define chip_t vx_core_t
32 static int vxp_reg_offset[VX_REG_MAX] = {
33 [VX_ICR] = 0x00, // ICR
34 [VX_CVR] = 0x01, // CVR
35 [VX_ISR] = 0x02, // ISR
36 [VX_IVR] = 0x03, // IVR
37 [VX_RXH] = 0x05, // RXH
38 [VX_RXM] = 0x06, // RXM
39 [VX_RXL] = 0x07, // RXL
40 [VX_DMA] = 0x04, // DMA
41 [VX_CDSP] = 0x08, // CDSP
42 [VX_LOFREQ] = 0x09, // LFREQ
43 [VX_HIFREQ] = 0x0a, // HFREQ
44 [VX_DATA] = 0x0b, // DATA
45 [VX_MICRO] = 0x0c, // MICRO
46 [VX_DIALOG] = 0x0d, // DIALOG
47 [VX_CSUER] = 0x0e, // CSUER
48 [VX_RUER] = 0x0f, // RUER
52 inline static unsigned long vxp_reg_addr(vx_core_t *_chip, int reg)
54 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
55 return chip->port + vxp_reg_offset[reg];
59 * snd_vx_inb - read a byte from the register
60 * @offset: register offset
62 static unsigned char vxp_inb(vx_core_t *chip, int offset)
64 return inb(vxp_reg_addr(chip, offset));
68 * snd_vx_outb - write a byte on the register
69 * @offset: the register offset
70 * @val: the value to write
72 static void vxp_outb(vx_core_t *chip, int offset, unsigned char val)
74 outb(val, vxp_reg_addr(chip, offset));
78 * redefine macros to call directly
81 #define vx_inb(chip,reg) vxp_inb((vx_core_t*)(chip), VX_##reg)
83 #define vx_outb(chip,reg,val) vxp_outb((vx_core_t*)(chip), VX_##reg,val)
87 * vx_check_magic - check the magic word on xilinx
89 * returns zero if a magic word is detected, or a negative error code.
91 static int vx_check_magic(vx_core_t *chip)
93 unsigned long end_time = jiffies + HZ / 5;
96 c = vx_inb(chip, CDSP);
99 snd_vx_delay(chip, 10);
100 } while (time_after_eq(end_time, jiffies));
101 snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
107 * vx_reset_dsp - reset the DSP
110 #define XX_DSP_RESET_WAIT_TIME 2 /* ms */
112 static void vxp_reset_dsp(vx_core_t *_chip)
114 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
116 /* set the reset dsp bit to 1 */
117 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK);
119 mdelay(XX_DSP_RESET_WAIT_TIME);
121 chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK;
122 vx_outb(chip, CDSP, chip->regCDSP);
124 mdelay(XX_DSP_RESET_WAIT_TIME);
130 static void vxp_reset_codec(vx_core_t *_chip)
132 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
134 /* Set the reset CODEC bit to 1. */
135 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
137 snd_vx_delay(_chip, 10);
138 /* Set the reset CODEC bit to 0. */
139 chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
140 vx_outb(chip, CDSP, chip->regCDSP);
142 snd_vx_delay(_chip, 1);
146 * vx_load_xilinx_binary - load the xilinx binary image
147 * the binary image is the binary array converted from the bitstream file.
149 static int vxp_load_xilinx_binary(vx_core_t *_chip, const snd_hwdep_dsp_image_t *xilinx)
151 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
154 int regCSUER, regRUER;
155 unsigned char *image, data;
157 /* Switch to programmation mode */
158 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
159 vx_outb(chip, DIALOG, chip->regDIALOG);
161 /* Save register CSUER and RUER */
162 regCSUER = vx_inb(chip, CSUER);
163 regRUER = vx_inb(chip, RUER);
165 /* reset HF0 and HF1 */
166 vx_outb(chip, ICR, 0);
168 /* Wait for answer HF2 equal to 1 */
169 snd_printdd(KERN_DEBUG "check ISR_HF2\n");
170 if (vx_check_isr(_chip, ISR_HF2, ISR_HF2, 20) < 0)
173 /* set HF1 for loading xilinx binary */
174 vx_outb(chip, ICR, ICR_HF1);
175 image = xilinx->image;
176 for (i = 0; i < xilinx->length; i++, image++) {
177 __get_user(data, image);
178 if (vx_wait_isr_bit(_chip, ISR_TX_EMPTY) < 0)
180 vx_outb(chip, TXL, data);
181 /* wait for reading */
182 if (vx_wait_for_rx_full(_chip) < 0)
184 c = vx_inb(chip, RXL);
186 snd_printk(KERN_ERR "vxpocket: load xilinx mismatch at %d: 0x%x != 0x%x\n", i, c, (int)data);
190 vx_outb(chip, ICR, 0);
193 if (vx_check_isr(_chip, ISR_HF3, ISR_HF3, 20) < 0)
196 /* read the number of bytes received */
197 if (vx_wait_for_rx_full(_chip) < 0)
200 c = (int)vx_inb(chip, RXH) << 16;
201 c |= (int)vx_inb(chip, RXM) << 8;
202 c |= vx_inb(chip, RXL);
204 snd_printdd(KERN_DEBUG "xilinx: dsp size received 0x%x, orig 0x%x\n", c, xilinx->length);
206 vx_outb(chip, ICR, ICR_HF0);
208 /* TEMPO 250ms : wait until Xilinx is downloaded */
209 snd_vx_delay(_chip, 300);
211 /* test magical word */
212 if (vx_check_magic(_chip) < 0)
215 /* Restore register 0x0E and 0x0F (thus replacing COR and FCSR) */
216 vx_outb(chip, CSUER, regCSUER);
217 vx_outb(chip, RUER, regRUER);
219 /* Reset the Xilinx's signal enabling IO access */
220 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
221 vx_outb(chip, DIALOG, chip->regDIALOG);
222 vx_inb(chip, DIALOG);
223 snd_vx_delay(_chip, 10);
224 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
225 vx_outb(chip, DIALOG, chip->regDIALOG);
226 vx_inb(chip, DIALOG);
228 /* Reset of the Codec */
229 vxp_reset_codec(_chip);
235 vx_outb(chip, CSUER, regCSUER);
236 vx_outb(chip, RUER, regRUER);
237 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
238 vx_outb(chip, DIALOG, chip->regDIALOG);
244 * vxp_load_dsp - load_dsp callback
246 static int vxp_load_dsp(vx_core_t *vx, const snd_hwdep_dsp_image_t *dsp)
251 snd_printdd("loading dsp [%d] %s, size = %d\n", dsp->index, dsp->name, dsp->length);
253 switch (dsp->index) {
256 if ((err = vx_check_magic(vx)) < 0)
258 if ((err = snd_vx_load_boot_image(vx, dsp)) < 0)
263 return vxp_load_xilinx_binary(vx, dsp);
266 return snd_vx_dsp_boot(vx, dsp);
269 return snd_vx_dsp_load(vx, dsp);
278 * vx_test_and_ack - test and acknowledge interrupt
280 * called from irq hander, too
284 static int vxp_test_and_ack(vx_core_t *_chip)
286 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
288 /* not booted yet? */
289 if (! (_chip->chip_status & VX_STAT_XILINX_LOADED))
292 if (! (vx_inb(chip, DIALOG) & VXP_DLG_MEMIRQ_MASK))
295 /* ok, interrupts generated, now ack it */
296 /* set ACQUIT bit up and down */
297 vx_outb(chip, DIALOG, chip->regDIALOG | VXP_DLG_ACK_MEMIRQ_MASK);
298 /* useless read just to spend some time and maintain
299 * the ACQUIT signal up for a while ( a bus cycle )
301 vx_inb(chip, DIALOG);
302 vx_outb(chip, DIALOG, chip->regDIALOG & ~VXP_DLG_ACK_MEMIRQ_MASK);
309 * vx_validate_irq - enable/disable IRQ
311 static void vxp_validate_irq(vx_core_t *_chip, int enable)
313 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
315 /* Set the interrupt enable bit to 1 in CDSP register */
317 chip->regCDSP |= VXP_CDSP_VALID_IRQ_MASK;
319 chip->regCDSP &= ~VXP_CDSP_VALID_IRQ_MASK;
320 vx_outb(chip, CDSP, chip->regCDSP);
324 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
325 * @do_write: 0 = read, 1 = set up for DMA write
327 static void vx_setup_pseudo_dma(vx_core_t *_chip, int do_write)
329 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
331 /* Interrupt mode and HREQ pin enabled for host transmit / receive data transfers */
332 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
333 /* Reset the pseudo-dma register */
335 vx_outb(chip, ISR, 0);
337 /* Select DMA in read/write transfer mode and in 16-bit accesses */
338 chip->regDIALOG |= VXP_DLG_DMA16_SEL_MASK;
339 chip->regDIALOG |= do_write ? VXP_DLG_DMAWRITE_SEL_MASK : VXP_DLG_DMAREAD_SEL_MASK;
340 vx_outb(chip, DIALOG, chip->regDIALOG);
345 * vx_release_pseudo_dma - disable the pseudo-DMA mode
347 static void vx_release_pseudo_dma(vx_core_t *_chip)
349 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
351 /* Disable DMA and 16-bit accesses */
352 chip->regDIALOG &= ~(VXP_DLG_DMAWRITE_SEL_MASK|
353 VXP_DLG_DMAREAD_SEL_MASK|
354 VXP_DLG_DMA16_SEL_MASK);
355 vx_outb(chip, DIALOG, chip->regDIALOG);
356 /* HREQ pin disabled. */
357 vx_outb(chip, ICR, 0);
361 * vx_pseudo_dma_write - write bulk data on pseudo-DMA mode
362 * @count: data length to transfer in bytes
364 * data size must be aligned to 6 bytes to ensure the 24bit alignment on DSP.
365 * NB: call with a certain lock!
367 static void vxp_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
368 vx_pipe_t *pipe, int count)
370 long port = vxp_reg_addr(chip, VX_DMA);
371 int offset = pipe->hw_ptr;
372 unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
374 vx_setup_pseudo_dma(chip, 1);
375 if (offset + count > pipe->buffer_bytes) {
376 int length = pipe->buffer_bytes - offset;
378 length >>= 1; /* in 16bit words */
379 /* Transfer using pseudo-dma. */
380 while (length-- > 0) {
381 outw(cpu_to_le16(*addr), port);
384 addr = (unsigned short *)runtime->dma_area;
387 pipe->hw_ptr += count;
388 count >>= 1; /* in 16bit words */
389 /* Transfer using pseudo-dma. */
390 while (count-- > 0) {
391 outw(cpu_to_le16(*addr), port);
394 vx_release_pseudo_dma(chip);
399 * vx_pseudo_dma_read - read bulk data on pseudo DMA mode
400 * @offset: buffer offset in bytes
401 * @count: data length to transfer in bytes
403 * the read length must be aligned to 6 bytes, as well as write.
404 * NB: call with a certain lock!
406 static void vxp_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
407 vx_pipe_t *pipe, int count)
409 struct snd_vxpocket *pchip = (struct snd_vxpocket *)chip;
410 long port = vxp_reg_addr(chip, VX_DMA);
411 int offset = pipe->hw_ptr;
412 unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
414 snd_assert(count % 2 == 0, return);
415 vx_setup_pseudo_dma(chip, 0);
416 if (offset + count > pipe->buffer_bytes) {
417 int length = pipe->buffer_bytes - offset;
419 length >>= 1; /* in 16bit words */
420 /* Transfer using pseudo-dma. */
422 *addr++ = le16_to_cpu(inw(port));
423 addr = (unsigned short *)runtime->dma_area;
426 pipe->hw_ptr += count;
427 count >>= 1; /* in 16bit words */
428 /* Transfer using pseudo-dma. */
430 *addr++ = le16_to_cpu(inw(port));
432 pchip->regDIALOG &= ~VXP_DLG_DMAREAD_SEL_MASK;
433 vx_outb(chip, DIALOG, pchip->regDIALOG);
434 /* Read the last word (16 bits) */
435 *addr = le16_to_cpu(inw(port));
436 /* Disable 16-bit accesses */
437 pchip->regDIALOG &= ~VXP_DLG_DMA16_SEL_MASK;
438 vx_outb(chip, DIALOG, pchip->regDIALOG);
439 /* HREQ pin disabled. */
440 vx_outb(chip, ICR, 0);
445 * write a codec data (24bit)
447 static void vxp_write_codec_reg(vx_core_t *chip, int codec, unsigned int data)
451 /* Activate access to the corresponding codec register */
453 vx_inb(chip, LOFREQ);
455 vx_inb(chip, CODEC2);
457 /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
458 for (i = 0; i < 24; i++, data <<= 1)
459 vx_outb(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
461 /* Terminate access to codec registers */
462 vx_inb(chip, HIFREQ);
467 * vx_set_mic_boost - set mic boost level (on vxp440 only)
468 * @boost: 0 = 20dB, 1 = +38dB
470 void vx_set_mic_boost(vx_core_t *chip, int boost)
472 struct snd_vxpocket *pchip = (struct snd_vxpocket *)chip;
475 if (chip->chip_status & VX_STAT_IS_STALE)
478 spin_lock_irqsave(&chip->lock, flags);
479 if (pchip->regCDSP & P24_CDSP_MICS_SEL_MASK) {
482 pchip->regCDSP &= ~P24_CDSP_MIC20_SEL_MASK;
483 pchip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
485 /* minimum value: 20 dB */
486 pchip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
487 pchip->regCDSP &= ~P24_CDSP_MIC38_SEL_MASK;
489 vx_outb(chip, CDSP, pchip->regCDSP);
491 spin_unlock_irqrestore(&chip->lock, flags);
495 * remap the linear value (0-8) to the actual value (0-15)
497 static int vx_compute_mic_level(int level)
500 case 5: level = 6 ; break;
501 case 6: level = 8 ; break;
502 case 7: level = 11; break;
503 case 8: level = 15; break;
510 * vx_set_mic_level - set mic level (on vxpocket only)
511 * @level: the mic level = 0 - 8 (max)
513 void vx_set_mic_level(vx_core_t *chip, int level)
515 struct snd_vxpocket *pchip = (struct snd_vxpocket *)chip;
518 if (chip->chip_status & VX_STAT_IS_STALE)
521 spin_lock_irqsave(&chip->lock, flags);
522 if (pchip->regCDSP & VXP_CDSP_MIC_SEL_MASK) {
523 level = vx_compute_mic_level(level);
524 vx_outb(chip, MICRO, level);
526 spin_unlock_irqrestore(&chip->lock, flags);
531 * change the input audio source
533 static void vxp_change_audio_source(vx_core_t *_chip, int src)
535 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
538 case VX_AUDIO_SRC_DIGITAL:
539 chip->regCDSP |= VXP_CDSP_DATAIN_SEL_MASK;
540 vx_outb(chip, CDSP, chip->regCDSP);
542 case VX_AUDIO_SRC_LINE:
543 chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
544 if (_chip->type == VX_TYPE_VXP440)
545 chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
547 chip->regCDSP &= ~VXP_CDSP_MIC_SEL_MASK;
548 vx_outb(chip, CDSP, chip->regCDSP);
550 case VX_AUDIO_SRC_MIC:
551 chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
552 /* reset mic levels */
553 if (_chip->type == VX_TYPE_VXP440) {
554 chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
556 chip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
558 chip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
559 vx_outb(chip, CDSP, chip->regCDSP);
561 chip->regCDSP |= VXP_CDSP_MIC_SEL_MASK;
562 vx_outb(chip, CDSP, chip->regCDSP);
563 vx_outb(chip, MICRO, vx_compute_mic_level(chip->mic_level));
570 * change the clock source
571 * source = INTERNAL_QUARTZ or UER_SYNC
573 static void vxp_set_clock_source(vx_core_t *_chip, int source)
575 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
577 if (source == INTERNAL_QUARTZ)
578 chip->regCDSP &= ~VXP_CDSP_CLOCKIN_SEL_MASK;
580 chip->regCDSP |= VXP_CDSP_CLOCKIN_SEL_MASK;
581 vx_outb(chip, CDSP, chip->regCDSP);
588 static void vxp_reset_board(vx_core_t *_chip, int cold_reset)
590 struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
601 struct snd_vx_ops snd_vxpocket_ops = {
604 .test_and_ack = vxp_test_and_ack,
605 .validate_irq = vxp_validate_irq,
606 .write_codec = vxp_write_codec_reg,
607 .reset_codec = vxp_reset_codec,
608 .change_audio_source = vxp_change_audio_source,
609 .set_clock_source = vxp_set_clock_source,
610 .load_dsp = vxp_load_dsp,
611 .add_controls = vxp_add_mic_controls,
612 .reset_dsp = vxp_reset_dsp,
613 .reset_board = vxp_reset_board,
614 .dma_write = vxp_dma_write,
615 .dma_read = vxp_dma_read,