/* * linux/include/asm-arm/arch-omap/hardware.h * * Hardware definitions for TI OMAP processors and boards * * NOTE: Please put device driver specific defines into a separate header * file for each driver. * * Copyright (C) 2001 RidgeRun, Inc. * Author: RidgeRun, Inc. Greg Lonnon * * Reorganized for Linux-2.6 by Tony Lindgren * and Dirk Behme * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __ASM_ARCH_OMAP_HARDWARE_H #define __ASM_ARCH_OMAP_HARDWARE_H #include #include #ifndef __ASSEMBLER__ #include #include #endif #include /* * --------------------------------------------------------------------------- * Common definitions for all OMAP processors * NOTE: Put all processor or board specific parts to the special header * files. * --------------------------------------------------------------------------- */ /* * ---------------------------------------------------------------------------- * Clocks * ---------------------------------------------------------------------------- */ #define CLKGEN_REG_BASE (0xfffece00) #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) #define CK_RATEF 1 #define CK_IDLEF 2 #define CK_ENABLEF 4 #define CK_SELECTF 8 #define SETARM_IDLE_SHIFT /* DPLL control registers */ #define DPLL_CTL (0xfffecf00) /* DSP clock control */ #define DSP_CONFIG_REG_BASE (0xe1008000) #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) /* * --------------------------------------------------------------------------- * UPLD * --------------------------------------------------------------------------- */ #define ULPD_REG_BASE (0xfffe0800) #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) /* * --------------------------------------------------------------------------- * Timers * --------------------------------------------------------------------------- */ #define OMAP_32kHz_TIMER_BASE 0xfffb9000 /* 32k Timer Registers */ #define TIMER32k_CR 0x08 #define TIMER32k_TVR 0x00 #define TIMER32k_TCR 0x04 /* 32k Timer Control Register definition */ #define TIMER32k_TSS (1<<0) #define TIMER32k_TRB (1<<1) #define TIMER32k_INT (1<<2) #define TIMER32k_ARL (1<<3) /* MPU Timer base addresses */ #define OMAP_TIMER1_BASE (0xfffec500) #define OMAP_TIMER2_BASE (0xfffec600) #define OMAP_TIMER3_BASE (0xfffec700) #define OMAP_MPUTIMER_BASE OMAP_TIMER1_BASE #define OMAP_MPUTIMER_OFFSET 0x100 /* MPU Timer Registers */ #define OMAP_TIMER1_CNTL (OMAP_TIMER_BASE1 + 0x0) #define OMAP_TIMER1_LOAD_TIM (OMAP_TIMER_BASE1 + 0x4) #define OMAP_TIMER1_READ_TIM (OMAP_TIMER_BASE1 + 0x8) #define OMAP_TIMER2_CNTL (OMAP_TIMER_BASE2 + 0x0) #define OMAP_TIMER2_LOAD_TIM (OMAP_TIMER_BASE2 + 0x4) #define OMAP_TIMER2_READ_TIM (OMAP_TIMER_BASE2 + 0x8) #define OMAP_TIMER3_CNTL (OMAP_TIMER_BASE3 + 0x0) #define OMAP_TIMER3_LOAD_TIM (OMAP_TIMER_BASE3 + 0x4) #define OMAP_TIMER3_READ_TIM (OMAP_TIMER_BASE3 + 0x8) /* CNTL_TIMER register bits */ #define MPUTIM_FREE (1<<6) #define MPUTIM_CLOCK_ENABLE (1<<5) #define MPUTIM_PTV_MASK (0x7<