mtmsr r0
/* If switching to PLL1, disable HID0:BTIC */
- cmpli cr0,r3,0
+ cmplwi cr0,r3,0
beq 1f
mfspr r5,HID0
rlwinm r5,r5,0,27,25
stw r4,nap_save_hid1@l(r6)
/* If switching to PLL0, enable HID0:BTIC */
- cmpli cr0,r3,0
+ cmplwi cr0,r3,0
bne 1f
mfspr r5,HID0
ori r5,r5,HID0_BTIC
ori r9,r9,mmu_hash_lock@l
tophys(r9,r9)
10: lwarx r7,0,r9
- cmpi 0,r7,0
+ cmpwi 0,r7,0
bne- 10b
stwcx. r8,0,r9
bne- 10b
ori r9,r9,mmu_hash_lock@l
tophys(r9,r9)
10: lwarx r7,0,r9
- cmpi 0,r7,0
+ cmpwi 0,r7,0
bne- 10b
stwcx. r8,0,r9
bne- 10b
#else
mfspr r3,PVR
rlwinm r3,r3,16,16,31
- cmpi 0,r3,1
+ cmpwi 0,r3,1
beqlr /* for 601, do nothing */
/* 603/604 processor - use invalidate-all bit in HID0 */
mfspr r3,HID0
* flush_icache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_icache_range)
- mfspr r5,PVR
- rlwinm r5,r5,16,16,31
- cmpi 0,r5,1
- beqlr /* for 601, do nothing */
+BEGIN_FTR_SECTION
+ blr /* for 601, do nothing */
+END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
li r5,L1_CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
* void __flush_dcache_icache(void *page)
*/
_GLOBAL(__flush_dcache_icache)
- mfspr r5,PVR
- rlwinm r5,r5,16,16,31
- cmpi 0,r5,1
- beqlr /* for 601, do nothing */
+BEGIN_FTR_SECTION
+ blr /* for 601, do nothing */
+END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
rlwinm r3,r3,0,0,19 /* Get page base address */
li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
mtctr r4
* void __flush_dcache_icache_phys(unsigned long physaddr)
*/
_GLOBAL(__flush_dcache_icache_phys)
- mfspr r5,PVR
- rlwinm r5,r5,16,16,31
- cmpi 0,r5,1
- beqlr /* for 601, do nothing */
+BEGIN_FTR_SECTION
+ blr /* for 601, do nothing */
+END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
mfmsr r10
rlwinm r0,r10,0,28,26 /* clear DR */
mtmsr r0
li r4,0 /* new sp (unused) */
li r0,__NR_clone
sc
- cmpi 0,r3,0 /* parent or child? */
+ cmpwi 0,r3,0 /* parent or child? */
bne 1f /* return if parent */
li r0,0 /* make top-level stack frame */
stwu r0,-16(r1)