* Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
*/
-#include <linux/config.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/pci.h>
+#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
static struct ioc3_submodule *ioc3_submodules[IOC3_MAX_SUBMODULES];
static struct ioc3_submodule *ioc3_ethernet;
-static rwlock_t ioc3_submodules_lock = RW_LOCK_UNLOCKED;
+static DEFINE_RWLOCK(ioc3_submodules_lock);
/* NIC probing code */
return intrs;
}
-static irqreturn_t ioc3_intr_io(int irq, void *arg, struct pt_regs *regs)
+static irqreturn_t ioc3_intr_io(int irq, void *arg)
{
unsigned long flags;
- struct ioc3_driver_data *idd = (struct ioc3_driver_data *)arg;
+ struct ioc3_driver_data *idd = arg;
int handled = 1, id;
unsigned int pending;
if(ioc3_ethernet && idd->active[ioc3_ethernet->id] &&
ioc3_ethernet->intr) {
handled = handled && !ioc3_ethernet->intr(ioc3_ethernet,
- idd, 0, regs);
+ idd, 0);
}
}
pending = get_pending_intrs(idd); /* look at the IO IRQs */
write_ireg(idd, ioc3_submodules[id]->irq_mask,
IOC3_W_IEC);
if(!ioc3_submodules[id]->intr(ioc3_submodules[id],
- idd, pending & ioc3_submodules[id]->irq_mask,
- regs))
+ idd, pending & ioc3_submodules[id]->irq_mask))
pending &= ~ioc3_submodules[id]->irq_mask;
if (ioc3_submodules[id]->reset_mask)
write_ireg(idd, ioc3_submodules[id]->irq_mask,
return handled?IRQ_HANDLED:IRQ_NONE;
}
-static irqreturn_t ioc3_intr_eth(int irq, void *arg, struct pt_regs *regs)
+static irqreturn_t ioc3_intr_eth(int irq, void *arg)
{
unsigned long flags;
struct ioc3_driver_data *idd = (struct ioc3_driver_data *)arg;
read_lock_irqsave(&ioc3_submodules_lock, flags);
if(ioc3_ethernet && idd->active[ioc3_ethernet->id]
&& ioc3_ethernet->intr)
- handled = handled && !ioc3_ethernet->intr(ioc3_ethernet, idd, 0,
- regs);
+ handled = handled && !ioc3_ethernet->intr(ioc3_ethernet, idd, 0);
read_unlock_irqrestore(&ioc3_submodules_lock, flags);
return handled?IRQ_HANDLED:IRQ_NONE;
}
pci_set_master(pdev);
#ifdef USE_64BIT_DMA
- ret = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
+ ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
if (!ret) {
- ret = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
+ ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
if (ret < 0) {
printk(KERN_WARNING "%s: Unable to obtain 64 bit DMA "
"for consistent allocations\n",
writel(~0, &idd->vma->eisr);
idd->dual_irq = 1;
- if (!request_irq(pdev->irq, ioc3_intr_eth, SA_SHIRQ,
+ if (!request_irq(pdev->irq, ioc3_intr_eth, IRQF_SHARED,
"ioc3-eth", (void *)idd)) {
idd->irq_eth = pdev->irq;
} else {
"%s : request_irq fails for IRQ 0x%x\n ",
__FUNCTION__, pdev->irq);
}
- if (!request_irq(pdev->irq+2, ioc3_intr_io, SA_SHIRQ,
+ if (!request_irq(pdev->irq+2, ioc3_intr_io, IRQF_SHARED,
"ioc3-io", (void *)idd)) {
idd->irq_io = pdev->irq+2;
} else {
__FUNCTION__, pdev->irq+2);
}
} else {
- if (!request_irq(pdev->irq, ioc3_intr_io, SA_SHIRQ,
+ if (!request_irq(pdev->irq, ioc3_intr_io, IRQF_SHARED,
"ioc3", (void *)idd)) {
idd->irq_io = pdev->irq;
} else {