+ if (irq > 31)
+ if (irq > 63) /* mask GPP irq */
+ mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
+ ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
+ else /* mask high interrupt register */
+ mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
+ ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
+ else /* mask low interrupt register */
+ mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
+ ppc_cached_irq_mask[0] &= ~(1 << irq));
+
+ (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
+ return;
+}
+
+static irqreturn_t
+gt64260_cpu_error_int_handler(int irq, void *dev_id)
+{
+ printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n",
+ "Error on CPU interface - Cause regiser",
+ mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
+ printk(KERN_ERR "\tCPU error register dump:\n");
+ printk(KERN_ERR "\tAddress low 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
+ printk(KERN_ERR "\tAddress high 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
+ printk(KERN_ERR "\tData low 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
+ printk(KERN_ERR "\tData high 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
+ printk(KERN_ERR "\tParity 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
+ mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+gt64260_pci_error_int_handler(int irq, void *dev_id)
+{
+ u32 val;
+ unsigned int pci_bus = (unsigned int)dev_id;
+
+ if (pci_bus == 0) { /* Error on PCI 0 */
+ val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
+ printk(KERN_ERR "%s: Error in PCI %d Interface\n",
+ "gt64260_pci_error_int_handler", pci_bus);
+ printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
+ printk(KERN_ERR "\tCause register 0x%08x\n", val);
+ printk(KERN_ERR "\tAddress Low 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
+ printk(KERN_ERR "\tAddress High 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
+ printk(KERN_ERR "\tAttribute 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
+ printk(KERN_ERR "\tCommand 0x%08x\n",
+ mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
+ mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);