+ if (ext_model >= OPTERON_CPU_REV_F) {
+ /* 27 shift, is 128Mib minimum DIMM size in REV F and later
+ * upto 8 Gb, in a step function progression
+ */
+ static u32 rev_f_shift[] = { 27, 28, 29, 29, 29, 30, 30, 31,
+ 31, 32, 32, 33, 0, 0, 0, 0 };
+ nr_pages = 1 << (rev_f_shift[shift] - PAGE_SHIFT);
+ } else {
+ /* REV E and less section This line is tricky.
+ * It collapses the table used by revision D and later to one
+ * that matches revision CG and earlier
+ */
+ shift -= (ext_model >= OPTERON_CPU_REV_D)?
+ (shift > 8 ? 4:
+ (shift > 5 ? 3:
+ (shift > 2 ? 1 : 0))): 0;
+ /* 25 shift, is 32MiB minimum DIMM size in REV E and prior */
+ nr_pages = 1 << (shift + 25 - PAGE_SHIFT);
+ }
+
+ /* If dual channel then double thememory size of single channel */
+ nr_pages <<= dual_channel_active(pvt->dcl, pvt->node_id);
+
+ debugf0(" nr_pages= %u dual channel_active = %d\n",
+ nr_pages, dual_channel_active(pvt->dcl, pvt->node_id));
+
+ return nr_pages;
+}
+
+/*
+ * determine_parity_enabled()
+ *
+ * NOTE: CPU Revision Dependent code
+ *
+ * determine if Parity is Enabled
+ */
+static int determine_parity_enabled(struct k8_pvt *pvt)
+{
+ int rc = 0;
+
+ if (pvt->ext_model >= OPTERON_CPU_REV_F) {
+ if (pvt->dcl & BIT(8))
+ rc = 1;
+ }
+
+ return rc;
+}
+
+/*
+* determine_memory_type()
+*
+* NOTE: CPU Revision Dependent code
+*
+* determine the memory type in operation on this controller
+*/
+static enum mem_type determine_memory_type(struct k8_pvt *pvt)
+{
+ enum mem_type type;
+
+ if (pvt->ext_model >= OPTERON_CPU_REV_F) {
+ /* Rev F and later */
+ type = ((pvt->dcl >> 16) & 0x1) ? MEM_DDR2 : MEM_RDDR2;
+ } else {
+ /* Rev E and earlier */
+ type = ((pvt->dcl >> 18) & 0x1) ? MEM_DDR : MEM_RDDR;
+ }
+
+ debugf1(" Memory type is: %s\n",
+ (type == MEM_DDR2) ? "MEM_DDR2" :
+ (type == MEM_RDDR2) ? "MEM_RDDR2" :
+ (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR");
+
+ return type;
+}
+
+/*
+ * determine_dram_type()
+ *
+ * NOTE: CPU Revision Dependent code
+ *
+ * determine the DRAM type in operation
+ * There are K8_NR_CSROWS (8) and 2 CSROWS per DIMM, therefore
+ * there are 4 Logical DIMMs possible, thus 4 bits in the
+ * configuration register indicating whether there are
+ * X4 or X8 devices, one per logical DIMM
+ */
+static enum dev_type determine_dram_type(struct k8_pvt *pvt, int row)
+{
+ int bit;
+ enum dev_type type;
+
+ /* the starting bit depends on Revision value */
+ bit = (pvt->ext_model >= OPTERON_CPU_REV_F) ? 12 : 20;
+ type = ((pvt->dcl >> (bit + (row / 2))) & 0x01) ? DEV_X4 : DEV_X8;
+
+ debugf1(" DRAM type is: %s\n", (type == DEV_X4) ? "DEV-x4" : "DEV-x8");
+
+ return type;
+}
+
+/*
+ * determine_edac_cap()
+ *
+ * NOTE: CPU Revision Dependent code
+ *
+ * determine if the DIMMs have ECC enabled
+ * ECC is enabled ONLY if all the DIMMs are ECC capable
+ */
+static enum edac_type determine_edac_cap(struct k8_pvt *pvt)
+{
+ int bit;
+ enum dev_type edac_cap = EDAC_NONE;
+
+ bit = (pvt->ext_model >= OPTERON_CPU_REV_F) ? 19 : 17;
+ if ((pvt->dcl >> bit) & 0x1) {
+ debugf1(" edac_type is: EDAC_FLAG_SECDED\n");
+ edac_cap = EDAC_FLAG_SECDED;
+ }
+
+ return edac_cap;