X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;ds=sidebyside;f=arch%2Fmips%2Fpci%2Fpci-sb1250.c;h=7cca3bde59b24d09c01d48dd816345c9e5fe89e7;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=8c7c385e4f96f202d678a12064885c92e08685e8;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git

diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 8c7c385e4..7cca3bde5 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2001,2002,2003 Broadcom Corporation
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -36,9 +37,9 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/console.h>
+#include <linux/tty.h>
 
 #include <asm/io.h>
-#include <asm/pci_channel.h>
 
 #include <asm/sibyte/sb1250_defs.h>
 #include <asm/sibyte/sb1250_regs.h>
@@ -89,6 +90,12 @@ int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 	return dev->irq;
 }
 
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+	return 0;
+}
+
 /*
  * Some checks before doing config cycles:
  * In PCI Device Mode, hide everything on bus 0 except the LDT host
@@ -175,28 +182,28 @@ static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 }
 
 struct pci_ops sb1250_pci_ops = {
-	.read = sb1250_pcibios_read,
-	.write = sb1250_pcibios_write
+	.read	= sb1250_pcibios_read,
+	.write	= sb1250_pcibios_write,
 };
 
 static struct resource sb1250_mem_resource = {
 	.name	= "SB1250 PCI MEM",
-	.start	= 0x14000000UL,
-	.end	= 0x17ffffffUL,
+	.start	= 0x40000000UL,
+	.end	= 0x5fffffffUL,
 	.flags	= IORESOURCE_MEM,
 };
-                                                                                
+
 static struct resource sb1250_io_resource = {
-	.name	= "SB1250 IO MEM",
-	.start	= 0x14000000UL,
-	.end	= 0x17ffffffUL,
+	.name	= "SB1250 PCI I/O",
+	.start	= 0x00000000UL,
+	.end	= 0x01ffffffUL,
 	.flags	= IORESOURCE_IO,
 };
 
 struct pci_controller sb1250_controller = {
 	.pci_ops	= &sb1250_pci_ops,
 	.mem_resource	= &sb1250_mem_resource,
-	.io_resource	= &sb1250_io_resource
+	.io_resource	= &sb1250_io_resource,
 };
 
 static int __init sb1250_pcibios_init(void)
@@ -208,9 +215,13 @@ static int __init sb1250_pcibios_init(void)
 	/* CFE will assign PCI resources */
 	pci_probe_only = 1;
 
-	/* set resource limit to avoid errors */
-	ioport_resource.end = 0x0000ffff;	/* 32MB reserved by sb1250 */
-	iomem_resource.end = 0xffffffff;	/* no HT support yet */
+	/* Avoid ISA compat ranges.  */
+	PCIBIOS_MIN_IO = 0x00008000UL;
+	PCIBIOS_MIN_MEM = 0x01000000UL;
+
+	/* Set I/O resource limits.  */
+	ioport_resource.end = 0x01ffffffUL;	/* 32MB accessible by sb1250 */
+	iomem_resource.end = 0xffffffffUL;	/* no HT support yet */
 
 	cfg_space =
 	    ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);