X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;ds=sidebyside;f=include%2Fasm-mips%2Ftitan_dep.h;h=fd9599e40a0ae4e80da1cb023db5b9a46e896503;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=d820445e8ead4d3a4e6f35e2d103323c08f0ec45;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git

diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
index d820445e8..fd9599e40 100644
--- a/include/asm-mips/titan_dep.h
+++ b/include/asm-mips/titan_dep.h
@@ -16,25 +16,19 @@
 #include <asm/addrspace.h>              /* for KSEG1ADDR() */
 #include <asm/byteorder.h>              /* for cpu_to_le32() */
 
-/* PCI */
-#define	TITAN_PCI_BASE			0xbb000000
-
-#define TITAN_WRITE(ofs, data)  \
-        *(volatile u32 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define TITAN_READ(ofs, data)   \
-        *(data) = le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs)))
-#define TITAN_READ_DATA(ofs)    \
-        le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs)))
-
-#define TITAN_WRITE_16(ofs, data)  \
-        *(volatile u16 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define TITAN_READ_16(ofs, data)   \
-        *(data) = le16_to_cpu(*(volatile u16 *)(TITAN_PCI_BASE+(ofs)))
-
-#define TITAN_WRITE_8(ofs, data)  \
-        *(volatile u8 *)(TITAN_PCI_BASE+(ofs)) = data
-#define TITAN_READ_8(ofs, data)   \
-        *(data) = *(volatile u8 *)(TITAN_PCI_BASE+(ofs))
+#define TITAN_READ(ofs)							\
+	(*(volatile u32 *)(ocd_base+(ofs)))
+#define TITAN_READ_16(ofs)						\
+	(*(volatile u16 *)(ocd_base+(ofs)))
+#define TITAN_READ_8(ofs)						\
+	(*(volatile u8 *)(ocd_base+(ofs)))
+
+#define TITAN_WRITE(ofs, data)						\
+	do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_16(ofs, data)					\
+	do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_8(ofs, data)					\
+	do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
 
 /*
  * PCI specific defines
@@ -45,11 +39,11 @@
 /*
  * HT specific defines
  */
-#define RM9000x2_HTLINK_REG     0xbb000644
-#define RM9000x2_BASE_ADDR      0xbb000000
+#define RM9000x2_HTLINK_REG		0xbb000644
+#define RM9000x2_BASE_ADDR		0xbb000000
 
-#define OCD_BASE                0xfb000000UL
-#define OCD_SIZE                0x3000UL
+#define OCD_BASE			0xfb000000UL
+#define OCD_SIZE			0x3000UL
 
 extern unsigned long ocd_base;