X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=Documentation%2Fcachetlb.txt;h=26bb2b4052cd8729736df2917a0a39b9e2ff3e59;hb=9bf4aaab3e101692164d49b7ca357651eb691cb6;hp=98e4c6c7319d4add84eb458368343f096a50edce;hpb=db216c3d5e4c040e557a50f8f5d35d5c415e8c1c;p=linux-2.6.git

diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt
index 98e4c6c73..26bb2b405 100644
--- a/Documentation/cachetlb.txt
+++ b/Documentation/cachetlb.txt
@@ -132,6 +132,17 @@ changes occur:
 	translations for software managed TLB configurations.
 	The sparc64 port currently does this.
 
+7) void tlb_migrate_finish(struct mm_struct *mm)
+
+	This interface is called at the end of an explicit
+	process migration. This interface provides a hook
+	to allow a platform to update TLB or context-specific
+	information for the address space.
+
+	The ia64 sn2 platform is one example of a platform
+	that uses this interface.
+
+
 Next, we have the cache flushing interfaces.  In general, when Linux
 is changing an existing virtual-->physical mapping to a new value,
 the sequence will be in one of the following forms: