X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=Documentation%2Fkbuild%2Fmakefiles.txt;h=1075e4de239ea089a7bbcfbd966e30d40309be77;hb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;hp=ec817761629df056b0e2ff6eef67a514174415e1;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt index ec8177616..1075e4de2 100644 --- a/Documentation/kbuild/makefiles.txt +++ b/Documentation/kbuild/makefiles.txt @@ -25,6 +25,7 @@ This document describes the Linux kernel Makefiles. --- 4.4 Using C++ for host programs --- 4.5 Controlling compiler options for host programs --- 4.6 When host programs are actually built + --- 4.7 Using hostprogs-$(CONFIG_FOO) === 5 Kbuild clean infrastructure @@ -36,6 +37,8 @@ This document describes the Linux kernel Makefiles. --- 6.5 Building non-kbuild targets --- 6.6 Commands useful for building a boot image --- 6.7 Custom kbuild commands + --- 6.8 Preprocessing linker scripts + --- 6.9 $(CC) support functions === 7 Kbuild Variables === 8 Makefile language @@ -387,7 +390,7 @@ compilation stage. Two steps are required in order to use a host executable. The first step is to tell kbuild that a host program exists. This is -done utilising the variable host-prog. +done utilising the variable hostprogs-y. The second step is to add an explicit dependency to the executable. This can be done in two ways. Either add the dependency in a rule, @@ -402,7 +405,7 @@ Both possibilities are described in the following. built on the build host. Example: - host-progs := bin2hex + hostprogs-y := bin2hex Kbuild assumes in the above example that bin2hex is made from a single c-source file named bin2hex.c located in the same directory as @@ -418,7 +421,7 @@ Both possibilities are described in the following. Example: #scripts/lxdialog/Makefile - host-progs := lxdialog + hostprogs-y := lxdialog lxdialog-objs := checklist.o lxdialog.o Objects with extension .o are compiled from the corresponding .c @@ -438,7 +441,7 @@ Both possibilities are described in the following. Example: #scripts/kconfig/Makefile - host-progs := conf + hostprogs-y := conf conf-objs := conf.o libkconfig.so libkconfig-objs := expr.o type.o @@ -457,7 +460,7 @@ Both possibilities are described in the following. Example: #scripts/kconfig/Makefile - host-progs := qconf + hostprogs-y := qconf qconf-cxxobjs := qconf.o In the example above the executable is composed of the C++ file @@ -468,7 +471,7 @@ Both possibilities are described in the following. Example: #scripts/kconfig/Makefile - host-progs := qconf + hostprogs-y := qconf qconf-cxxobjs := qconf.o qconf-objs := check.o @@ -509,7 +512,7 @@ Both possibilities are described in the following. Example: #drivers/pci/Makefile - host-progs := gen-devlist + hostprogs-y := gen-devlist $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist ( cd $(obj); ./gen-devlist ) < $< @@ -524,18 +527,32 @@ Both possibilities are described in the following. Example: #scripts/lxdialog/Makefile - host-progs := lxdialog - always := $(host-progs) + hostprogs-y := lxdialog + always := $(hostprogs-y) This will tell kbuild to build lxdialog even if not referenced in any rule. +--- 4.7 Using hostprogs-$(CONFIG_FOO) + + A typcal pattern in a Kbuild file lok like this: + + Example: + #scripts/Makefile + hostprogs-$(CONFIG_KALLSYMS) += kallsyms + + Kbuild knows about both 'y' for built-in and 'm' for module. + So if a config symbol evaluate to 'm', kbuild will still build + the binary. In other words Kbuild handle hostprogs-m exactly + like hostprogs-y. But only hostprogs-y is recommend used + when no CONFIG symbol are involved. + === 5 Kbuild clean infrastructure "make clean" deletes most generated files in the src tree where the kernel is compiled. This includes generated files such as host programs. -Kbuild knows targets listed in $(host-progs), $(always), $(extra-y) and -$(targets). They are all deleted during "make clean". +Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always), +$(extra-y) and $(targets). They are all deleted during "make clean". Files matching the patterns "*.[oas]", "*.ko", plus some additional files generated by kbuild are deleted all over the kernel src tree when "make clean" is executed. @@ -547,8 +564,17 @@ Additional files can be specified in kbuild makefiles by use of $(clean-files). clean-files := devlist.h classlist.h When executing "make clean", the two files "devlist.h classlist.h" will -be deleted. Kbuild knows that files specified by $(clean-files) are -located in the same directory as the makefile. +be deleted. Kbuild will assume files to be in same relative directory as the +Makefile except if an absolute path is specified (path starting with '/'). + +To delete a directory hirachy use: + Example: + #scripts/package/Makefile + clean-dirs := $(objtree)/debian/ + +This will delete the directory debian, including all subdirectories. +Kbuild will assume the directories to be in the same relative path as the +Makefile if no absolute path is specified (path does not start with '/'). Usually kbuild descends down in subdirectories due to "obj-* := dir/", but in the architecture makefiles where the kbuild infrastructure @@ -638,15 +664,6 @@ When kbuild executes the following steps are followed (roughly): #arch/i386/Makefile LDFLAGS_vmlinux := -e stext - LDFLAGS_BLOB Options for $(LD) when linking the initramfs blob - - The image used for initramfs is made during the build process. - LDFLAGS_BLOB is used to specify additional flags to be used when - creating the initramfs_data.o file. - Example: - #arch/i386/Makefile - LDFLAGS_BLOB := --format binary --oformat elf32-i386 - OBJCOPYFLAGS objcopy flags When $(call if_changed,objcopy) is used to translate a .o file, @@ -914,6 +931,90 @@ When kbuild executes the following steps are followed (roughly): will be displayed with "make KBUILD_VERBOSE=0". +--- 6.8 Preprocessing linker scripts + + When the vmlinux image is build the linker script: + arch/$(ARCH)/kernel/vmlinux.lds is used. + The script is a preprocessed variant of the file vmlinux.lds.S + located in the same directory. + kbuild knows .lds file and includes a rule *lds.S -> *lds. + + Example: + #arch/i386/kernel/Makefile + always := vmlinux.lds + + #Makefile + export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH) + + The assigment to $(always) is used to tell kbuild to build the + target: vmlinux.lds. + The assignment to $(CPPFLAGS_vmlinux.lds) tell kbuild to use the + specified options when building the target vmlinux.lds. + + When building the *.lds target kbuild used the variakles: + CPPFLAGS : Set in top-level Makefile + EXTRA_CPPFLAGS : May be set in the kbuild makefile + CPPFLAGS_$(@F) : Target specific flags. + Note that the full filename is used in this + assignment. + + The kbuild infrastructure for *lds file are used in several + architecture specific files. + + +--- 6.9 $(CC) support functions + + The kernel may be build with several different versions of + $(CC), each supporting a unique set of features and options. + kbuild provide basic support to check for valid options for $(CC). + $(CC) is useally the gcc compiler, but other alternatives are + available. + + cc-option + cc-option is used to check if $(CC) support a given option, and not + supported to use an optional second option. + + Example: + #arch/i386/Makefile + cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586) + + In the above example cflags-y will be assigned the option + -march=pentium-mmx if supported by $(CC), otherwise -march-i586. + The second argument to cc-option is optional, and if omitted + cflags-y will be assigned no value if first option is not supported. + + cc-option-yn + cc-option-yn is used to check if gcc supports a given option + and return 'y' if supported, otherwise 'n'. + + Example: + #arch/ppc/Makefile + biarch := $(call cc-option-yn, -m32) + aflags-$(biarch) += -a32 + cflags-$(biarch) += -m32 + + In the above example $(biarch) is set to y if $(CC) supports the -m32 + option. When $(biarch) equals to y the expanded variables $(aflags-y) + and $(cflags-y) will be assigned the values -a32 and -m32. + + cc-version + cc-version return a numerical version of the $(CC) compiler version. + The format is where both are two digits. So for example + gcc 3.41 would return 0341. + cc-version is useful when a specific $(CC) version is faulty in one + area, for example the -mregparm=3 were broken in some gcc version + even though the option was accepted by gcc. + + Example: + #arch/i386/Makefile + GCC_VERSION := $(call cc-version) + cflags-y += $(shell \ + if [ $(GCC_VERSION) -ge 0300 ] ; then echo "-mregparm=3"; fi ;) + + In the above example -mregparm=3 is only used for gcc version greater + than or equal to gcc 3.0. + + === 7 Kbuild Variables The top Makefile exports the following variables: